CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future revisions
will occur when appropriate, and changes will be noted in a document history page.
CONTINUITY OF ORDERING PART NUMBERS
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in
this document.
FOR MORE INFORMATION
Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products
and services.
OUR CUSTOMERS
Cypress is for true innovators – in companies both large and small.
Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize
their industries or create new industries with products and solutions that nobody ever thought of before.
ABOUT CYPRESS
Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive,
industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-onchip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance
memories help engineers design differentiated products and get them to market first.
Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators
and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 002-14912 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 19, 2016
Not Recommended for New Designs
The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”,
the company that originally developed the specification, Cypress will continue to offer these products to new and existing
customers.
Preliminary Data Sheet
BCM43236/BCM43236B
GE N E R A L D ESC RIPTION
FEATURES
The BCM43236/BCM43236B is a dual-band (2.4 GHz
and 5 GHz) IEEE 802.11n-compliant MAC/PHY/Radio
complete system-on-a-chip with 2.4 GHz and 5 GHz
internal PAs. The device enables development of USB
2.0- or HSIC-based IEEE 802.11n WLAN client and
router subsystem solutions. The BCM43236/
BCM43236B addresses all WLAN markets that deliver
high throughput and extended range of the Broadcom
second-generation MIMO solution. With MIMO,
information is bidirectional over two or more antennas
simultaneously using the same frequency band thus
providing greater range and increasing throughput,
while maintaining compatibility with legacy IEEE
802.11a/b/g devices. This is accomplished by a
combination of enhanced MAC and PHY
implementations including spatial transmitter/
receiver multiplexing modes and advanced DSP
techniques to improve receive sensitivity.
43236B Enhancements:
256 KB ROM with WLAN driver mapped to support
CPU host offload for low-end SoC platforms. Improved
radio for better band edge and output power
performance. Open Source Linux driver support.
•
•
•
•
The BCM43236/BCM43236B architecture with its fully
integrated dual-band radio transceiver supports 2 × 2
antennas for Layer 2 throughput of over 200 Mbps.
State-of-the-art security is provided by industry
standardized system support for WPA™, WPA2™ (IEEE
802.11i), and hardware-accelerated AES encryption/
decryption, coupled with TKIP and IEEE 802.1X
support. Embedded hardware acceleration enables
increased performance and significant reduction in
host-CPU utilization in both client and access point
configurations. The BCM43236/BCM43236B also
supports Broadcom’s widely accepted and deployed
WPS for ease-of-use wireless secured networks.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.11n-compliant
2.4 GHz and 5 GHz internal PA
Two-stream spatial multiplexing up to 300 Mbps
Uses on-chip OTP (One-Time Programmable) memory
instead of SROM for substantial RBOM savings.
Supports MCS 0–15 and MCS 32 modulation and
coding rates.
Supports 20 MHz and 40 MHz channels with optional
SGI.
Support for STBC in both TX and RX
Greenfield, mixed mode, and legacy modes supported
Full IEEE 802.11a/b/g legacy compatibility with
enhanced performance.
Supports one USB 2.0 host or one 480 MHz HSIC port.
UART and JTAG interface, up to eight GPIOs.
Supports up to 32 MB of serial flash memory.
ARM® Cortex-M3™ CPU core plus 256 KB ROM and
448 KB RAM.
256 KB ROM supports driver ROMLIB of the latest
driver for CPU host offload functionality.
Supports Broadcom’s OneDriver™ software.
Supports WHQL certified drivers for Windows® Vista
32- and 64-bit, Windows® XP, and Windows 2000
operating systems for client applications.
Supports Linux® and VxWorks® for access point and
router applications.
Comprehensive wireless network security support
that includes WPA, WPA2, and AES encryption/
decryption coupled with TKIP and IEEE 802.1X
support.
BCM43236/BCM43236B package: 10 mm x 10 mm
88-pin QFN
A P P LICA T IO NS
• USB 2.0 dongles
• HSIC media modules
43236_43236B-DS103-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203
September 16, 2013
Not Recommended for New Designs
2.4 GHz/5 GHz IEEE802.11n MAC/PHY/Radio Chip
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2013 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or
the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES
THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES,
EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
Not Recommended for New Designs
Figure 1: BCM43236/BCM43236B Block Diagram
BCM43236/BCM43236B Preliminary Data Sheet
Revision History
Revision
Date
Change Description
002-14912 Rev *D
09/19/16
Parts in this Datasheet are not recommended for new designs.
43236_43236B-DS103-R
09/16/13
Updated:
• Table 3: “Signal Descriptions,” on page 22.
43236_43236B-DS102-R
03/06/12
Added:
• Figure 11: “Power Supply Sequence,” on page 37.
43236_43236B-DS101-R
10/14/11
Updated:
• Table 5: “Absolute Maximum Ratings,” on page 26.
43236_43236B-DS100-R
6/24/11
Initial release
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Title_Footer (Optional)
Page 3
Not Recommended for New Designs
Revision History
BCM43236/BCM43236B Preliminary Data Sheet
Table of Contents
Table of Contents
About This Document.....................................................................................................................................8
Purpose and Audience .............................................................................................................................8
Acronyms and Abbreviations ...................................................................................................................8
Technical Support ...........................................................................................................................................8
Section 2: Functional Description ....................................................................................11
Global Functions...........................................................................................................................................11
Power Management ..............................................................................................................................11
Voltage Regulators.................................................................................................................................11
Reset ......................................................................................................................................................11
GPIO Interface........................................................................................................................................11
Bluetooth Coexistence Interface ...........................................................................................................12
OTP.........................................................................................................................................................12
JTAG Interface........................................................................................................................................12
UART Interface.......................................................................................................................................12
Serial Flash Interface..............................................................................................................................12
USB/HSIC Interface ................................................................................................................................13
Crystal Oscillator ....................................................................................................................................14
IEEE 802.11n MAC Description.....................................................................................................................15
IEEE 802.11n PHY Description ......................................................................................................................17
Dual-Band Radio Transceiver .......................................................................................................................19
Receiver Path .........................................................................................................................................19
Transmitter Path ....................................................................................................................................19
Calibration..............................................................................................................................................19
Section 3: Pin Assignments..............................................................................................20
BCM43236/BCM43236B 88-Pin QFN Assignments......................................................................................20
Signals by Pin Number ...........................................................................................................................21
Section 4: Signal and Pin Descriptions .............................................................................22
Package Signal Descriptions .........................................................................................................................22
Strapping Options.........................................................................................................................................26
Section 5: Electrical Characteristics..................................................................................27
Absolute Maximum Ratings .........................................................................................................................27
Recommended Operating Conditions and DC Characteristics ....................................................................28
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 4
Not Recommended for New Designs
Section 1: Introduction......................................................................................................9
BCM43236/BCM43236B Preliminary Data Sheet
Table of Contents
Current Consumption from the 3.3V Supply ...............................................................................................28
Current Consumption from the 1.2V Supply ...............................................................................................28
HSIC Characteristics......................................................................................................................................29
Section 6: RF Specifications .............................................................................................30
2.4 GHz Band General RF Specifications ......................................................................................................30
2.4 GHz Band Receiver RF Specifications .....................................................................................................31
2.4 GHz Band Local Oscillator Specifications ...............................................................................................32
5 GHz Band Receiver RF Specifications ........................................................................................................33
5 GHz Band Transmitter RF Specifications...................................................................................................34
5 GHz Band Local Oscillator Frequency Generator Specifications ..............................................................34
On-Chip Regulator Power Supply Characteristics........................................................................................35
Section 7: Timing Characteristics .....................................................................................36
Reset and Clock Timing Diagram..................................................................................................................36
Serial Flash Timing Diagram .........................................................................................................................37
Section 8: Thermal Information.......................................................................................39
Junction Temperature Estimation and PSIJT Versus ThetaJC .......................................................................39
Section 9: Package Information .......................................................................................40
Section 10: Ordering Information ....................................................................................41
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 5
Not Recommended for New Designs
2.4 GHz Band Transmitter RF Specifications................................................................................................32
BCM43236/BCM43236B Preliminary Data Sheet
List of Figures
List of Figures
Figure 1: BCM43236/BCM43236B Block Diagram..............................................................................................2
Figure 2: MIMO System Diagram Showing 2 × 2 Antenna Configuration ..........................................................9
Figure 3: Functional Block Diagram..................................................................................................................10
Figure 4: USB 2.0 Device/HSIC Core Block Diagram .........................................................................................13
Figure 6: Enhanced MAC Block Diagram ..........................................................................................................16
Figure 7: PHY Block Diagram ............................................................................................................................18
Figure 8: BCM43236/BCM43236B 88-Pin QFN Package ..................................................................................20
Figure 9: Timing for the Optional External Power-On Reset ............................................................................36
Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible).......................................................37
Figure 11: Power Supply Sequence ..................................................................................................................38
Figure 12: BCM43236/BCM43236B Mechanical Drawing................................................................................40
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 6
Not Recommended for New Designs
Figure 5: Recommended Oscillator Configuration ...........................................................................................15
BCM43236/BCM43236B Preliminary Data Sheet
List of Tables
List of Tables
Table 1: Crystal Oscillator Requirements .........................................................................................................14
Table 2: Pin Assignments..................................................................................................................................21
Table 3: Signal Descriptions..............................................................................................................................22
Table 4: Strapping Options ...............................................................................................................................26
Table 6: Recommended Operating Conditions and DC Characteristics ...........................................................28
Table 7: Current Consumption from 3.3V Supply.............................................................................................28
Table 8: Current Consumption from 1.2V Supply.............................................................................................28
Table 9: HSIC Characteristics ............................................................................................................................29
Table 10: 2.4 GHz Band General RF Specifications...........................................................................................30
Table 11: 2.4 GHz Band Receiver RF Specifications..........................................................................................31
Table 12: 2.4 GHz Band Transmitter RF Specifications.....................................................................................32
Table 13: 2.4 GHz Band Local Oscillator Specifications ....................................................................................32
Table 14: 5 GHz Band Receiver RF Specifications.............................................................................................33
Table 15: 5 GHz Band Transmitter RF Specifications........................................................................................34
Table 16: 5 GHz Band Local Oscillator Frequency Generator Specifications....................................................34
Table 17: On-Chip Regulator Power Supply Characteristics.............................................................................35
Table 18: Ext_por and Clock Timing .................................................................................................................36
Table 19: Serial Flash Timing ............................................................................................................................37
Table 20: 88-Pin QFN Thermal Characteristics .................................................................................................39
Table 21: Ordering Information........................................................................................................................41
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 7
Not Recommended for New Designs
Table 5: Absolute Maximum Ratings................................................................................................................27
BCM43236/BCM43236B Preliminary Data Sheet
About This Document
About This Document
Purpose and Audience
Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use.
For a comprehensive list of acronyms and other terms used in Broadcom documents, go to:
http://www.broadcom.com/press/glossary.php.
Technical Support
Broadcom provides customer access to a wide range of information, including technical documentation,
schematic diagrams, product bill of materials, PCB layout information, and software updates through its
customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering
support representative.
In addition, Broadcom provides other product support through its Downloads & Support site
(http://www.broadcom.com/support/).
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 8
Not Recommended for New Designs
This document provides details of the functional, operational, and electrical characteristics of the Broadcom®
BCM43236/BCM43236B. It is intended for hardware design, application, and OEM engineers.
BCM43236/BCM43236B Preliminary Data Sheet
Introduction
Section 1: Introduction
Figure 2: MIMO System Diagram Showing 2 × 2 Antenna Configuration
Employing a native 32-bit bus with Direct Memory Access (DMA) architecture, the BCM43236/BCM43236B
chips offer significant performance improvements in transfer rates, CPU utilization, and flexible support for
USB 2.0 devices.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 9
Not Recommended for New Designs
The BCM43236/BCM43236B chips are the latest innovative chips from Broadcom® based on IEEE 802.11n.
These chips are designed to take current WLAN systems to the next level of higher performance and greater
range with Multiple Input Multiple Output (MIMO) technology, as shown in Figure 2. The IEEE 802.11n
standard more than doubles the spectral efficiency compared to that of current IEEE 802.11a/g WLANs.
BCM43236/BCM43236B Preliminary Data Sheet
Introduction
Figure 3 shows a block diagram of the device.
Not Recommended for New Designs
Figure 3: Functional Block Diagram
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 10
BCM43236/BCM43236B Preliminary Data Sheet
Functional Description
Section 2: Functional Description
Power Management
The BCM43236/BCM43236B chips have been designed with the stringent power consumption requirements of
battery-powered hosts in mind. All areas of the chip design were scrutinized to help reduce power
consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages.
The BCM43236/BCM43236B chips include an advanced Power Management Unit (PMU). The PMU provides
significant power savings by putting the BCM43236/BCM43236B into various power management states
appropriate to the current environment and activities that are being performed. The power management unit
enables and disables internal regulators, switches, and other blocks based on a computation of the required
resources and a table that describes the relationship between resources and the time needed to enable and
disable them. Power-up sequences are fully programmable. Configurable, free-running counters in the PMU
are used to turn on/off individual regulators and power switches. Clock speeds are dynamically changed (or
gated altogether) for the current mode. Slower clock speeds are used wherever possible.
Voltage Regulators
Three Low-Dropout (LDO) regulators and a PMU are integrated into the BCM43236/BCM43236B. All regulators
are programmable via the PMU.
Reset
Resets are generated internally by the BCM43236/BCM43236B. An optional external power-on reset circuit can
be connected to the active-low Ext_por input pin. A 50 ms low pulse is recommended to guarantee that a
sufficiently long reset is applied to all internal circuits, including integrated PHYs. The initialization process loads
all pin-configurable modes, resets all internal processes, and puts the device in the idle state. During
initialization, the clock source input signal must be active, and the 3.3V power supply to the device must be
stable. The external power-on reset overrides the BCM43236/BCM43236B internal reset.
GPIO Interface
There are eight General-Purpose I/O (GPIO) pins provided on the BCM43236/BCM43236B. They are
multiplexed with the control signals. These pins can be used to attach to various external devices. Upon powerup and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output
pins via the GPIO control register. A programmable internal pull-up/pull-down resistor is included on each
GPIO. If a GPIO output enable is not asserted, and the corresponding GPIO signal is not being driven externally,
the GPIO state is determined by its programmable resistor.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 11
Not Recommended for New Designs
Global Functions
BCM43236/BCM43236B Preliminary Data Sheet
Global Functions
A 5-wire handshake interface is provided to enable signalling between the device and an external Bluetooth
device host to manage sharing of the wireless medium for optimum performance. The signals provided are:
• btcx_tx_conf
• btcx_rf_active
• btcx_status
• btcx_prisel
• btcx_freq
Note: These five pins are muxed with the JTAG interface.
OTP
The BCM43236/BCM43236B chips contain an on-chip One-Time-Programmable (OTP) area that can be used for
nonvolatile storage of WLAN information such as a MAC address and other hardware-specific parameters. The
total area available for programming is 2 Kbits.
JTAG Interface
The BCM43236/BCM43236B chips support the IEEE 1149.1 JTAG boundary-scan standard for testing the device
packaging and PCB manufacturing.
UART Interface
One UART interface is provided that can be attached to RS-232 Data Termination Equipment (DTE) for
exchanging and managing data with other serial devices. The UART interface is primarily used for debugging
and development.
Serial Flash Interface
Serial flash is available regardless of whether USB 2.0 operation is enabled or disabled. The flash interface is an
STMicroelectronics®-compatible 4-pin interface.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 12
Not Recommended for New Designs
Bluetooth Coexistence Interface
BCM43236/BCM43236B Preliminary Data Sheet
Global Functions
The BCM43236/BCM43236B USB/HSIC interface can be set to operate as a USB 2.0 port or a High-Speed InterChip (HSIC) port. Features of the interface are:
• USB 2.0 protocol engine:
– Parallel Interface Engine (PIE) between packet buffers and USB transceiver
– Supports up to nine endpoints, including Configurable Control Endpoint 0
• Separate endpoint packet buffers with a 512-byte FIFO buffer each
• Host-to-device communication for bulk, control, and interrupt transfers
• Configuration/status registers
• The HSIC port can communicate with an external HSIC host, such as the BCM5357 and BCM5358.
The various blocks in the USB 2.0 device/HSIC core are shown in Figure 4.
Figure 4: USB 2.0 Device/HSIC Core Block Diagram
The USB 2.0 PHY handles the USB protocol and the serial signaling interface between the host and device. It is
primarily responsible for data transmission and recovery. On the transmit side, data is encoded, along with a
clock, using the NRZI scheme with bit stuffing to ensure that the receiver detects a transition in the data
stream. A SYNC field that precedes each packet enables the receiver to synchronize the data and clock recovery
circuits. On the receive side, the serial data is deserialized, unstuffed, and checked for errors. The recovered
data and clock are then shifted to the clock domain that is compatible with the internal bus logic.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 13
Not Recommended for New Designs
USB/HSIC Interface
BCM43236/BCM43236B Preliminary Data Sheet
Global Functions
The endpoint management unit contains the PIE control logic and the endpoint logic. The PIE interfaces
between the packet buffers and the USB transceiver. It handles packet identification (PID), USB packets, and
transactions.
Endpoints are supported by 512-byte FIFO buffers, one for each IN endpoint and one shared by all OUT
endpoints. Both TX and RX data transfers support a DMA burst of 4, which guarantees low latency and
maximum throughput performance. The RX FIFO can never overflow by design. The maximum USB packet size
cannot be more than 512 bytes.
The BCM43236/BCM43236B can be configured as a USB 2.0 device or as a PHY-less HSIC by selecting the
appropriate strapping option. See Table 4 on page 26 for information on how to select the strapping options.
Crystal Oscillator
Table 1 lists the requirements for the crystal oscillator.
Table 1: Crystal Oscillator Requirements
Parameter
Value
Frequency
Mode
Load capacitance
ESR
Frequency stability
20 MHz
AT cut, fundamental
16 pF
50Ω maximum
±10 ppm at 25°C
±10 ppm at 0°C to +85°C
±3 ppm/year max first year, ±1 ppm thereafter
300 μW maximum
40,000 minimum
< 5 pF
Aging
Drive level
Q-factor
Shunt capacitance
Figure 5 shows the recommended oscillator configuration.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 14
Not Recommended for New Designs
The endpoint logic contains nine uniquely-addressable endpoints. These endpoints are the source or sink of
communication flow between the host and the device. Endpoint zero is used as a default control port for both
the input and output directions. The USB system software uses this default control method to initialize and
configure the device information, and allows USB status and control access. Endpoint zero is always accessible
after a device is attached, powered, and reset.
BCM43236/BCM43236B Preliminary Data Sheet
IEEE 802.11n MAC Description
IEEE 802.11n MAC Description
The IEEE 802.11n MAC features include:
• Enhanced MAC for supporting IEEE 802.11n features
• Programmable Access Point (AP) or Station (STA) functionality
• Programmable Independent Basic Service Set (IBSS) or infrastructure mode
• Aggregated MPDU (MAC Protocol Data Unit) support for High-throughput (HT)
• Passive scanning
• Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF)
functionality
• RTS/CTS procedure
• Transmission of response frames (ACK/CTS)
• Address filtering of receive frames as specified by IBSS rules
• Multirate support
• Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation and
programmable Announcement Traffic Indication Message (ATIM) window
• CF conformance: Setting NAV for neighborhood Point Coordination Function (PCF) operation
• Security through a variety of encryption schemes including WEP, TKIP, AES, WPA™, WAP2™, and
IEEE 802.1X
• Power management
• Statistics counters for MIB support
The MAC core supports the transmission and reception of sequences of packets, together with related timing,
without any packet-by-packet driver interaction. Time-critical tasks requiring response times of only a few
milliseconds are handled in the MAC core. This achieves the required timing on the medium while keeping the
host driver easier to write and maintain. Also, incoming packets are buffered in the MAC core, which allows the
MAC driver to process them in bursts, enabling high bandwidth performance.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 15
Not Recommended for New Designs
Figure 5: Recommended Oscillator Configuration
BCM43236/BCM43236B Preliminary Data Sheet
IEEE 802.11n MAC Description
The MAC driver interacts with the MAC core to prepare queues of packets to transmit and to analyze and
forward received packets to upper software layers. The internal blocks of the MAC core are connected to a
Programmable State Machine (PSM) through the host interface that connects to the internal bus (see
Figure 6).
The host interface consists of registers for controlling and monitoring the status of the MAC core and
interfacing with the TX/RX FIFOs. For transmit, a total of 128 KB FIFO buffering is available that can be
dynamically allocated to six transmit queues plus template space for beacons, ACKs, and probe responses.
Whenever the host has a frame to transmit, the host queues the frame into one of the transmit FIFOs with a
TX descriptor containing TX control information. The PSM schedules the transmission on the medium
depending on the frame type, transmission rules in IEEE 802.11 protocol, and the current medium occupancy
scenario. After the transmission is completed, a TX status is returned to the host, informing the host of the
result that got transmitted.
The MAC contains a single 10 KB RX FIFO. When a frame is received, it is sent to the host along with an RX
descriptor that contains additional information about the frame reception conditions.
The power management block maintains the information regarding the power management state of the core
(and the associated STAs in case of an AP) to help in dynamic decisions by the core regarding frame
transmission.
The wireless security engine performs the required encryption/decryption on the TX/RX frames. This block
supports separate transmit and receive keys with four shared keys and 50 link-specific keys. The link-specific
keys are used to establish a secure link between any two STAs, with the required key being shared between
only those two STAs, hence excluding all of the other STAs in the same network from deciphering the
communication between those two STAs. The wireless security engine supports the following encryption
schemes that can be selected on a per-destination basis:
• None: The wireless security engine acts as a pass-through
• WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std. 802.11-2007
• WEP128: 104-bit secure key and 24-bit IV
• TKIP: IEEE Std. 802.11-2007
• AES: IEEE Std. 802.11-2007
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 16
Not Recommended for New Designs
Figure 6: Enhanced MAC Block Diagram
BCM43236/BCM43236B Preliminary Data Sheet
IEEE 802.11n PHY Description
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the
encryption engine and the addition of an FCS (CRC-32) as required by IEEE 802.11-2007. Similarly, the receive
engine is responsible for byte flow from the PHY interface to the RX FIFO through the decryption engine and
for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE Std. 802.11-2007.
IEEE 802.11n PHY Description
The PHY features include:
• Programmable data rates from MCS 0–15 in 20 MHz and 40 MHz channels, as specified in IEEE 802.11n.
• Support for Short Guard Interval (SGI) and Space-Time Block Coding (STBC)
• All scrambling, encoding, forward error correction, and modulation in the transmit direction, and inverse
operations in the receive direction
• Advanced digital signal processing technology for best-in-class receive sensitivity
• Both mixed-mode and optional greenfield preamble of IEEE 802.11n
• Both long and optional short preambles of IEEE 802.11b
• Resistance to multipath (>250 nanoseconds RMS delay spread) with maximal ratio combining for high
throughput and range performance, including improved performance in legacy mode over existing IEEE
802.11a/b/g solutions.
• Automatic Gain Control (AGC)
• Available per-packet channel quality and signal strength measurements
The dual PHYs integrated in the BCM43236/BCM43236B chips provide baseband processing at all mandatory
data rates specified in IEEE 802.11n up to 300 Mbps, and the legacy rates specified in IEEE 802.11a/b/g
including 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps. This core acts as an intermediary between the MAC
and the dual-band 2.4/5 GHz radio, converting back and forth between packets and baseband waveforms.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 17
Not Recommended for New Designs
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for
both transmission and reception. The PSM also maintains the statistics counters required for MIB support.
BCM43236/BCM43236B Preliminary Data Sheet
IEEE 802.11n PHY Description
Not Recommended for New Designs
Figure 7: PHY Block Diagram
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 18
BCM43236/BCM43236B Preliminary Data Sheet
Dual-Band Radio Transceiver
Dual-Band Radio Transceiver
Integrated into the BCM43236/BCM43236B chips is Broadcom's world-class dual-band radio transceiver that
ensures low power consumption and robust communications for low-cost applications operating in the 2.4 GHz
and 5 GHz bands. Channel bandwidths of 20 MHz and 40 MHz are supported as specified in IEEE 802.11n.
The BCM43236/BCM43236B chips have a wide dynamic range, direct conversion receiver. It employs high order
on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII
band. The excellent noise figure of the receiver makes an external LNA unnecessary.
Transmitter Path
Baseband data is modulated and upconverted to the 2.4 GHz ISM band or the 5 GHz U-NII bands, respectively.
Linear on-chip Power Amplifiers are included, which are capable of delivering a nominal output power
exceeding +15 dBm while meeting the IEEE 802.11a and 802.11g specifications. The TX gain has a 78 dB range
with a resolution of 0.25 dB.
Calibration
The BCM43236/BCM43236B chips feature dynamic on-chip calibration, eliminating process variation across
components. This enables the device to be used in high-volume applications because calibration routines are
not required during manufacturing testing. These calibration routines are performed periodically in the course
of normal radio operation.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 19
Not Recommended for New Designs
Receiver Path
BCM43236/BCM43236B Preliminary Data Sheet
Pin Assignments
Section 3: Pin Assignments
BCM43236/BCM43236B 88-Pin QFN Assignments
VDDIO
sflash_cs_l
sflash_q
sflash_c
sflash_d
mimophy_core0_ant0_tx
mimophy_core0_ant0_rx
VDD
mimophy_core1_ant0_tx
mimophy_core1_ant0_rx
VDDIO
VDD
gpio_7
jtag_trst_l
jtag_tdi
jtag_tck
analog_wlan_iqtest_VDD1p2
jtag_tms
jtag_tdo
analog_wlan_iqtest_qp
analog_wlan_iqtest_qn
analog_wlan_iqtest_in
BCM43236/BCM43236B 10 x 10 QFN
VDD
66
mimophy_core1_ant1_rx
65
mimophy_core1_ant1_tx
64
VDDIO
63
UART_RX
62
UART_TX
61
VDD
60
VDDPLL/RF_AVDD_1p2
59
USBLDO_2p5_out
58
LDO_3p3_in
57
VREF
56
PAREF
55
PAREF_CTL1
54
PAREF_CTL2
53
Ext_por
52
xtal_buf_out
51
i_xtal_VDD2p5/o_xtal_VDD2p5 50
xtal_in
49
xtal_out
48
synth_VDD1p2
47
synth_vco_VDD1p2
46
vreg3p3_VDD3p3
45
analog_wlan_iqtest_ip
Gnd
pa_5g_core1_VDD3p3
PA_5g_core1
tx_5g_core1_VDD1p2
rf_5g_antenna_core1
core1_VDD1p2
rf_2g_antenna_core1
tx_2g_core1_VDD1p2
pa_2g_core1_VDD3p3
PA_2g_core1
pa_5g_core0_VDD3p3
PA_5g_core0
tx_5g_core0_VDD1p2
rf_5g_antenna_core0
core0_VDD1p2
rf_2g_antenna_core0
tx_2g_core0_VDD1p2
pa_2g_core0_VDD3p3
PA_2g_core0
gpiao_GPIO_PAD
rcal_res_ext_core
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD
mimophy_core0_ant1_rx
mimophy_core0_ant1_tx
gpio_6
gpio_5
VDDIO
gpio_4
gpio_3
gpio_2
gpio_1
gpio_0
VDD
VDDIO/OTP_VDD
USB_RREF
HSIC_STRB
HSIC_DATA
USB AVDD 1p2
USB_DMNS
USB_DPLS
USB_AVDD3p3
USB_MONCDR
USBAVDD2p5
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 8: BCM43236/BCM43236B 88-Pin QFN Package
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 20
Not Recommended for New Designs
This sections contains pin assignments and ballout information for the BCM43236/BCM43236B (88-pin)
packages.
BCM43236/BCM43236B Preliminary Data Sheet
BCM43236/BCM43236B 88-Pin QFN Assignments
Signals by Pin Number
Pin Signal Name
Pin Signal Name
Pin Signal Name
Pin Signal Name
1
VDDIO
23 analog_wlan_iqtest_ip
46 synth_vco_VDD1p2
68 USB_MONCDR
2
sflash_cs_l
24 Gnd
47 synth_VDD1p2
69 USB_AVDD3p3
3
sflash_q
25 pa_5g_core1_VDD3p3
48 xtal_out
70 USB_DPLS
4
sflash_c
26 PA_5g_core1
49 xtal_in
71 USB_DMNS
5
sflash_d
27 tx_5g_core1_VDD1p2
72 USB AVDD 1p2
6
mimophy_core0_ant0_tx
28 rf_5g_antenna_core1
50 i_xtal_VDD2p5/
o_xtal_VDD2p5
7
mimophy_core0_ant0_rx
29 core1_VDD1p2
51 xtal_buf_out
74 HSIC_STRB
8
VDD
30 rf_2g_antenna_core1
52 Ext_por
75 USB_RREF
mimophy_core1_ant0_tx
31 tx_2g_core1_VDD1p2
53 PAREF_CTL2
76 VDDIO/OTP_VDD
10 mimophy_core1_ant0_rx
32 pa_2g_core1_VDD3p3
54 PAREF_CTL1
77 VDD
11 VDDIO
33 PA_2g_core1
55 PAREF
78 gpio_0
12 VDD
34 pa_5g_core0_VDD3p3
56 VREF
79 gpio_1
13 gpio_7
35 PA_5g_core0
57 LDO_3p3_in
80 gpio_2
14 jtag_trst_l
36 tx_5g_core0_VDD1p2
58 USBLDO_2p5_out
81 gpio_3
15 jtag_tdi
37 rf_5g_antenna_core0
59 VDDPLL/RF_AVDD_1p2
82 gpio_4
16 jtag_tck
38 core0_VDD1p2
60 VDD
83 VDDIO
17 analog_wlan_iqtest_VDD
1p2
39 rf_2g_antenna_core0
61 UART_TX
84 gpio_5
40 tx_2g_core0_VDD1p2
62 UART_RX
85 gpio_6
18 jtag_tms
41 pa_2g_core0_VDD3p3
63 VDDIO
86 mimophy_core0_ant1_tx
19 jtag_tdo
42 PA_2g_core0
64 mimophy_core1_ant1_tx
87 mimophy_core0_ant1_rx
20 analog_wlan_iqtest_qp
43 gpiao_GPIO_PAD
65 mimophy_core1_ant1_rx
88 VDD
21 analog_wlan_iqtest_qn
44 rcal_res_ext_core
66 VDD
22 analog_wlan_iqtest_in
45 vreg3p3_VDD3p3
67 USBAVDD2p5
9
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
73 HSIC_DATA
®
Page 21
Not Recommended for New Designs
Table 2: Pin Assignments
BCM43236/BCM43236B Preliminary Data Sheet
Signal and Pin Descriptions
Section 4: Signal and Pin Descriptions
The signal name, type, and description of each pin in the BCM43236/BCM43236B 88-pin QFN package is listed
in Table 3. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and
the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pulldown resistor), if any. See also Table 4 on page 26 for resistor strapping options.
Table 3: Signal Descriptions
BCM43236/
BCM43236B Type
Signal
Description
Crystal Oscillator
xtal_in
49
I
xtal_out
xtal_buf_out
48
51
O
O
XTAL oscillator input. Connect a 20 MHz, 10 ppm
crystal between the xtal_in and xtal_out pins.
XTAL oscillator output
Buffered XTAL output
2
3
4
5
O (8 mA-PU)
I (8 mA-PU)
O (8 mA-PD)
O (8 mA)
Serial flash chip select
Serial flash data input
Serial flash clock
Serial flash data output
usb_dmns
usb_dpls
usb_rref
71
70
75
I/O
I/O
O
hsic_strb
hsic_data
usb_moncdr
74
73
68
O
I/O
–
USB interface port D–
USB interface port D+
During USB mode, tie this pin in parallel through
a 100 pF capacitor and a 4 kΩ resistor to ground.
During HSIC mode, tie this pin to a 50Ω resistor
to ground.
USB HSIC strobe
USB HSIC data
For test/diagnostic purposes only.
rcal_res_ext_core
44
O
ext_por
52
I
Serial Flash Interface
sflash_cs_l
sflash_q
sflash_c
sflash_d
USB Interface
Miscellaneous Signals
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
Reference output, connect to ground via 15k 1%
resistor.
External power-on reset (POR) input. Active low.
Allows an optional external power-on reset
circuit to be connected. If installed, the external
POR will override the internal POR.
®
Page 22
Not Recommended for New Designs
Package Signal Descriptions
BCM43236/BCM43236B Preliminary Data Sheet
Package Signal Descriptions
Signal
BCM43236/
BCM43236B Type
Description
analog_wlan_iqtest_qp
analog_wlan_iqtest_qn
analog_wlan_iqtest_in
analog_wlan_iqtest_ip
20
21
22
23
–
–
–
–
IQ test pin
IQ test pin
IQ test pin
IQ test pin
mimophy_core0_ant0_tx
mimophy_core0_ant0_rx
6
7
O
mimophy_core0_ant1_tx
mimophy_core0_ant1_rx
86
87
O
mimophy_core1_ant0_tx
mimophy_core1_ant0_rx
9
10
O
mimophy_core1_ant1_tx
mimophy_core1_ant1_rx
64
65
O
Antenna0 TR Switch controls for core 0. These
pins are also used as strapping options, see
Table 4 on page 26.
Antenna1 TR Switch controls for core 0. These
pins are also used as strapping options, see
Table 4 on page 26.
Antenna0 TR Switch controls for core 1. These
pins are also used as strapping options, see
Table 4.
Antenna1 TR Switch controls for core 1. These
pins are also used as strapping options, see
Table 4.
37
28
39
30
35
26
42
33
I
I
I
I
O
O
O
O
Chain 0 RF receive input, 5 GHz band
Chain 1 RF receive input, 5 GHz band
Chain 0 RF receive input, 2.4 GHz band
Chain 1 RF receive input, 2.4 GHz band
Chain 0 RF transmit output, 5 GHz band
Chain 1 RF transmit output, 5 GHz band
Chain 0 RF transmit output, 2.4 GHz band
Chain 1 RF transmit output, 2.4 GHz band
jtag_trst_l
14
I/O
jtag_tck
16
I/O
jtag_tdi
15
I/O
JTAG Reset Input. Resets the JTAG Controller. If
not used, this pin should be pulled low by a 1 kΩ
resistor. This pin is muxed with gpio0.
JTAG Test Clock Input. Used to synchronize JTAG
control and data transfers. If not used, this pin
should be pulled low by a 1 kΩ resistor. This pin
is muxed with btcx_rf_active (Bluetooth
coexistence output, RF active).
JTAG Test Data Input. Serial data input to the
JTAG TAP controller. Sampled on the rising edge
of TCK. If not used, it may be left unconnected.
This pin is muxed with btcx_tx_conf (Bluetooth
coexistence output, WLAN transmit).
RF Control Interface
RF Signal Interface
rf_5g_antenna_core0
rf_5g_antenna_core1
rf_2g_antenna_core0
rf_2g_antenna_core1
pa_5g_core0
pa_5g_core1
pa_2g_core0
pa_2g_core1
JTAG Interface
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 23
Not Recommended for New Designs
Table 3: Signal Descriptions (Cont.)
BCM43236/BCM43236B Preliminary Data Sheet
Package Signal Descriptions
Table 3: Signal Descriptions (Cont.)
BCM43236/
BCM43236B Type
jtag_tdo
19
I/O
jtag_tms
18
I/O
gpio_0
78
I/O
(8 mA)
gpio_1
79
I/O
gpio_2
80
I/O
gpio_3
gpio_4
81
82
I/O
I/O
gpio_5
84
I/O
Description
JTAG Test Data Output. Serial data output from
the JTAG TAP controller. Sampled on the rising
edge of TCK. If not used, it may be left
unconnected. This pin is muxed with btcx_prisel
(Bluetooth coexistence output, antenna select).
JTAG Mode Select Input. Single control input to
the JTAG TAP controller used to traverse the test
logic state machine. Sampled on the rising edge
of TCK. If not used, it may be left unconnected.
This pin is muxed with btcx_status (Bluetooth
coexistence output, status).
GPIO Interface
General Purpose I/O pin. This pin is tristated on
power-up and reset. Subsequently, it becomes
an input or an output through software control.
A programmable PU or PD resistor is available
for each GPIO pin. This pin is muxed with
wlan_led (WLAN LED output).
General Purpose I/O pin. This pin is muxed with
mimophy_core0_ant_shd (antenna switch
control for the shared [middle] antenna of a 2 of
3 design
[core 0]).
General Purpose I/O pin. This pin is muxed with:
• mimophy_core1_ant_shd: antenna switch
control for the shared (middle) antenna of a
2 of 3 design
(core 1).
• btcx_freq: Bluetooth coexistence RF
frequency
General Purpose I/O pin.
General Purpose I/O pin. This pin is muxed with:
• ext_lna_2g_pu_0: 2.4 GHz band core 0
power amplifier control
• ext_pa_2g_0: 2.4 GHz band core 0 power
amplifier control
• CS: SPI select
General Purpose I/O pin. This pin is muxed with:
• ext_lna_2g_pu_1: 2.4 GHz band core 1
power amplifier control
• ext_pa_2g_1: 2.4 GHz band core 1 power
amplifier control
• SCLK: SPI clock
• I2C_SCL: I2C clock
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 24
Not Recommended for New Designs
Signal
BCM43236/BCM43236B Preliminary Data Sheet
Package Signal Descriptions
Table 3: Signal Descriptions (Cont.)
BCM43236/
BCM43236B Type
gpio_6
85
I/O
gpio_7
13
I/O
gpiao_gpio_pad
Description
General Purpose I/O pin. This pin is muxed with:
• ext_lna_5g_pu_0: 5 GHz band core 0 power
amplifier control
• ext_pa_5g_0: 5 GHz band core 0 power
amplifier control)
• SDI: SPI data input
General Purpose I/O pin. This pin is muxed with:
• ext_lna_5g_pu_1: 5 GHz band core 1 power
amplifier control
• ext_pa_5g_1: 5 GHz band core 1 power
amplifier control
• SDO: SPI data output
• I2C_SDA: I2C data
Connect 0.1 F bypass cap
43
–
62
61
I/O (4 mA PU) UART receive data
I/O (4 mA)
UART transmit data
8, 12, 60, 66,
77, 88
1, 11, 63, 83
76
67
58
69
72
47
46
38
29
36
27
40
31
34
25
41
32
PWR
1.2V supply input for the core logic.
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
3.3V supply input for I/O logic
3.3V supply input for I/O logic
USB analog power supply
USB LDO output; decouple to ground.
3.3V supply input to USB interface
1.2V supply input to USB interface
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Analog 1.2V supply input
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
Filtered 3.3V input to internal PA
UART Interface
UART_RX
UART_TX
Power and Ground
vdd
vddio
vddio/otp_vdd
usbavdd2p5
usbldo_2p5_out
usb_avdd3p3
usbavdd1p2
synth_vdd1p2
synth_vco_vdd1p2
core0_vdd1p2
core1_vdd1p2
tx_5g_core0_vdd1p2
tx_5g_core1_vdd1p2
tx_2g_core0_vdd1p2
tx_2g_core1_vdd1p2
pa_5g_core0_vdd3p3
pa_5g_core1_vdd3p3
pa_2g_core0_vdd3p3
pa_2g_core1_vdd3p3
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 25
Not Recommended for New Designs
Signal
BCM43236/BCM43236B Preliminary Data Sheet
Strapping Options
Signal
BCM43236/
BCM43236B Type
Description
analog_wlan_iqtest_vdd_1p2
ldo_3p3_in
vddpll/rf_avdd_1p2
vreg3p3_vdd3p3
i_xtal_vdd2p5/o_xtal_vdd2p5
vref
paref
paref_ctl1
paref_ctl2
gnd_slug
gnd
17
57
59
45
50
56
55
54
53
H
24
1.2V power supply for IQ test.
3.3V input to RF LDO
XTAL power reference; decouple to ground.
Analog 3.3V supply
Connect with bypass cap.
VREF; decouple to ground.
PA reference; decouple to ground.
PA reference control 1
PA reference control 2
Ground
Ground
PWR
PWR
O
PWR
O
–
–
–
–
GND
GND
Strapping Options
The pins listed in Table 4 are sampled at Power-on Reset (POR) to determine the various operating modes.
Sampling occurs within a few milliseconds following internal POR or deassertion of external POR. After POR,
each pin assumes the function specified in the signal descriptions table. Each pin has an internal pull-up (PU)
or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU
resistor to VDDIO or a PD resistor to GND; use 10 kΩ or less (refer to the reference board schematics for further
details).
Table 4: Strapping Options
Signal Name
Mode
Default
Description
mimophy_core0_ant0_tx
OTP select
PU
mimophy_core1_ant0_tx
SFLASH not
present
PD
mimophy_core0_ant0_rx
ST SFLASH
PD
mimophy_core0_ant1_tx
USB PHY
PU
mimophy_core0_ant1_rx
120 MHz
PU
gpio[7:6]
Boot from ROM
No pull
0: No OTP
1: OTP present
0: SFLASH not present
1: SFLASH present
0: SFLASH type is STMicroelectronics
1: SFLASH type is Atmel®
0: HSIC mode
1: USB PHY mode
0: Backplane at 96 (98.4) MHz
1: Backplane at 120 (123) MHz
00: Remap to RAM; ARM processor to be held at
reset.
01: Boot from ROM unless the ARM needs to be
held at reset.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 26
Not Recommended for New Designs
Table 3: Signal Descriptions (Cont.)
BCM43236/BCM43236B Preliminary Data Sheet
Electrical Characteristics
Section 5: Electrical Characteristics
Absolute Maximum Ratings
Caution! The specifications in Table 5 define levels at which permanent damage to the device can
occur. Functional operation is not guaranteed under these conditions. Operation at absolute
maximum conditions for extended periods can adversely affect the long-term reliability of the device.
Table 5: Absolute Maximum Ratings
Rating
Symbol
Minimum
Maximum
Unit
DC supply voltage for core
DC supply voltage for I/O
Voltage on any input or output pin
VDDC
VDDO
VIMAX, VIMIN
–0.5
–0.5
–0.5
+1.4
+3.8
V
V
V
Ambient Temperature (Operating)
TA
0
°C
Operating Junction Temperature 125°C
TJ
–
+65b
125
Operating Humidity
Storage Temperature
–
TSTG
–
–40
85
+125
%
°C
Storage Humidity
ESD Protection
–
VESD
–
–
–
–
–
60
2000
500
150
200
%
V
V
V
mV
(HBM)
(CDM)
(MM)
(LU)
+3.8a
°C
a. The max voltage requirement is to not exceed VDDO + 0.5V when VDDO < 3.3V.
b. The temperature above the shield is 65°C for the TJ to be less than 125°C with a Pout of 15 dBm.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 27
Not Recommended for New Designs
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
BCM43236/BCM43236B Preliminary Data Sheet
Recommended Operating Conditions and DC Characteristics
Recommended Operating Conditions and DC Characteristics
Table 6: Recommended Operating Conditions and DC Characteristics
Value
Symbol
Minimum
Typical
Maximum
Unit
DC supply voltage for I/O
VDDO
DC supply voltage for core and 1.2V analog VDD12
Input low voltage (VDDO = 3.3V)
VIL
2.97
1.14
–
3.3
1.2
–
3.63
1.26
0.8
V
V
V
Input high voltage (VDDO = 3.3V)
VIH
2.0
–
–
V
Output low voltage
VOL
–
–
0.4
V
Output high voltage
VOH
VDDO – 0.4V –
–
V
Not Recommended for New Designs
Element
Current Consumption from the 3.3V Supply
Table 7: Current Consumption from 3.3V Supply
Item
Typical
Maximum
Units
Radio disabled state
Idle and associated state, PM2 mode
Active state, TX or RX, 40 MHz channel, maximum
throughput, PM2 mode
29
120
462
48
148
716
mA
mA
mA
Current Consumption from the 1.2V Supply
Table 8: Current Consumption from 1.2V Supply
Item
Typical
Maximum
Units
Radio disabled state
Idle and associated state, PM2 mode
Active state, TX or RX, 40 MHz channel, maximum
throughput, PM2 mode
47
228
510
68
296
708
mA
mA
mA
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 28
BCM43236/BCM43236B Preliminary Data Sheet
HSIC Characteristics
HSIC Characteristics
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Comments
HSIC signaling voltage
VDD
1.1
1.2
1.3
V
–
I/O voltage input low
VIL
–0.3
–
0.35 × VDD
V
–
I/O Voltage input high
VIH
0.65 × VDD
–
VDD + 0.3
V
–
I/O voltage output low
VOL
–
–
0.25 × VDD
V
–
I/O voltage output high
VOH
0.75 × VDD
–
–
V
–
I/O pad drive strength
OD
40
–
60
Ω
I/O weak keepers
IL
20
–
70
mA
Controlled output
impedance driver
–
I/O input impedance
ZI
100
–
–
kΩ
–
Total capacitive loada
Characteristic trace
impedance
Circuit board trace length
CL
3
–
14
pF
–
TI
45
50
55
Ω
–
TL
–
–
10
cm
–
Circuit board trace
propagation skewb
TS
–
–
15
ps
–
STROBE frequencyc
Slew rate (rise and fall)
STROBE and DATAC
Receiver data setup time
(with respect to STROBE)c
Receiver data hold time
(with respect to STROBE)c
FSTROBE
239.988
240
240.012
MHz
± 500 ppm
Tslew
0.60 × VDD
1.0
1.2
V/ns
Averaged from
30% ~ 70% points
Ts
300
–
–
ps
Measured at the
50% point
Tb
300
–
–
ps
Measured at the
50% point
a. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with
a length of 10 cm.
b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be
matched between STROBE and DATA to ensure that the signal timing is within specification limits at the
receiver.
c. Jitter and duty cycle are not separately specified parameters: they are incorporated into the values in the table
above.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 29
Not Recommended for New Designs
Table 9: HSIC Characteristics
BCM43236/BCM43236B Preliminary Data Sheet
RF Specifications
Section 6: RF Specifications
2.4 GHz Band General RF Specifications
Table 10: 2.4 GHz Band General RF Specifications
Item
Condition
Minimum Typical
Maximum Unit
aRxTxTurnaroundTime
Including switch time
–
2
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
–
μs
®
Page 30
Not Recommended for New Designs
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
BCM43236/BCM43236B Preliminary Data Sheet
2.4 GHz Band Receiver RF Specifications
2.4 GHz Band Receiver RF Specifications
Characteristic
Condition
Cascaded Noise Figure
Minimum Typical
–
–
4.5
@ 1, 2 Mbps
–4
–
Maximum Receive Levela
@ 5.5, 11 Mbps
–10
–
@ 54 Mbps
–10
–
Input IP3
Maximum gain
–
–16
Minimum gain
–
–2
LPF 3 dB Bandwidth
–
8
8.5
PGA DC Rejection Servo Loop Bandwidth WB mode
–
1
NB mode
120 Hz
–
LPF DC Rejection Servo Loop Bandwidth WB mode
–
500
NB mode
120 Hz
–
Maximum Receiver Gain
–
–
88
Gain Control Step
–
–
3
Rx Sensitivity
20 MHz channel spacing for all MCS rates
(10% PER for 4096 octet PSDU) at WLAN MCS0 OFDM
–
–91
RF port. Defined for default parameters:
MCS7 OFDM
–
–74
GF, 800 ns GI, and non-STBC.
MCS8 OFDM
–
–88.5
MCS15 OFDM
–
–69
40 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–88
MCS7 OFDM
–
–71
MCS8 OFDM
–
–85.5
MCS15 OFDM
–
–66
Maximum
Unit
–
–
–
–
–
–
9
–
230 kHz
–
230 kHz
–
–
dB
dBm
dBm
dBm
dBm
dBm
MHz
MHz
–
kHz
–
dB
dB/step
–
–
–
–
dBm
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
a. When using a suitable external switch.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 31
Not Recommended for New Designs
Table 11: 2.4 GHz Band Receiver RF Specifications
BCM43236/BCM43236B Preliminary Data Sheet
2.4 GHz Band Transmitter RF Specifications
2.4 GHz Band Transmitter RF Specifications
Characteristic
Condition
Minimum Typical
Maximum Unit
RF Output Frequency Range
TX Output Power
BCM43236
–
2400
–
2500
MHz
20 MHz BW
–
40 MHz BW
–
20 MHz BW
–
40 MHz BW
–
–
15
fc – 22 MHz < f < fc – 11 MHz
–
fc + 11 MHz < f < fc + 22 MHz
–
f < fc – 22 MHz; and f > fc + 22 MHz –
IEEE 802.11b mode
–
IEEE 802.11g mode
–
–
–
IEEE 802.11b mode
–
IEEE 802.11g mode
–
DC input
–1
–
–
–
–
–
–
–
–
–
–
0.25
12
12
–
16
14.5
18
15.5
–
–30
–30
–50
35%
5%
–
–
–
1
dBm
dBm
dBm
dBm
dBr
dBr
dBr
dBr
–
–
dB/step
MHz
MHz
dB
DC input
–1.5
–
1.5
°C
Shaped pulse
–
0.6
–
Vpp
BCM43236B
Carrier Suppression
TX Spectrum mask @
maximum gain
TX Modulation Accuracy
(EVM) at maximum gain
Gain Control Step Size
I/Q Baseband Bandwidth
Amplitude Balancea
Phase Balancea
Baseband Differential Input
Voltage
a. At a 3 MHz offset from the carrier frequency.
2.4 GHz Band Local Oscillator Specifications
Table 13: 2.4 GHz Band Local Oscillator Specifications
Characteristic
Condition Minimum Typical
Maximum Unit
VCO Frequency Range
Reference Input Frequency Range
Clock Frequency Tolerance
Reference Spurs
Local Oscillator Phase Noise, single-sided from
1 kHz–300 kHz offset
–
–
–
–
–
2484
–
±20
–34
–86.5
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
2412
–
–
–
–
–
20
–
–
–
MHz
MHz
ppm
dBc
dBc/Hz
®
Page 32
Not Recommended for New Designs
Table 12: 2.4 GHz Band Transmitter RF Specifications
BCM43236/BCM43236B Preliminary Data Sheet
5 GHz Band Receiver RF Specifications
5 GHz Band Receiver RF Specifications
Characteristic
Condition
Minimum Typical
Maximum Unit
Cascaded Noise Figure
Maximum RX gain
@ 6 Mbps
–
4.5
–10 (TBV) –
–
–
dB
dBm
@ 54 Mbps
–15 (TBV) –
–
dBm
Maximum LNA gain
Minimum LNA gain
–
WB mode
NB mode
–
–
–
–
–
–
–
–
–
120 Hz
–
–
–
–
–
–
–
–
–
230 kHz
–
–
–
–
–
dBm
dBm
MHz
kHz
–
dB
dB
dB/step
dB
°C
Maximum Receive Levela (5.24 GHz)
Maximum Receive Levela (5.24 GHz)
Input IP3
LPF 3 dB Bandwidth
DC Rejection Servo Loop Bandwidth
(normal operation)
Minimum RX Gain
Maximum RX Gain
Gain Control Step
IQ Amplitude Balance
IQ Phase Balance
–5
–4
8.5
500
–
15
92
3
0.5
1.5
Out-of-Band Blocking Performance without RF Band-Pass Filter (–1 dB desensitization):
CW
CW
CW
Rx Sensitivity
(10% PER for 4096 octet PSDU) at WLAN
RF port. Defined for default parameters:
GF, 800 ns GI, and non-STBC.
30 MHz–4300 MHz
–10 (TBV) –
4300 MHz–4800 MHz –25 (TBV) –
5900 MHz–6400 MHz –25 (TBV) –
20 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–90
MCS7 OFDM
–
–74
MCS8 OFDM
–
–88.5
MCS15 OFDM
–
–69
40 MHz channel spacing for all MCS rates
MCS0 OFDM
–
–87
MCS7 OFDM
–
–71
MCS8 OFDM
–
–86
MCS15 OFDM
–
–66
–
–
–
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
–
–
–
–
dBm
dBm
dBm
dBm
a. With minimum RF gain.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 33
Not Recommended for New Designs
Table 14: 5 GHz Band Receiver RF Specificationsa
BCM43236/BCM43236B Preliminary Data Sheet
5 GHz Band Transmitter RF Specifications
5 GHz Band Transmitter RF Specifications
Table 15: 5 GHz Band Transmitter RF Specifications
Condition
Minimum Typical Maximum Unit
RF Output Frequency Range –
Output Power (EVM-compliant)
BCM43236
20 MHz BW
40 MHz BW
BCM43236B
20 MHz BW
40 MHz BW
Carrier Suppression
–
TX Spectrum mask
f < fc – 11 MHz and f > fc + 11 MHz
(chip output power = 11 dBm) f < fc – 20 MHz and f > fc + 20 MHz
f < fc – 30 MHz and f > fc + 30 MHz
TX Modulation Accuracy (EVM) Po = 11 dBm
TX Modulation Accuracy (EVM) Po = 6 dBm
Gain Control Step Size
–
I/Q Baseband 3 dB Bandwidth –
Amplitude Balance
DC Input
Phase Balance
DC Input
Baseband Differential Input
–
Voltage
TX Power Ramp Up
90% of final power
TX Power Ramp Down
10% of final power
4920
–
5805
MHz
–
–
–
–
–
–
–
–
–
–
–
–
–0.5
–1.5
–
–
–
–
–
–
–
–
–
–25
–33
2
12
–
–
0.7
15
14
16.5
15
TBD
–26
–35
–40
–
–
–
–
0.5
1.5
–
dBm
dBm
dBm
dBm
dBr
dBc
dBr
dBr
dB
dB
dB/step
MHz
dB
°C
Vpp
–
–
–
–
2
2
μsec
μsec
5 GHz Band Local Oscillator Frequency Generator
Specifications
Table 16: 5 GHz Band Local Oscillator Frequency Generator Specifications
Characteristic
Condition
Minimum Typical
Maximum
Unit
VCO Frequency Range
Reference Input Frequency Range
Clock Frequency Tolerance
Reference Spurs
Local Oscillator Integrated Phase
Noise (1 kHz–300 kHz)
–
–
–
–
4.920 GHz–5.700 GHz
5.725 GHz–5.805 GHz
4920
–
–
–
–
–
5805
–
±20
–30
–
–
MHz
MHz
ppm
dBc
°C
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
–
20
–
–
0.7
1.4
®
Page 34
Not Recommended for New Designs
Characteristic
BCM43236/BCM43236B Preliminary Data Sheet
On-Chip Regulator Power Supply Characteristics
On-Chip Regulator Power Supply Characteristics
Table 17: On-Chip Regulator Power Supply Characteristics
Element
Minimum
Typical
Maximum Unit
2.97
2.5
–4
–
–
150
–
20
3.3
2.85
–
–
–
–
–
30
3.63
3.1
+4
40
10
–
100
100
V
V
%
mA
mA
mV
μs
ns
1
1.3
2
ns
2.97
1.2
–4
150
–
–
3.30
–
–
–
–
–
3.63
3.0
+4
–
120
50
V
V
%
mV
mA
μs
2.5V–3.1V PA Reference LDO (default: off)
Vout: 2.5V to 3.1V when output A, B, C and/or D is enabled.
Control Step: 50 mV/step
Input Power Supply
Vout (Note 1) Programmable, 50 mV/step
Absolute Accuracy
Maximum Output Current: A, B, C and D all enabled
Maximum Output Current: any output A, B, C, or D
Dropout Voltage
Startup Time
Switching ON Time (either A or G)
Note: LDO is already powered.
Switching OFF Time (either A or G)
Note: LDO is already powered.
3.3V–1.2V RF LDO
Input power supply, Vbat
Vout (Note 1) Programmable, 50 mV/step
Absolute Accuracy
Dropout Voltage
Maximum Output Current
Startup time with 100 μs VDD
Ramp
3.3V–2.5V USB LDO
Input power supply
2.97
3.30
3.63
V
Vout
2.3
2.5
2.65
V
Absolute accuracy
–4
–
+4
%
Dropout voltage
150
–
–
mV
Maximum output current
–
–
30
mA
Start-up time
–
–
50
μs
Note: It is required that the input supply be at least 200 mV higher than the output. More headroom is better
for PSRR performance.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 35
Not Recommended for New Designs
Value
BCM43236/BCM43236B Preliminary Data Sheet
Timing Characteristics
Section 7: Timing Characteristics
Resets are generated internally by the BCM43236/BCM43236B chips. An optional external Power-On Reset
(POR) circuit can be connected to the active-low Ext_por input pin. The BCM43236/BCM43236B chips are reset
automatically as long as the power supplies are turned on in the following sequence. 3.3V first, 2.5V second,
and 1.2V last.
Figure 9: Timing for the Optional External Power-On Reset
Table 18: Ext_por and Clock Timing
Parameter Description
Minimum Typical
Maximum Units
t201
t202
t203
t204
t207
t208
t209
19.9995
–
–
50
50
1.7
–
20.0000
20
20
–
–
–
3
20.0005
–
–
–
–
2.8
–
MHz
ns
ns
ms
μs
ms
ms
50
–
–
ms
t210
OSCIN frequency
OSCIN high time
OSCIN low time
EXT_POR_L low pulse duration
Configuration valid setup to EXT_POR_L rising
Configuration valid hold from EXT_POR_L rising
EXT_POR_L deassertion to normal switch
operation
Reset low hold time after power supplies
stabilize
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 36
Not Recommended for New Designs
Reset and Clock Timing Diagram
BCM43236/BCM43236B Preliminary Data Sheet
Serial Flash Timing Diagram
Serial Flash Timing Diagram
Table 19: Serial Flash Timing
Parameter
Descriptions
Minimum Typical
Maximum
Units
fSCK
Serial flash clock frequency
–
12.5
66
MHz
tWH
Serial flash clock high time
9
–
–
ns
tWL
Serial flash clock low time
9
–
–
ns
tR, tFa
Clock rise and fall timesb
TBD
–
–
V/ns
tCSS
Chip select active setup time
5
–
–
ns
tCS
Chip select deselect time
100
–
–
ns
tCSH
Chip select hold time
5
–
–
ns
tSU
Data input setup time
2
–
–
ns
tH
Data input hold time
5
–
–
ns
tHO
Data output hold time
0
–
–
ns
tV
Clock low to output valid
–
–
8
ns
a. tR and tF are expressed as a slew-rate.
b. Peak-to-peak
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 37
Not Recommended for New Designs
Figure 10: Serial Flash Timing Diagram (STMicroelectronics-Compatible)
BCM43236/BCM43236B Preliminary Data Sheet
Serial Flash Timing Diagram
Figure 11 shows the power supply sequence.
Figure 11: Power Supply Sequence
3.3V supply
Not Recommended for New Designs
3.3V ramp time
Max 5 ms
1.2V ramp time
Maximum 5 ms
1.2V supply
50% of 3.3V to 50% of 1.2V
5 ms (minimum time)
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 38
BCM43236/BCM43236B Preliminary Data Sheet
Thermal Information
Section 8: Thermal Information
Airflow
0 fpm,
0 mps
100 fpm,
0.508 mps
200 fpm,
1.016 mps
400 fpm,
2.032 mps
600 fpm,
3.048 mps
JA (°C/W)
20.79
17.55
16.24
15.00
14.34
JB (°C/W)
3.95
–
–
–
–
JC (°C/W)
12.44
–
–
–
–
JT (°C/W)
3.51
3.50
3.55
3.59
3.61
Note:
• In the thermal characterizations that were done on BCM43236/BCM43236B chips using a 4-layer
board, the temperature at 1 mm above the shield must be no higher than 65°C in order to keep
the junction temperature (TJ) from exceeding 125°C.
• The BCM43236/BCM43236B chips are designed and rated for operation at a maximum TJ of
125°C.
Junction Temperature Estimation and PSIJT Versus ThetaJC
Package thermal characterization parameter Psi-JT (JT) yields a better estimation of actual junction
temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for
this is JC assumes that all the power is dissipated through the top surface of the package case. In actual
applications, some of the power is dissipated through the bottom and sides of the package. JT takes into
account power dissipated through the top, bottom, and sides of the package. The equation for calculating the
device junction temperature is as follows:
TJ = TT + P JT
Where:
• TJ = junction temperature at steady-state condition, °C
• TT = package case top center temperature at steady-state condition, °C
• P = device power dissipation, Watts
• JT = package thermal characteristics (no airflow), °C/W
Package thermal characterization measurements: The temperature above the shield is 65°C for the TJ to be less
than 125°C with a Pout of 15 dBm.
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 39
Not Recommended for New Designs
Table 20: 88-Pin QFN Thermal Characteristics
BCM43236/BCM43236B Preliminary Data Sheet
Package Information
Section 9: Package Information
Not Recommended for New Designs
Figure 12: BCM43236/BCM43236B Mechanical Drawing
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
®
Page 40
BCM43236/BCM43236B Preliminary Data Sheet
Ordering Information
Section 10: Ordering Information
Table 21: Ordering Information
Package
Temperature @ 1 mm Above the Shield
BCM43236KMLG
BCM43236BKMLG
10 × 10, 88-pin QFN (RoHs compliant)
10 × 10, 88-pin QFN (RoHs compliant)
0°C to 65°C (32°F to 149°F)
0°C to 65°C (32°F to 149°F)
BROADCOM
September 16, 2013 • 43236_43236B-DS103-R
Not Recommended for New Designs
Part Number
®
Page 41
Broadcom® Corporation reserves the right to make changes without further notice to any products
or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,
Broadcom Corporation does not assume any liability arising out of the application or use of this
information, nor the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
®
BROADCOM CORPORATION
5300 California Avenue
Irvine, CA 92617
© 2013 by BROADCOM CORPORATION. All rights reserved.
43236_43236B-DS103-R September 16, 2013
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: info@broadcom.com
Web: www.broadcom.com
Not Recommended for New Designs
BCM43236/BCM43236B Preliminary Data Sheet
工商网监
湘ICP备2023018690号
