DHP1050N10N5AUMA1

100 V OptiMOS™ PowerStage DHPx050N10N5 Features  Symmetrical half-bridge 100V MOSFETs integrated with level-shift driver  100 V OptiMOS™ 5 Power MOSFET technology  (DHP0050N10N5) Independently controlled high-side and low-side gate drivers  (DHP1050N10N5) Differential input for superb robustness with inherent shoot-through protection  Up to 20 A current handling capability  120 V On-chip bootstrap diode  Maximum VDD Voltage 20 V  Support operating frequency up to 1 MHz  VDD/VHB under voltage lockout (UVLO)  -10 V to 20 V input pin capability for increased robustness  ( DHP1050N10N5) -8 V to 15 V input pin common mode rejection  -5 A output pin reverse current capability  8 V to 17 V supply voltage operating range  Fast propagation delay  < 6 ns delay matching between high- and low-side drivers  Small 7.5 mm x 6.0 mm x 0.9 mm PQFN package  Lead free RoHS compliant package Potential applications  Power modules and on-board converters for Telecom  half-bridge and full-bridge converters  Intermediate bus architecture  Synchronous buck converter Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/20/22 Description DHPx050N10N5 is a 100 V half-bridge module designed for advanced DC/DC converter applications such as telecom bus converters. Technology offers an extremely compact, high performance half-bridge topology in an isolated package. This advanced device offers a combination of low RDS(on) and fast switching OptiMOS technology and the optimized half-bridge driver in a small PQFN package. At only 7.5 mm x 6 mm and featuring integrated bootstrap functionality, the compact footprint of this surface-mount package makes it suitable for applications that are space-constrained. Datasheet www.infineon.com Please read the Important Notice and Warnings at the end of this document page 1 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Table of contents Table of contents Features ........................................................................................................................................ 1 Potential applications ..................................................................................................................... 1 Product validation .......................................................................................................................... 1 Description .................................................................................................................................... 1 Table of contents ............................................................................................................................ 2 1 1.1 1.2 Package Information .............................................................................................................. 3 Ordering Information .............................................................................................................................. 3 Module Pin-Out Description.................................................................................................................... 3 2 Block Diagram ....................................................................................................................... 5 3 3.1 3.2 3.3 3.4 3.5 3.6 Functional Description............................................................................................................ 6 Supply Voltage......................................................................................................................................... 6 Input Control ........................................................................................................................................... 6 Driver Outputs ......................................................................................................................................... 7 Under-voltage Lockout (UVLO) ............................................................................................................... 7 Minimum Pulse Width ............................................................................................................................. 7 Transient Detector .................................................................................................................................. 8 4 4.1 4.2 4.3 4.4 4.5 4.6 Characteristics....................................................................................................................... 9 Absolute Maximum Ratings .................................................................................................................... 9 ESD Ratings.............................................................................................................................................. 9 Recommended Operating Conditions .................................................................................................... 9 Static Electrical Characteristics ............................................................................................................ 10 Dynamic Electrical Characteristics ....................................................................................................... 10 Thermal and Mechanical Characteristics ............................................................................................. 11 5 Descriptive Illustration .......................................................................................................... 12 6 Typical Characteristics .......................................................................................................... 13 7 Application and Guidelines ..................................................................................................... 16 7.1 Typical Application Diagram ................................................................................................................. 16 7.2 Design Guidelines .................................................................................................................................. 17 7.2.1 Bootstrap Capacitor Selection ........................................................................................................ 18 7.2.2 VDD Bypass Capacitor Selection...................................................................................................... 19 7.2.3 Bootstrap Resistor Selection ........................................................................................................... 19 7.2.4 External Bootstrap Diode Selection ................................................................................................ 19 7.3 PCB Layout Guidelines .......................................................................................................................... 19 8 8.1 8.2 8.3 8.4 Outline Dimensions ............................................................................................................... 22 PG-IQFN-36-1 Package Outline, 1 of 2 .................................................................................................. 22 PG-IQFN-36-1 Package Outline, 2 of 2 .................................................................................................. 23 PG-IQFN-36-1 Footprint Dimensions .................................................................................................... 24 Top Marking ........................................................................................................................................... 25 Revision history............................................................................................................................. 26 Datasheet 2 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Package Information 1 Package Information PQFN-36 1.1 Ordering Information Standard Pack Base Part Number Package Type DHP0050N10N5 PQFN 7.5 mm x 6 mm Tape and Reel 4000 DHP0050N10N5AUMA1 DHP1050N10N5 PQFN 7.5 mm x 6 mm Tape and Reel 4000 DHP1050N10N5AUMA1 1.2 Form Quantity Orderable Part Number Module Pin-Out Description (Top Transparent View) Figure 1 Datasheet Pin Configuration of PG-IQFN-36-1, Top Transparent View 3 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Package Information Table 1 Pin Description Pin # Pin Name Pin Description 1, 3, 29, 31, 32, 34 NC Leave the pin unconnected or short neighboring VIN plane or ground. 2 HI High side PWM input 4 LI Low side PWM input 10, 11, 22, 23, 33 PGND Power ground. It is also the power ground of the low-side MOSFET. 5 GNDA Driver ground A. All driver power and signals are referenced to this pin.1 6 GNDB Driver ground B. All driver power and signals are referenced to this pin.1 7, 9 LO Low-side MOSFET driver output pin that can be connected to a test point in order to observe the waveform. 8 VDD The supply of gate driver. Connect a 1uF cap between VDD and GNDA. 12-21 SW Switching node of half bridge. 24-28 VIN Up to 100V high current input voltage connection. 30 HO High-side MOSFET driver output pin that can be connected to a test point in order to observe the waveform. 35 HS Phase (switching) node. For Bootstrap capacitor connection only. HB High-side bootstrap. Connect a minimum 0.1µF capacitor from HB to HS pin. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. 36 Due to the benefit of differential input, the driver IC requires no separate ground between signal and power. Therefore, PGND, GNDA, and GNDB are connected internally. Datasheet 4 of 27 Rev. 1.4 2021-07-21 1 100 V OptiMOS™ PowerStage DHPx050N10N5 Block Diagram 2 Block Diagram A simplified functional block diagram is given in the figure below HB HS HO VIN VDD HB UVLO Q1 BANDGAP & REFERENCE VDD3V0 3.3V Regulator POR driver HV Level Shift POR SW HI PWM_HS PADS VDD PWM_LS LI VDD UVLO Q2 driver LV Level Shift GNDA Figure 2 Datasheet GNDB LO PGND Block Diagram 5 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Functional Description 3 Functional Description The device is an integrated power stage designed to support advanced switching converters such as in telecom and datacom applications. The device pairs a level-shifted half-bridge driver with 100 V high-side and low-side symmetrical power MOSFETs. It features 4 A source current for both high-side and low-side and a strong 5 A high-side and 6 A low-side sink current driving capabilities to combat induced turn on. DHP0050N10N5’s input pins support TTL logic levels independently of supply voltage. They are capable to withstand voltages from -10 V to 20 V, allowing the device to interface with a broad range of analog and digital controllers. The input stage features built-in hysteresis for enhanced noise immunity. The low-side and highside gate drivers are independently controlled and matched to typical 2 ns between the turn on and turn off of each other. DHP1050N10N5’s input pins support TTL logic levels independently of supply voltage. They are capable to withstand voltages from -10 V to 20 V and ground potential shifts from -8 V to 15 V, allowing the device to interface with a broad range of analog and digital controllers. The input stage features built-in hysteresis for enhanced noise immunity. The low-side and high-side gate drivers are differentially controlled and matched to typical 2 ns between the turn on and turn off of each other. The differential inputs provide inherent shootthrough protection and ensure high-side and low-side outputs are never on at the same time. The switching node (HS pin) is able to handle negative voltages down to –(24 - VDD) V which allows the high-side channel to be protected from inherent negative voltages caused by parasitic inductance and stray capacitance. Under-voltage lockout circuits are provided for both high- and low-side drivers. UVLO protects the system by forcing the output low when the supply voltage is lower than the specified threshold. The following sections describe key functionalities. 3.1 Supply Voltage The absolute maximum supply voltage is 20 V. The minimum operating supply voltage is set by the undervoltage lockout function to a typical default value of 7.0 V. This lockout function protects power MOSFETs from running into linear mode with subsequent high power dissipation. 3.2 Input Control DHP0050N10N5 device responds to the two inputs signals (HI and LI) independently according to the following truth table. Table 2 DHP0050N10N5 Truth Table LI HI LO HO L L L L H L H L L H L H H H H H The high-side and low-side outputs respond to high-side and low-side inputs independently. DHP1050N10N5 device responds to the combination of two inputs signals (HI and LI) according to the following truth table. Datasheet 6 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Functional Description Table 3 DHP1050N10N5 Truth Table LI HI LO HO L L L L H L H L L H L H H H L L True differential input comes with inherent shoot through protection by preventing both low and high side to be on at the same time. It also provides noise immunity against ground bounce. The input stage is designed to operate reliably against –8 V / +15 V ground voltage drift. Input logic hysteresis also helps combat disturbances to the input signal. 3.3 Driver Outputs The low output impedances allow fast transition of the load transistor. Specifically, the ultra-low impedance pull down resistances, typically 0.5 Ω for the high side and 0.35 Ω for the low side, keep the gate of the load transistor down during fast transient events – avoiding dv/dt induced re-turn-on. 3.4 Under-voltage Lockout (UVLO) The under voltage lockout function ensures that the output can be switched to its high level only if the supply voltage exceeds the UVLO rising threshold voltage. Thus it can be guaranteed, that the switch transistor is not switched on if the driving voltage is too low to completely switch on the device, thereby avoiding excessive power dissipation. The UVLO level is set to a typical value of 7.0 V with 0.5 V hysteresis for supply voltage (VDD) and 5.75 V with 0.25 V hysteresis for high side boot voltage (VHB). UVLO threshold trigger is synchronous. The clock gating ensures minimum pulse width set by the controller is obeyed at all times. This increases robustness of the integrated boot diode due to the controllability of the reverse recovery behavior. 3.5 Minimum Pulse Width TONOUT The device responds to input level according to the truth table in section Input Control as long as the logic signal complies with the minimum pulse width requirement. Signal pulse longer than the minimum allowable input pulse width yields valid output. Any output in response to shorter pulses or glitches should be disregarded and filtered out by the user. Under all allowable operation above input minimum pulse width of 40ns, the output behaves one to one to the input with minimal pulse width distortion. 100 ns 40 ns 40 ns Figure 3 Datasheet 100 ns TONIN Minimum Pulse Width Input-output On-time Transfer Function 7 of 27 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Functional Description This is diagram is illustrative only with typical value. Actual value and pulse width distortion is subject to process variation. Output pulse width could in some case be shortened or extended to prevent retoggling. See transient detector section below. 3.6 Transient Detector The transient detector block is designed to prevent re-toggling of the HO output in case of potential instability of the level shifter caused by phase node movement. For example, a fast-rising phase node voltage could pull the power ground (PGND) down. This could result in potential between HI and PGND higher than the rising threshold of the high-side signal. Such a glitch or noise can be picked up by the driver and propagate through which can lead to a shoot-through event, transformer volt-second imbalance, and potential device destruction. The following describes the basic operation of the block.  The transient detector monitors the phase node and tracks its movement, and the rate of change over time for both rising and falling edge.  Whenever the rate of change is larger than a certain dv/dt threshold1, the transient detector is active and blocks the HO output from changing state.  A High-side Input (HI) toggle triggers a decision to change the state, but HO waits until the transient detector’s active state is removed, then the decision is propagated through. Additional propagation delay caused by the transient detector is limited to one-half of the oscillation period, as the signal always propagates through whenever the transient detector sees a peak or valley where dv/dt approaches zero. See link to Understanding the transient detector [1] for more information. Reference slew rate threshold versus temperature under Section 6 Typical Characteristics Datasheet 8 of 27 1 Rev. 1.4 2021-07-21 100 V OptiMOS™ PowerStage DHPx050N10N5 Characteristics 4 Characteristics 4.1 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Symbol Description Min Max Unit VIN Input Supply Voltage --- 100 V VDD Driver Supply Voltage -0.3 20 V VSW,VHS Phase Voltage -(24 - VDD) VHB + 0.3 V VHB High Side Bootstrap Voltage -0.3 120 V VHI, VLI LI and HI Input Voltage -10 20 V TJ Operating Junction Temperature -40 150 °C VLO Output voltage on LO -0.3 VDD + 0.3 V VHO Output voltage on HO VHS – 0.3 VHB + 0.3 V IOR LO and HO Peak Reverse Current --- 5 A TS Storage Temperature -55 150 °C 4.2 1 1,2 1,2 3 ESD Ratings Symbol Description ESDHBM Human Body Model sensitivity as per ANSI/ESDA/JEDEC JS-001 (HBM Class 1C) ESDCDM Charged Device Model sensitivity as per ANSI/ESDA/JEDEC JS-002 (CDM Class C3) 4.3 Value Unit 1000 to < 2000 V ≥ 1000 V Recommended Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the device. All parameters specified in the subsequent tables refer to these operating conditions. Symbol Description Min Typ Max Unit VIN PowerStage Input Voltage --- --- 80 V VSW,VHS Phase Voltage to PGND -(24 VDD) --- 80 V VDD Driver Supply Voltage 8 10 17 V VHB High Side Bootstrap Voltage -0.3 --- 90 V TJ Junction Temperature -40 --- 125 °C dv/dt HS Slew Rate --- --- 50 V/ns All voltage ratings in this section referenced to ground and for Tc = 25 oC. 2 Not subject to production test. Verified by design/characterization. 3 For