EMA-MB91F467T-LS-144M08 数据手册
Fujitsu Microelectronics Europe
User Guide
UG-910062-13-EMA-MB91F467T-LS-144M08
FR60 FAMILY
SOCKET ADAPTER BOARD
EMA-MB91F467T-LS-144M08
USER GUIDE
UG-910062-13-EMA-MB91F467T-LS-144M08
Revision History
Date
12.09.2007
02.10.2007
25.10.2007
19.01.2009
Issue
V1.0, MB,AW,RH First creation
V1.1, Amendments to tables 3.4.1 to 3.4.3; table 3.4.4 deleted
V1.2, Removing of headlines
V1.3, CEy
Description for EMA-MB91FV460B-001 added, updated CPLD code
Schematic version:
1.1
PCB version:
1.0
CPLD version:
1.3
This document contains 21 pages.
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Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for the EMA-MB91F467T-LS-144M08 Board and all its deliverables
(e.g. software include or header files, application examples, target boards, evaluation boards,
engineering samples of IC’s etc.), its performance and any consequential damages, on the use of the
Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase
Agreement under which agreements the Product has been delivered, (ii) the technical descriptions
and (iii) all accompanying written materials. In addition, to the maximum extent permitted by
applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the
performance of the Product and any consequential damages in cases of unauthorised decompiling
and/or reverse engineering and/or disassembling. Note, the EMA-MB91F467T-LS-144M08 Board
and all its deliverables are intended and must only be used in an evaluation laboratory
environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer’s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its supplier’s liability are restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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0 Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
0 CONTENTS...................................................................................................................... 4
1 OVERVIEW...................................................................................................................... 5
1.1
Abstract................................................................................................................... 5
1.2
General Description................................................................................................. 5
1.3
Functional Restrictions ............................................................................................ 6
2 INSTALLATION ............................................................................................................... 7
3 SWITCHES AND JUMPERS............................................................................................ 8
3.1
Level Shifter Switches and Jumpers overview......................................................... 8
3.2
Level-shifter direction control jumper ....................................................................... 9
3.3
Bus control jumpers............................................................................................... 10
3.4
Port Jumpers......................................................................................................... 13
3.5
Default Jumper Setting .......................................................................................... 14
4 MECHANICAL DIMENSIONS........................................................................................ 16
5 CPLD ............................................................................................................................. 17
5.1
CPLD Verilog Code ............................................................................................... 17
5.2
CPLD programming jumper (J491) ........................................................................ 19
6 INFORMATION IN THE WWW....................................................................................... 20
7 RECYCLING .................................................................................................................. 21
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1 Overview
1.1
Abstract
The EMA-MB91F467T-LS-144M08 in combination with the EMA-MB91V460A-002B/-80/003
or EMA-MB91FV460B-001 is a development system for the Fujitsu FR60 MB91V460 Flash
microcontroller.
The EMA-MB91F467T-LS-144M08 is an adapter board with level shifters to support the
MB91V460A external bus interface at 3.3V levels.
The development system allows the designer immediately to start with the software
development before MB91V460 based silicon samples are available.
This board must only be used for test applications
in an evaluation laboratory environment.
Before using the EMA-MB91F467T-LS-144M08 adapter board, make sure that the following
packed components have been delivered:
1.2
o
1 pcs. EMA-MB91F467T-LS-144M08 socket adapter board
o
1 pcs. YQPACK144SD
o
5 pcs. Screw M2x12
o
5 pcs. Washer M2, Nylon
o
20 pcs. 1.27mm mini jumper
o
1 pcs. User Guide
General Description
The EMA-MB91F467T-LS-144M08 in combination with the EMA-MB91V460A-002B/-80/003
or EMA-MB91FV460B-001 replaces a MB91F467T microcontroller. For further details of the
EMA-MB91V460A-002B/-80/003 or EMA-MB91FV460B-001 board please refer to the User
Guide of the EMA-MB91V460A-002B/-80/003 or EMA-MB91FV460B-001.
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1.3
Functional Restrictions
1.3.1 Valid for EMA-MB91V460A-002B/-80/003 and EMA-MB91FV460B-001
This probe cable can only be used for the following Microcontroller configuration:
1. VDD5 = 5V, VDD35 = 3.3V, External bus enabled by software
The following Microcontroller configurations (2 & 3) are applicable with this probe cable, but
it is recommended to use the appropriate MCU “NLS” probe cable!
2. VDD5 = 5V, VDD35 = 5V, External bus enabled by software
3. VDD5 = 3.3V, VDD35 = 3.3V, External bus enabled by software
While using this probe cable, the GPIO functionality on the external bus interface (VDD35
voltage domain) is restricted!
Unused external bus function pins (e.g. address lines) cannot be configured as general
purpose in- or output randomly!
The following ports can be configured as permanent general purpose input OR output.
1. P07[0..7]
2. P06[0..7]
3. P05[0..7]
It is only possible to configure the whole port as input OR output!
Configuring each pin of these ports separately as input or output is not applicable!
For details on how to configure the port input and output direction please see chapter 3.4
Level-shifter direction control jumper!
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2 Installation
Remove carefully the EMA-MB91F467T-LS-144M08 board from the shipping carton and
check if there are any damages.
Please refer to the attached document “NQPACK/ YQPACK/ HQPACK Technical
Information” for installation the socket adapter.
Screw
M2.5 x 12
(optional)
DSU4 SSRAM, Emulation bus Flash + SRAM
MB91V460
Washer
M2.5 (Fiber)
(optional)
Connector for extension board
EMA-MB91V460A-002B/003
Connector EMA-MB91V460A-002B/003
to EMA-MB91F467T-LS-144M08
EMA-MB91F467T-LS-144M08
120,8 mm
YQPACK / CSICE adapter
NQPACK / CSPACK
Target board
Figure 2-1: Installation
© Fujitsu Microelectronics Europe GmbH
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3 Switches and Jumpers
This chapter describes all switches and jumpers that can be modified or accessed on the
EMA-MB91F467T-LS-144M08 board. The default setting is shown with a grey shaded area.
3.1
Level Shifter Switches and Jumpers overview
Jumper
Description/ Function
Type
Default
S400-1
S400-2
S400-3
S400-4
S400-5
S400-6
S400-7
S400-8
S400-9
S400-10
S401-1
S401-2
S401-3
S401-4
S401-5
S401-6
S401-7
S401-8
S401-9
S401-10
R400
R401
R402
R403
R404
R405
R406
R407
R408
R410
DIR_U406
DIR_U407
DIR_U408
P09_0 CS0#
P09_1 CS1#
P09_2 CS2#
P10_0 SYSCLK
P10_1 AS#
P10_3 WE#
P08_0 WR0#
CS select
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
DIP-Switch
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
reserved
P08_7
P08_4
P08_1
P09_0
P09_1
P09_2
P10_0
P10_1
P10_3
P08_0
P08_1
P08_4
P08_7
RDY
RD#
WR1
CS0#
CS1#
CS2#
SYSCLK
AS#
WE#
WR0#
WR1#
RD#
RDY
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3.2
Level-shifter direction control jumper
Jumper
Setting
S400-1
(Direction U406)
ON
Target board A[0..7]
MB91V460 A[0..7]
OFF
Target board A[0..7]
MB91V460 A[0..7]
ON
Target board A[8..15]
MB91V460 A[8..15]
OFF
Target board A[8..15]
MB91V460 A[8..15]
ON
Target board A[16..23]
MB91V460 A[16..23]
OFF
Target board A[16..23]
MB91V460 A[16..23]
S400-2
(Direction U407)
S400-3
(Direction U408)
Description
Default: S400-1, S400-2, S400-3: OFF
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3.3
Bus control jumpers
3.3.1 WR0# (P08_0)
R406
S400-10
Description
Closed
OFF
P08_0
WR0#
Open
ON
P08_0
WR0#
Closed
ON
Prohibited
Default: R406: Closed, S400-10: OFF
3.3.2 WR1# (P08_1)
R407
S401-10
Description
Closed
OFF
P08_1
WR1#
Open
ON
P08_1
WR1#
Closed
ON
Prohibited
Default: R407: Closed, S401-10: OFF
3.3.3 RD# (P08_4)
R408
S401-9
Description
Closed
OFF
P08_4
RD#
Open
ON
P08_4
RD#
Closed
ON
Prohibited
Default: R408: Closed, S401-9: OFF
3.3.4 RDY (P08_7)
R410
S401-8
Description
Closed
OFF
P08_7
RDY
Open
ON
P08_7
RDY
Closed
ON
Prohibited
Default: R410: Closed, S401-8: OFF
3.3.5 CS0# (P09_0)
R400
S400-4
Description
Closed
OFF
P09_0
CS0#
Open
ON
P09_0
CS0#
Closed
ON
Prohibited
Default: R400: Closed, S400-4: OFF
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3.3.6 CS1# (P09_1)
R401
S400-5
Description
Closed
OFF
P09_1
CS1#
Open
ON
P09_1
CS1#
Closed
ON
Prohibited
Default: R401: Closed, S400-5: OFF
3.3.7 CS2# (P09_2)
R402
S400-6
Description
Closed
OFF
P09_2
CS2#
Open
ON
P09_2
CS2#
Closed
ON
Prohibited
Default: R402: Closed, S400-6: OFF
3.3.8 SYSCLK (P10_0)
R403
S400-7
Description
Closed
OFF
P10_0
SYSCLK
Open
ON
P10_0
SYSCLK
Closed
ON
Prohibited
Default: R403: Closed, S400-7: OFF
3.3.9 AS# (P10_1)
R404
S400-8
Description
Closed
OFF
P10_1
AS#
Open
ON
P10_1
AS#
Closed
ON
Prohibited
Default: R404: Closed, S400-8: OFF
3.3.10 WE# (P10_3)
R405
S400-9
Description
Closed
OFF
P10_3
WE#
Open
ON
P10_3
WE#
Closed
ON
Prohibited
Default: R405: Closed, S400-9: OFF
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3.3.11 CS select (CPLD)
S401_2
S401_1
Description
OFF
OFF
CS0# is selected
OFF
ON
CS1# is selected
ON
OFF
CS2# is selected
ON
ON
Do not set
Default: S401_1, S401_2: OFF
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3.4
Port Jumpers
3.4.1 P35
P29
Jumper U100 pin
J238
110
J239
111
J240
112
J241
113
J242
114
J243
115
Default: all 1-2 and 3-4
3.4.2 P24
P 1-2
[PPMUX.PS5=1]
P35_0
P35_1
P35_2
P35_3
P35_4
P35_5
P 2-3
[PPMUX.PS5=0]
P29_0
P29_1
P29_2
P29_3
P29_4
P29_5
P 3-4
[PPMUX.PS5=1]
P29_0 pulldown
P29_1 pulldown
P29_2 pulldown
P29_3 pulldown
P29_4 pulldown
P29_5 pulldown
P 1-2
[PPMUX.PS2=0]
and
[PPMUX.PR0=0]
P24_0
P24_1
P24_2
P24_3
P24_4
P24_5
P24_6
P24_7
P 2-3
[PPMUX.PS2=1]
and
[PPMUX.PR0=1]
P28_0
P28_1
P28_2
P28_3
P28_4
P28_5
P28_6
P28_7
P 3-4
[PPMUX.PS2=0]
and
[PPMUX.PR0=0]
P28_0 pulldown
P28_1 pulldown
P28_2 pulldown
P28_3 pulldown
P28_4 pulldown
P28_5 pulldown
P28_6 pulldown
P28_7 pulldown
P28
Jumper U100 pin
J244
118
J245
119
J246
120
J247
121
J248
122
J249
123
J250
124
J251
125
Default: all 1-2 and 3-4
3.4.3 P16/P20
Jumper U100 pin
J252
128
J253
129
J254
130
J255
131
J256
132
J257
133
J258
134
J259
135
Default: all 1-2 and 3-4
P27
P 1-2
[PPMUX.PS1=0]
and NOT
[PPMUX.PR(11..17)=1]
and
[PPMUX.PRPS0=1]
P16_0
P16_1
P20_0
P20_1
P20_2
P20_4
P20_5
P20_6
© Fujitsu Microelectronics Europe GmbH
P 2-3
[PPMUX.PS1=1]
and NOT
[PPMUX.PR(11..17)=1]
and
[PPMUX.PRPS0=1]
P27_0
P27_1
P27_2
P27_3
P27_4
P27_5
P27_6
P27_7
P 3-4
[PPMUX.PS1=0]
and NOT
[PPMUX.PR(11..17)=1]
and
[PPMUX.PRPS0=1]
P27_0 pulldown
P27_1 pulldown
P27_2 pulldown
P27_3 pulldown
P27_4 pulldown
P27_5 pulldown
P27_6 pulldown
P27_7 pulldown
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3.5
Default Jumper Setting
The following jumper setting is the default setting.
R400
R402
R401
R404
R403
R406
R405
R407
J491
Figure 3-1: Jumper default setting, top
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S400
ON
1
R409
U100
R410
10
R408
ON
1
R411
10
R412
R413
S401
R100
Figure 3-2: Jumper location, bottom
© Fujitsu Microelectronics Europe GmbH
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4 Mechanical dimensions
33 mm
Top view
71 mm
Pin1
33 mm
YQ Socket
66 mm
29mm
EMA-MB91V460A-002B/003
EMA-MB91F467T-LS-144M08
14mm
YQSOCKET / YQPACK / NQPACK
(socket dimension depends on socket type)
Target board
29 mm
Figure 4-1: Mechanical Dimensions
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5 CPLD
The CPLD Xilinx XC9536XL-5VQL44C controls the direction of the data bus.
5.1
CPLD Verilog Code
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////
// Company:
Accemic GmbH & Co. KG
// Engineer:
RH / AW
//
// Create Date:
03/08/2007
// Design Name:
EMA-MB91F467T-LS-144M08
// Module Name:
F467T
// Project Name:
// Target Devices: XC9536XL-5VQ44
// Tool versions: ISE 9.1
// Description:
//
// Dependencies:
//
// Revision:
// Revision
1.3
// Additional Comments: none
//
// USERCODE:
7T13
//
||||____ Subversion
//
|||_____ Version
//
||______ Target 467T
//
**
//
///////////////////////////////////////////////////////////////////////////
module EMA_MB91F467T_LS_144M08_V11_cpld_7T13(
ECSx,
CSx,
// P09_7..P09_0
WRx,
// P08_3..P08_0
RDx,
// P08_4
ASx,
// P10_1
BAAx,
// P10_2
WEx,
// P10_3
IORDx,
// P11_0
IOWRx,
// P11_1
S401,
DIR_U400,
DIR_U401,
DIR_U404,
DIR_U405,
OEx_U400_U401,
OEx_U404_U405);
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input ECSx;
input[7:0] CSx;
input[3:0] WRx;
input RDx;
input ASx;
input BAAx;
input WEx;
input IORDx;
input IOWRx;
input[7:1] S401;
output DIR_U400;
output DIR_U401;
output DIR_U404;
output DIR_U405;
output OEx_U400_U401;
output OEx_U404_U405;
reg OEx_U400_U401, OEx_U404_U405;
reg DIR_U400, DIR_U401, DIR_U404, DIR_U405;
always @*
begin
case (S401[2:1] ) // CS_MASK
2'b11: // CS0
OEx_U404_U405
2'b10: // CS1
OEx_U404_U405
2'b01: // CS2
OEx_U404_U405
2'b00: // none masked
OEx_U404_U405
endcase
= !ECSx | (CSx[1] & CSx[2]);
= !ECSx | (CSx[0] & CSx[2]);
= !ECSx | (CSx[0] & CSx[1]);
= !ECSx | (CSx[0] & CSx[1] & CSx[2]);
OEx_U400_U401 = 1;
// check
DIR_U400
DIR_U401
DIR_U404
DIR_U405
schematic for DIR level (different on LS boards)
= 1;
= 1;
= !RDx;
= !RDx;
end
endmodule
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5.2
CPLD programming jumper (J491)
The CPLD is re-configurable by programming via J491. Please refer to www.xilinx.com for
details and tools for Xilinx CPLD configuration.
J491 pin
Name
1
2
3
4
5
6
GND
TDO
TCK
TMS
TDI
VREF
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6 Information in the WWW
Information about FUJITSU MICROELECTRONICS Products
can be found on the following Internet pages:
Microcontrollers (8-, 16- and 32bit), Graphics Controllers
Datasheets and Hardware Manuals, Support Tools (Hard- and Software)
http://www.fme.gsdc.de/gsdc.htm
Linear Products: Power Management, A/D and D/A Converters
http://www.fujitsu.com/emea/services/microelectronics
Media Products: SAW filters, acoustic resonators and VCOs
http://www.fujitsu.com/emea/services/microelectronics/saw
For more information about FUJITUS MICROELECTRONICS
http://www.fujitsu.com/emea/services/microelectronics
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7 Recycling
Gültig für EU-Länder:
Gemäß der Europäischen WEEE-Richtlinie und deren Umsetzung in landesspezifische
Gesetze nehmen wir dieses Gerät wieder zurück.
Zur Entsorgung schicken Sie das Gerät bitte an die folgende Adresse:
Fujitsu Microelectronics Europe GmbH
Warehouse/Disposal
Monzastraße 4a
63225 Langen
Valid for European Union Countries:
According to the European WEEE-Directive and its implementation into national laws we
take this device back.
For disposal please send the device to the following address:
Fujitsu Microelectronics Europe GmbH
Warehouse/Disposal
Monzastraße 4a
63225 Langen
© Fujitsu Microelectronics Europe GmbH
UG-910062-13-EMA-MB91F467T-LS-144M08
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