EMA-MB91F469G-LS-320M06

Fujitsu Microelectronics Europe User Guide UG-910046-15-EMA-MB91F469G-LS-320M06 FR60 FAMILY SOCKET ADAPTER BOARD EMA-MB91F469G-LS-320M06 USER GUIDE UG-910046-15-EMA-MB91F469G-LS-320M06 Revision History Date 19.03.2007 30.03.2007 Issue V1.00, RH/AW, First Release V1.1, MB, UG-910046-10-EMA-MB91F469G-LS-320M06-corr-x1-00 corrections added 26.04.2007 V1.2, MB, Fig. 3-2 S400 changed 16.09.2008(!) V1.2, MSc, China-RoHS regulation added 30.05.2007 V1.3, Chapter 1.3 added, Amendments to Fig 3.1 31.10.2008 V1.4, CEy Please note version conflict of V1.2! Merged both versions Restored missing images, made some minor corrections and updates, added description of features of CPLD code version 9G12 16.01.2009 V1.5, CEy Description for EMA-MB91FV460B-001 added Schematic version: 2.4 PCB version: 2.2 CPLD version : 9G12 This document contains 36 pages. UG-910046-15-EMA-MB91F469G-LS-320M06 © Fujitsu Microelectronics Europe GmbH -2- UG-910046-15-EMA-MB91F469G-LS-320M06 Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for the EMA-MB91F469G-LS-320M06 Board and all its deliverables (e.g. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC’s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, the EMA-MB91F469G-LS-320M06 Board and all its deliverables are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. 2. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer’s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH. 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated. 4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s and its supplier’s liability are restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect © Fujitsu Microelectronics Europe GmbH UG-910046-15-EMA-MB91F469G-LS-320M06 -3- UG-910046-15-EMA-MB91F469G-LS-320M06 0 Contents REVISION HISTORY ............................................................................................................ 2 WARRANTY AND DISCLAIMER ......................................................................................... 3 0 CONTENTS...................................................................................................................... 4 1 OVERVIEW...................................................................................................................... 7 1.1 Abstract................................................................................................................... 7 1.2 General Description................................................................................................. 8 1.3 Functional Restrictions ............................................................................................ 9 1.3.1 Valid for EMA-MB91V460A-002B/-80/003 and EMA-MB91FV460B-001.... 9 2 INSTALLATION ............................................................................................................. 10 3 SWITCHES AND JUMPERS.......................................................................................... 11 3.1 Switches and Jumpers overview ........................................................................... 11 3.1.1 External bus data..................................................................................... 11 3.1.2 Bus control............................................................................................... 12 3.1.3 DMA control............................................................................................. 13 3.1.4 Level Shifter direction / CS ...................................................................... 13 3.2 Default Jumper Setting .......................................................................................... 14 3.3 Level-shifter direction control jumper ..................................................................... 16 3.4 Data bus jumpers (D0-D7)..................................................................................... 17 3.5 3.4.1 D0 (P03_0) .............................................................................................. 17 3.4.2 D1 (P03_1) .............................................................................................. 17 3.4.3 D2 (P03_2) .............................................................................................. 17 3.4.4 D3 (P03_3) .............................................................................................. 17 3.4.5 D4 (P03_4) .............................................................................................. 17 3.4.6 D5 (P03_5) .............................................................................................. 18 3.4.7 D6 (P03_6) .............................................................................................. 18 3.4.8 D7 (P03_7) .............................................................................................. 18 Data bus jumpers (D8-D15)................................................................................... 19 3.5.1 D8 (P02_0) .............................................................................................. 19 3.5.2 D9 (P02_1) .............................................................................................. 19 3.5.3 D10 (P02_2) ............................................................................................ 19 3.5.4 D11 (P02_3) ............................................................................................ 19 3.5.5 D12 (P02_4) ............................................................................................ 19 3.5.6 D13 (P02_5) ............................................................................................ 20 UG-910046-15-EMA-MB91F469G-LS-320M06 © Fujitsu Microelectronics Europe GmbH -4- UG-910046-15-EMA-MB91F469G-LS-320M06 3.6 3.7 3.5.7 D14 (P02_6) ............................................................................................ 20 3.5.8 D15 (P02_7) ............................................................................................ 20 Bus control jumpers............................................................................................... 21 3.6.1 CS0# (P09_0).......................................................................................... 21 3.6.2 CS1# (P09_1).......................................................................................... 21 3.6.3 CS2# (P09_2).......................................................................................... 21 3.6.4 CS3# (P09_3).......................................................................................... 21 3.6.5 CS4# (P09_4).......................................................................................... 21 3.6.6 CS5# (P09_5).......................................................................................... 22 3.6.7 CS6# (P09_6).......................................................................................... 22 3.6.8 CS7# (P09_7).......................................................................................... 22 3.6.9 BGRNT# (P08_5) .................................................................................... 22 3.6.10 BRQ (P08_6) ........................................................................................... 22 3.6.11 BAA# (P10_2).......................................................................................... 23 3.6.12 WE# (P10_3) ........................................................................................... 23 3.6.13 AS# (P10_1) ............................................................................................ 23 3.6.14 RDY (P08_7) ........................................................................................... 23 3.6.15 SYSCLK (P10_0)..................................................................................... 23 DMA jumpers ........................................................................................................ 24 3.7.1 DREQ0 (P13_0)....................................................................................... 24 3.7.2 DACK0# (P13_1) ..................................................................................... 24 3.7.3 DEOT0 (P13_2) ....................................................................................... 24 3.7.4 DEOP0 (P13_3)....................................................................................... 24 3.7.5 DREQ1 (P13_4)....................................................................................... 24 3.7.6 DACK1# (P13_5) ..................................................................................... 25 3.7.7 DEOT1 (P13_6) ....................................................................................... 25 3.7.8 DEOP1 (P13_7)....................................................................................... 25 4 CPLD ............................................................................................................................. 26 4.1 CPLD Verilog Code ............................................................................................... 26 4.2 CPLD Constraints.................................................................................................. 29 4.3 CPLD control settings............................................................................................ 30 4.4 4.3.1 Product revision 1.2 (CPLD revision 9G12).............................................. 30 4.3.2 Product revision 1.1 (CPLD revision 9G11).............................................. 31 CPLD programming jumper (J491) ........................................................................ 31 5 MECHANICAL DIMENSIONS........................................................................................ 32 6 INFORMATION IN THE WWW....................................................................................... 33 © Fujitsu Microelectronics Europe GmbH UG-910046-15-EMA-MB91F469G-LS-320M06 -5- UG-910046-15-EMA-MB91F469G-LS-320M06 7 CHINA-ROHS REGULATION ........................................................................................ 34 8 RECYCLING .................................................................................................................. 36 UG-910046-15-EMA-MB91F469G-LS-320M06 © Fujitsu Microelectronics Europe GmbH -6- UG-910046-15-EMA-MB91F469G-LS-320M06 1 Overview 1.1 Abstract The EMA-MB91F469G-LS-320M06 in combination with the EMA-MB91V460A-002B/-80/003 or EMA-MB91FV460B-001 is a development system for the Fujitsu FR60 MB91V460 Flash microcontroller. The EMA-MB91F469G-LS-320M06 is an adapter board with level shifters to support the MB91V460A external bus interface at 3.3V levels. The development system allows the designer immediately to start with the software development before MB91V460 based silicon samples are available. This board must only be used for test applications in an evaluation laboratory environment. Before using the EMA-MB91F469G-LS-320M06 adapter board, make sure that the following packed components have been delivered: o 1 pcs. EMA-MB91F469G-LS-320M06 socket adapter board o 1 pcs. CSICE256Y2027FJ01 o 5 pcs. Screw M2x16 o 5 pcs. Washer M2, Nylon o 1 pcs. User Guide Note for SDRAM usage The EMA-MB91F469G-LS-320M06 supports external SRAM, Flash memory and SDRAM. Please refer to section 4 for further details. Because of the additional delay of the level shifter the bus clock (CLKT) is limited to 32 MHz while SDRAM is connected to the external bus. SDRAM SRAM X X X X X X X Flash CLKT restriction X No restriction No restriction No restriction CLKT