Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
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Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
FM1808B
256-Kbit (32 K × 8) Bytewide F-RAM Memory
FM1808B, 256-Kbit (32 K × 8) Bytewide F-RAM Memory
Features
■
256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32 K × 8
14
❐ High-endurance 100 trillion (10 ) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■
SRAM and EEPROM compatible
❐ Industry-standard 32 K × 8 SRAM and EEPROM pinout
❐ 70-ns access time, 130-ns cycle time
■
Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
❐ Resistant to negative voltage undershoots
■
Low power consumption
❐ Active current 15 mA (max)
❐ Standby current 25 A (typ)
■
Voltage operation: VDD = 4.5 V to 5.5 V
■
Industrial temperature: –40 C to +85 C
■
28-pin small outline integrated circuit (SOIC) package
■
Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM1808B is a 32 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM1808B operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM1808B ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
A14-0
Address Latch and Decoder
Logic Block Diagram
A 14-0
32 K x 8
F-RAM Array
CE
WE
Control
Logic
I/O Latch & Bus Driver
DQ 7-0
OE
Cypress Semiconductor Corporation
Document Number: 001-86209 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 10, 2019
FM1808B
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Architecture ................................................... 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Pre-charge Operation .................................................. 4
Endurance ......................................................................... 5
F-RAM Design Considerations ........................................ 5
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
Document Number: 001-86209 Rev. *F
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
SRAM Write Cycle ....................................................... 9
Power Cycle Timing ....................................................... 12
Functional Truth Table ................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ...................................................... 17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Page 2 of 17
FM1808B
Pinout
Figure 1. 28-pin SOIC Pinout
A14
1
28
VDD
A12
A7
2
3
27
26
WE
A13
A6
4
5
25
24
23
A8
22
21
OE
A10
20
CE
DQ7
A5
A4
A3
6
7
28-pin SOIC
(x 8)
A2
A1
8
9
Top view
(not to scale)
A0
10
11
19
18
12
13
17
16
14
15
DQ0
DQ1
DQ2
VSS
A9
A11
DQ6
DQ5
DQ4
DQ3
Pin Definitions
Pin Name
I/O Type
A14–A0
Input
DQ7–DQ0
Description
Address inputs: The 15 address lines select one of 32,768 bytes in the F-RAM array.
Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
Write Enable: A write cycle begins when WE is asserted. Asserting WE LOW causes the FM1808B to
write the contents of the data bus to the address location latched by the falling edge of CE.
CE
Input
Chip Enable: The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
OE
Input
Output Enable: When OE is LOW, the FM1808B drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS
Ground
VDD
NC
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect
No connect. This pin is not connected to the die.
Document Number: 001-86209 Rev. *F
Page 3 of 17
FM1808B
Device Operation
The FM1808B is a bytewide F-RAM memory logically organized
as 32,768 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM1808B requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 12 for a complete description of
read and write modes.
Memory Architecture
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The complete 15-bit address
specifies each of the 32,768 bytes uniquely. The F-RAM array is
organized as 4092 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance section.
The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits.
Likewise the access time is the same for read and write memory
operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that VDD remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between VDD and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing” on page 12.
Memory Operation
The FM1808B is designed to operate in a manner similar to other
bytewide memory products. For users familiar with BBSRAM, the
performance is comparable but the bytewide interface operates
in a slightly different manner as described below. For users
familiar with EEPROM, the differences result from the higher
write performance of F-RAM technology including NoDelay
writes and much higher write endurance.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
The FM1808B will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM1808B, writes occur in the same interval as reads. The
FM1808B supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM1808B will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the page 11.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
Document Number: 001-86209 Rev. *F
Page 4 of 17
FM1808B
Endurance
F-RAM Design Considerations
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM1808B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, F-RAM
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 1014 cycles will allow
150,000 accesses per second to the same row for over 20 years.
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
falling edge of CE, users cannot ground it as they might with
SRAM.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in Figure 2. Also shown is a common SRAM signal
relationship that will not work for the FM1808B.
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
Figure 2. Chip Enable and Memory Address Relationships
Valid Strobing of CE
CE
F-RAM
Signaling
Address
A1
A2
Data
D1
D2
Invalid Strobing of CE
CE
SRAM
Signaling
Address
A1
Data
A second design consideration relates to the level of VDD during
operation. Battery-backed SRAMs are forced to monitor VDD in
order to switch to battery backup. They typically block user
access below a certain VDD level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
Document Number: 001-86209 Rev. *F
A2
D1
D2
F-RAM memories do not need this system overhead. The
memory will not block access at any VDD level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when VDD is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track VDD during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below VDD min. (4.5 V).
Page 5 of 17
FM1808B
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 3. Use of Pull-up Resistor on CE
VDD
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If the chip is enabled
and WE is LOW during power cycles, data will be corrupted.
Figure 4 shows a pull-up resistor on WE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the WE pin tracks VDD to a high
enough value, so that the current drawn when WE is LOW is not
an issue.
Figure 4. Use of Pull-up Resistor on WE
FM1808B
VDD
CE
CE
WE
MCU / MPU
DQ 7-0
Document Number: 001-86209 Rev. *F
WE
OE
A 14-0
FM1808B
MCU / MPU
OE
A 14-0
DQ 7-0
Page 6 of 17
FM1808B
Maximum Ratings
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
Storage temperature ................................ –55 C to +125 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Latch-up current ................................................... > 140 mA
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Operating Range
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Range
Ambient Temperature (TA)
VDD
–40 C to +85 C
4.5 V to 5.5 V
Industrial
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Min
Typ [1]
Max
Unit
4.5
5.0
5.5
V
–
–
15
mA
TA 25 C
–
–
1.8
mA
TA < 25 C
–
–
2.0
mA
Test Conditions
VDD
Power supply voltage
IDD
VDD supply current
VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
ISB1
Standby current (TTL)
VDD = 5.5 V, CE at VIH,
All other pins are static and at
TTL levels (0.8 V or 2.0 V)
ISB2
Standby current (CMOS)
VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
–
25
50
µA
ILI
Input leakage current
VIN between VDD and VSS
–
–
+1
µA
ILO
Output leakage current
VOUT between VDD and VSS
–
–
+1
µA
VIH
Input HIGH voltage
–
2.0
–
VDD + 0.3
V
VIL
Input LOW voltage
–
– 0.3
–
0.8
V
VOH1
Output HIGH voltage
IOH = –2.0 mA
2.4
–
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDD – 0.2
–
–
V
VOL1
Output LOW voltage
IOL = 4.2 mA
–
–
0.4
V
VOL2
Output LOW voltage
IOL = 150 µA
–
–
0.2
V
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-86209 Rev. *F
Page 7 of 17
FM1808B
Data Retention and Endurance
Parameter
Description
Test condition
Min
Max
Unit
At +85 C
10
–
Years
TDR
Data retention
At +75 C
38
–
Years
At +65 C
151
–
Years
NVC
Endurance
Over operating temperature
1014
–
Cycles
Capacitance
Parameter
Description
Test Conditions
CI/O
Input/Output capacitance (DQ)
CIN
Input capacitance
Max
TA = 25 C, f = 1 MHz, VDD = VDD(Typ)
Unit
8
pF
6
pF
Thermal Resistance
Description
Parameter
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
28-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
in accordance with EIA/JESD51.
58
C/W
26
C/W
AC Test Conditions
Input pulse levels ....................................................0 V to 3V
Input rise and fall times (10%–90%) ......................... < 10 ns
Input and output timing reference levels .......................... 1.5
Output load capacitance ............................................. 100 pF
Figure 5. AC Test Loads
919
5.5 V
R1
OUTPUT
CL
100 pF
Document Number: 001-86209 Rev. *F
R2
497
Page 8 of 17
FM1808B
AC Switching Characteristics
Over the Operating Range
Parameters[2]
Cypress
Parameter
Description
Alt Parameter
Min
Max
Unit
SRAM Read Cycle
tCE
tACE
Chip enable access time
–
70
ns
tCA
–
Chip enable active time
70
–
ns
tRC
–
Read cycle time
130
–
ns
tPC
–
Pre-charge time
60
–
ns
tAS
tSA
Address setup time
0
–
ns
tAH
tHA
Address hold time
15
–
ns
tOE
tDOE
Output enable access time
–
12
ns
tHZ[3, 5]
tHZCE
Chip Enable to output HI-Z
–
15
ns
tOHZ[3, 5]
tHZOE
Output enable HIGH to output HI-Z
–
15
ns
tWC
tWC
Write cycle time
130
–
ns
tCA
–
Chip enable active time
70
–
ns
tCW
tSCE
Chip enable to write enable HIGH
70
–
ns
tPC
–
Pre-charge time
60
–
ns
tWP
tPWE
Write enable pulse width
40
–
ns
tAS
tSA
Address setup time
0
–
ns
tAH
tHA
Address hold time
15
–
ns
tDS
tSD
Data input setup time
30
–
ns
tDH
tHD
Data input hold time
0
–
ns
tWZ[4, 4]
tHZWE
Write enable LOW to output HI-Z
–
15
ns
tWX[4]
–
Write enable HIGH to output driven
10
–
ns
tHZ[4]
–
Chip enable to output HI-Z
–
15
ns
tWS[6]
tWH[6]
–
Write enable to CE LOW setup time
0
–
ns
–
Write enable to CE HIGH hold time
0
–
ns
SRAM Write Cycle
Notes
2. Test conditions assume a signal transition time of 10 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. tWZ and tHZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
6. The relationship between CE and WE determines if a CE or WE controlled write occurs. There is no timing specification associated with this relationship.
Document Number: 001-86209 Rev. *F
Page 9 of 17
FM1808B
Figure 6. Read Cycle Timing
tRC
tCA
tPC
CE
tAH
tAS
A12-0
tOE
OE
tOHZ
DQ7-0
tCE
tHZ
Figure 7. Write Cycle Timing 1 (CE Controlled)
tWC
tCA
tPC
CE
tAS
tAH
A12-0
tWS
tWH
WE
OE
tDS
tDH
DQ 7-0
Document Number: 001-86209 Rev. *F
Page 10 of 17
FM1808B
Figure 8. Write Cycle Timing 2 (WE Controlled)
tWC
tCA
tPC
tC W
CE
tAS
tAH
A12-0
tWS
tWH
tWP
WE
OE
tWZ
tWX
DQ7-0 (out)
tDH
tDS
DQ7-0 (in)
Document Number: 001-86209 Rev. *F
Page 11 of 17
FM1808B
Power Cycle Timing
Over the Operating Range
Parameter
tPU
tPD
tVR
[7]
tVF[7]
Description
Min
Max
Unit
Power-up (after VDD min. is reached) to first access time
10
–
ms
Last write (WE HIGH) to power down time
0
–
µs
VDD power-up ramp rate
30
–
µs/V
VDD power-down ramp rate
30
–
µs/V
Figure 9. Power Cycle Timing
VDD
VDD min
VDD min
t VR
t VF
t PU
t PD
Access Allowed
VIH (min)
VIL (max)
Functional Truth Table
Operation[8, 9]
CE
WE
H
X
Standby/Pre-charge
↓
X
Latch Address (and begin write if WE = LOW)
L
H
Read
L
↓
Write
Notes
7. Slope measured at any point on the VDD waveform.
8. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = Toggle LOW, ↑ = Toggle HIGH.
9. The OE pin controls only the DQ output buffers.
Document Number: 001-86209 Rev. *F
Page 12 of 17
FM1808B
Ordering Information
Ordering Code
Package Diagram
Package Type
FM1808B-SG
51-85026
28-pin SOIC
FM1808B-SGTR
51-85026
28-pin SOIC
Operating Range
Industrial
All the above parts are Pb-free.
Ordering Code Definitions
FM 18 08
B
-
SG TR
Option:
blank = Standard; TR = Tape and Reel
Package Type:
SG = 28-pin SOIC
Voltage: 4.5 V to 5.5 V
I/O Width: × 8
256-Kbit Parallel F-RAM
Cypress
Document Number: 001-86209 Rev. *F
Page 13 of 17
FM1808B
Package Diagram
Figure 10. 28-pin SOIC Package Outline, 51-85026
51-85026 *H
Document Number: 001-86209 Rev. *F
Page 14 of 17
FM1808B
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
CPU
Central Processing Unit
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
JEDEC
Joint Electron Devices Engineering Council
Hz
hertz
JESD
JEDEC Standards
kHz
kilohertz
EIA
Electronic Industries Alliance
k
kilohm
F-RAM
Ferroelectric Random Access Memory
MHz
megahertz
I/O
Input/Output
A
microampere
MCU
Microcontroller Unit
F
microfarad
MPU
Microprocessor Unit
s
microsecond
RoHS
Restriction of Hazardous Substances
mA
milliampere
R/W
Read and Write
ms
millisecond
SOIC
Small Outline Integrated Circuit
M
megaohm
SRAM
Static Random Access Memory
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-86209 Rev. *F
Symbol
Unit of Measure
Page 15 of 17
FM1808B
Document History Page
Document Title: FM1808B, 256-Kbit (32 K × 8) Bytewide F-RAM Memory
Document Number: 001-86209
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
3912933
GVCH
02/25/2013
New spec
*A
4000965
GVCH
05/15/2013
Added Appendix A - Errata for FM1808B
*B
4045491
GVCH
06/30/2013
All errata items are fixed and the errata is removed.
*C
4274813
GVCH
03/10/2014
Converted to Cypress standard format
Changed datasheet status from “Preliminary to Final”
Changed endurance value from 1012 to 1014 cycles
Updated Maximum Ratings table
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance table
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
*D
4562106
GVCH
11/05/2014
Added related documentation hyperlink in page 1.
Updated package diagram 51-85026 to current version.
*E
4881950
ZSK / PSR
09/04/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
*F
6572627
GVCH
06/10/2019
DC Electrical Characteristics: Updated ISB1 parameter test condition and
added ISB1 value for TA < 25 C.
Updated Copyright information.
Document Number: 001-86209 Rev. *F
Page 16 of 17
FM1808B
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Document Number: 001-86209 Rev. *F
Revised June 10, 2019
Page 17 of 17
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