Data Sheet, V0.2, Feb. 2006
TC1165/TC1166
32-Bit Single-Chip Microcontroller
T r i C o r e TM
Microcontrollers
Edition 2006-02
Published by Infineon Technologies AG,
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V0.2, Feb. 2006
TC1165/TC1166
32-Bit Single-Chip Microcontroller
T r i C o r e TM
Microcontrollers
TC1165/TC1166
Revision History:
2006-02
Previous Version:
V0.1, December 2005
V0.2
Page
Subjects (major changes since last revision)
3-82
The reset value for RTID is corrected.
4-95
A new footnote is added to VAREF.
4-100
The footnote on FADC callibration interval is updated.
4-105
Max. values for power supply current section is defined.
4-116
A new section is added for JTAG signals timing based on 40 MHz JTAG
clock.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Template: mc_a5_um_tmplt.fm / 5 / 2005-10-01
TC1165/TC1166
Advance Information
Table of Contents
Table of Contents
1
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
2.1
2.2
2.3
2.4
2.5
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.4.1
3.3.4.2
3.3.5
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.13.1
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . .
On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Read the Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents of the Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the FPI Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the Local Memory Bus (LMB) . . . . . . . . . . . . . . . . . . .
Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . .
High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) . . . . . . . . .
Micro Second Bus Interface (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Link Serial Bus Interface (MLI0, MLI1) . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
1
24
24
25
27
27
29
30
32
32
35
40
44
44
47
49
51
53
55
57
59
61
62
65
67
69
72
73
74
75
76
78
81
82
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table of Contents
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.8.1
4.3.8.2
4.3.8.3
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 84
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Analog to Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . . 99
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Timing for JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 121
Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . 122
5
5.1
5.2
5.3
5.4
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters (PG-LQFP-176-2) . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
2
123
123
124
125
126
V0.2, 2006-02
Advance Information
32-Bit Single-Chip Microcontroller
TriCoreTM
1
TC1165/TC1166
Summary of Features
The TC1165/TC1166 has the following features:
•
•
•
•
•
•
•
High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 80 MHz operation at full temperature range
Peripheral Control Processor with single cycle instruction (PCP2)
– 8 Kbyte Parameter Memory (PRAM)
– 12 Kbyte Code Memory (CMEM)
Multiple on-chip memories
– 56 Kbyte Local Data Memory (SRAM)
– 8 Kbyte Overlay Memory
– 16 Kbyte Scratch-Pad RAM (SPRAM)
– 8 Kbyte Instruction Cache (ICACHE)
– 1504 Kbyte Program Flash (for instruction code and constant data)
– 32 Kbyte Data Flash (e.g. 4 Kbyte EEPROM emulation)
– 16 Kbyte Boot ROM
8-channel DMA Controller
Fast-response interrupt system with 2 x 255 hardware priority arbitration levels
serviced by CPU or PCP2
High-performance on-chip bus structure
– 64-bit Local Memory Bus (LMB) to Flash memory
– System Peripheral Bus (SPB) for interconnections of functional units
Versatile on-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate
generator, parity, framing and overrun error detection
– Two High Speed Synchronous Serial Channels (SSCs) with programmable data
length and shift direction
– One Micro Second Bus (MSC) interface for serial port expansion to external power
devices
– Two high-speed Micro Link Interfaces (MLIs) for serial inter-processor
communication
– One MultiCAN Module with two CAN nodes and 64 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer1)
Data Sheet
3
V0.2, 2006-02
TC1165/TC1166
Advance Information
•
•
•
•
•
•
•
•
•
•
Summary of Features
– One General Purpose Timer Array Module (GPTA) with a powerful set of digital
signal filtering and timer functionality to realize autonomous and complex
Input/Output management
– One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10bit, or 12-bit, supporting 32 input channels
– One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated
comb filters for hardware data reduction: supporting 10-bit resolution, with
minimum conversion time of 262.5ns
32 analog input lines for ADC and FADC
81 digital general purpose I/O lines
Digital I/O ports with 3.3 V capability
On-chip debug support for OCDS Level 1 and 2 (CPU, PCP, DMA)
Power Management System
Clock Generation Unit with PLL
Core supply voltage of 1.5 V
I/O voltage of 3.3 V
Full Industrial and Multi-Market temperature range: -40° to +85°C
PG-LQFP-176-2 package
1) Not applicable to TC1165
Data Sheet
4
V0.2, 2005-12
TC1165/TC1166
Advance Information
Summary of Features
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
•
•
The derivative itself, i.e. its function set, the temperature range, and the supply
voltage
The package and the type of delivery
For the available ordering codes for the TC1165/TC1166, please refer to the “Product
Catalog Microcontrollers” that summarizes all available microcontroller variants.
This document describes the derivatives of the device.The Table 1-1 enumerates these
derivatives and summarizes the differences.
Table 1-1
TC1165/TC1166 Derivative Synopsis
Derivative
Ambient Temperature Range
SAF-TC1165-192F80HL
TA = -40oC to +85oC
SAF-TC1166-192F80HL
TA = -40oC to +85oC
Data Sheet
5
V0.2, 2005-12
TC1165/TC1166
Advance Information
2
General Device Information
General Device Information
Chapter 2 provides the general information for the TC1165/TC1166.
2.1
Block Diagram
Figure 2-1 shows the TC1165/TC1166 block diagram.
FPU
PMI
1 6 KB SPRAM
8 KB ICACHE
DMI
56 KB LDRAM
TriCore
(TC1.3M)
Abbreviations:
ICACHE:
SPRAM:
LDRAM:
OVRAM:
BROM:
PFlash:
DFlash:
PRAM:
CMEM:
CPS
Local Memory Bus (LMB)
16 KB BROM
1504 KB Pflash
32 KB DFlash
8 KB OVRAM
Overl ay
Me chan ism
PMU
LBCU
LFI Bridge
Instruction Cache
Scratch-Pad RAM
Local Data RAM
Overlay RAM
Boot ROM
Program Flash
Data Flash
Parameter Memory in PCP
Code Memory in PCP
PLL
PLL
DMA
8 ch.
Multi CAN
(2 Nodes,
64 Buffer)
1)
MLI0
1) Not applicable to TC1165
Data Sheet
ADC0
32 ch.
MSC0
MLI1
Figure 2-1
SSC1
FADC
2 ch.
SMIF
Ext.
Request
Unit
SSC0
Ana log Inp ut
Assi gnme nt
SCU
Ports
f FPI
f CPU
BI0
GPTA
SBCU
12 KB CMEM
DMA Bus
ASC1
STM
BI1
ASC0
PCP2
Core
Interru pts
System Peri phe ral Bus (SPB)
OCDS Debug
Interface/JTAG
FPI-Bus Interface
8 KB PRAM
Mem
Check
TC1165/TC1166 Block Diagram
TC1165/TC1166 Block Diagram
6
V0.2, 2006-02
TC1165/TC1166
Advance Information
2.2
General Device Information
Logic Symbol
Figure 2-2 shows the TC1165/TC1166 logic symbol.
Alternate Functions
PORST
HDRST
General Control
NMI
BYPASS
TESTMODE
MSC0 Control
FCLP0A
FCLN0
SOP0A
SON0
ADC Analog Inputs
AN[35:0]
VDDM
VSSM
VDDMF
ADC/FADC Analog
Power Supply
Digital Circuitry
Power Supply
VDD
VDDP
VSS
GPTA, SCU
Port 1 15-bit
GPTA, SSC1, ADC
Port 2 14-bit
SSC0/1, MLI0, GPTA, MSC0
Port 3 16-bit
ASC0/1, SSC0/1, SCU, CAN
Port 4 4-bit
GPTA, SCU
Port 5 16-bit
GPTA, OCDS L2, MLI0/1
1)
TRST
TCK
TC1165/
TC1166
TDI
TDO
TMS
BRKIN
BRKOUT
VSSMF
VDDAF
VSSAF
VAREF0
VAGND0
VFAREF
VFAGND
VDDFL3
Port 0 16-bit
OCDS / JTAG Control
TRCLK
XTAL1
XTAL2
VDDOSC3
7
VSSOSC3
8
Oscillator
VDDOSC
9
VSSOSC
TC1165/TC1166 Logic Symbol
1) Alternate functions for CAN module is not applicable for TC1165.
Figure 2-2
Data Sheet
TC1165/TC1166 Logic Symbol
7
V0.2, 2006-02
TC1165/TC1166
Advance Information
2.3
General Device Information
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TC1165/TC1166
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P3.4/MTSR0
P3.7/SLSI0/SLSO02/SLSO12
P3.3/MRST0
P3.2/SCLK0
P3.8/SLSO06/TXD1A
P3.6/SLSO01/SLSO11/SLSO01&SLSO11
P3.5/SLSO00/SLSO10/SLSO00&SLSO10
VS S
VD D P
VD D
HDRST
PORST
NMI
BYPASS
TESTMODE
BRKIN
BRKOUT
TCK
TRST
TDO
TMS
TDI
P1.7/IN23/OUT23/OUT79
P1.6/IN22/OUT22/OUT78
P1.5/IN21/OUT21/OUT77
P1.4/IN20/EMG_IN/OUT20/OUT76
VD D O S C 3
VD D O S C
VS S O S C
XTAL2
XTAL1
VS S
VD D P
VD D
P1.3/IN19/OUT19/OUT75
P1.11/IN27/IN51/SCLK1B/OUT27/OUT51
P1.10/IN26/IN50/OUT26/OUT50/SLSO17
P1.9/IN25/IN49/MRST1B/OUT25/OUT49
P1.8/IN24/IN48/MTSR1B/OUT24/OUT48
P1.2/IN18/OUT18/OUT74
P1.1/IN17/OUT17/OUT73
P1.0/IN16/OUT16/OUT72
P4.3/IN31/IN55/OUT31/OUT55/SYSCLK
N.C.
AN19
AN18
AN17
AN16
AN15
AN14
VA GN D 0
V
A R EF 0
VS SM
VDD M
AN13
AN12
AN11
AN10
AN9
AN8
AN6
AN5
AN4
AN3
AN2
AN1
AN0
V
VD DDDP
VS S
AD0EMUX2/P1.14
AD0EMUX1/P1.13
AD0EMUX0/P1.12
TCLK0A/OUT32/IN32/P2.0
SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1
T VALID0A/OUT34/IN34/P2.2
TDAT A0A/OUT35/IN54/P2.3
OUT36/RCLK0A/IN36/P2.4
RREADY0A/OUT37/IN37/P2.5
OUT 38/RVALID0A/IN38/P2.6
OUT39/RDATA0A/IN39/P2.7
V
VD DS PS
VDD
VS S
OUT52/OUT28/HWCF G0/IN52/IN28/P4.0
OUT53/OUT29/HWCF G1/IN53/IN29/P4.1
OUT54/OUT30/HWCF G2/IN54/IN30/P4.2
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
OCDSDBG0/OUT40/IN40/P5.0
OCDSDBG1/OUT41/IN41/P5.1
OCDSDBG2/OUT42/IN42/P5.2
OCDSDBG3/OUT43/IN43/P5.3
OCDSDBG4/OUT44/IN44/P5.4
OCDSDBG5/OUT45/IN45/P5.5
OCDSDBG6/OUT46/IN46/P5.6
OCDSDBG7/OUT47/IN47/P5.7
TRCLK
VDD
VD D P
VS S
OCDSDBG8/TDATA1/RDATA0B/P5.8
OCDSDBG9/TVALID1/RVALID0B/P5.9
OCDSDBG10/RREADY0B/TREADY1/P5.10
OCDSDBG11/TCLK1/RCLK0B/P5.11
OCDSDBG12/TDATA0B/RDATA1/P5.12
OCDSDBG13/TVALID0B/RVALID1/P5.13
OCDSDBG14/RREADY1/TREADY0B/P5.14
OCDSDBG15/TCLK0B/RCLK1/P5.15
N.C.
VS S A F
VDDAF
VD D M F
V
V S SR EM FF
V FA
FA G N D
AN35
AN34
AN33
AN32
AN31
AN30
AN29
AN28
AN7
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P0.15/I N15/SWCFG15/REQ5/OUT15/OUT71
P0.14/I N14/SWCFG14/REQ4/OUT14/OUT70
P0.7/IN7/SWCFG7/REQ3/OUT7/OUT 63
P0.6/IN6/SWCFG6/REQ2/OUT6/OUT 62
VS S
VD D P
VD D
P0.13/I N13/SWCFG13/OUT13/OUT69
P0.12/I N12/SWCFG12/OUT12/OUT68
P0.5/IN5/SWCFG5/OUT5/OUT61
P0.4/IN4/SWCFG4/OUT4/OUT60
P2.13/SLSI1/SDI0
P2.8/SLSO04/SLSO14/EN00
P2.12/M TSR1A/SOP0B
P2.11/SCLK1A/F CLP0B
P2.10/M RST1A
P2.9/SLSO05/SLSO15/EN01
SOP0A
SON0
FCLP0A
FCLN0
V
VSD DS P
VD D
P0.11/I N11/SWCFG11/OUT11/OUT67
P0.10/I N10/SWCFG10/OUT10/OUT66
P0.9/IN9/SWCFG9/OUT9/OUT65
P0.8/IN8/SWCFG8/OUT8/OUT64
P0.3/IN3/SWCFG3/OUT3/OUT59
P0.2/IN2/SWCFG2/OUT2/OUT58
P0.1/IN1/SWCFG1/OUT1/OUT57
P0.0/IN0/SWCFG0/OUT0/OUT56
P3.11/REQ1
P3.12/RXDCAN01) /RXD0B
P3.13/T XDCAN01 ) /TXD0B
VD D FL 3
VS S
VD D P
P3.9/RXD1A
P3.10/REQ0
P3.0/RXD0A
P3.1/T XD0A
P3.14/RXDCAN11) /RXD1B
P3.15/T XDCAN11 ) /TXD1B
Figure 2-3 shows the TC1165/TC1166 pin configuration.
1) Not applicable to TC1165
Figure 2-3
Data Sheet
TC1165/TC1166 Pinning
TC1165/TC1166 Pinning for PG-LQFP-176-2 Package
8
V0.2, 2006-02
TC1165/TC1166
Advance Information
2.4
General Device Information
Pad Driver and Input Classes Overview
The TC1165/TC1166 provides different types and classes of input and output lines. For
understanding of the abbreviations in Table 2-1 starting at the next page, Table 4-1
gives an overview on the pad type and class types.
Data Sheet
9
V0.2, 2006-02
TC1165/TC1166
Advance Information
2.5
General Device Information
Pin Definitions and Functions
Table 2-1 shows the TC1165/TC1166 pin definitions and functions.
Table 2-1
Symbol
Pin Definitions and Functions
Pins I/O Pad
Driver
Class
Power Functions
Supply
Parallel Ports
P0
I/O A1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
145
146
147
148
166
167
173
P0.7
174
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
149
150
151
152
168
169
175
P0.15
176
VDDP
Port 0
Port 0 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively
used for GPTA I/O lines or external trigger
inputs.
IN0 / OUT0 /
IN1 / OUT1 /
IN2 / OUT2 /
IN3 / OUT3 /
IN4 / OUT4 /
IN5 / OUT5 /
IN6 / OUT6 /
REQ2
IN7 / OUT7 /
REQ3
IN8 / OUT8 /
IN9 / OUT9 /
IN10 / OUT10 /
IN11 / OUT11 /
IN12 / OUT12 /
IN13 / OUT13 /
IN14 / OUT14 /
REQ4
IN15 / OUT15 /
REQ5
OUT56 line of GPTA
OUT57 line of GPTA
OUT58 line of GPTA
OUT59 line of GPTA
OUT60 line of GPTA
OUT61 line of GPTA
OUT62 line of GPTA
External trigger input 2
OUT63 line of GPTA
External trigger input 3
OUT64 line of GPTA
OUT65 line of GPTA
OUT66 line of GPTA
OUT67 line of GPTA
OUT68 line of GPTA
OUT69 line of GPTA
OUT70 line of GPTA
External trigger input 4
OUT71 line of GPTA
External trigger input 5
In addition, the state of the port pins are
latched into the software configuration input
register SCU_SCLIR at the rising edge of
HDRST. Therefore, Port 0 pins can be used
for operating mode selections by software.
Data Sheet
10
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
General Device Information
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
P1
Power Functions
Supply
VDDP
I/O
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
91
92
93
98
107
108
109
110
94
A1
A1
A1
A1
A1
A1
A1
A1
A2
P1.9
95
A2
P1.10
96
A2
P1.11
97
A2
P1.12
73
A1
P1.13
72
A1
P1.14
71
A1
Port 1
Port 1 is a 15-bit bi-directional general
purpose I/O port which can be alternatively
used for GPTA I/O lines, SSC1 and ADC0
interface.
IN16 / OUT16 /
IN17 / OUT17 /
IN18 / OUT18 /
IN19 / OUT19 /
IN20 / OUT20 /
IN21 / OUT21 /
IN22 / OUT22 /
IN23 / OUT23 /
IN24 / OUT24 /
MTSR1B
OUT72 line of GPTA
OUT73 line of GPTA
OUT74 line of GPTA
OUT75 line of GPTA
OUT76 line of GPTA
OUT77 line of GPTA
OUT78 line of GPTA
OUT79 line of GPTA
IN48 / OUT48 line of GPTA
SSC1 master transmit
output / slave rec. input B
IN25 / OUT25 / IN49 / OUT49 line of GPTA
MRST1B
SSC1 master receive input /
slave transmit output B
IN26 / OUT26 / IN50 / OUT50 line of GPTA
SLSO17
SSC1 slave select output 7
IN27 / OUT27 / IN51 / OUT51 line of GPTA
SCLK1B
SSC1 clock input / output B
AD0EMUX0
ADC0 external multiplexer
control output 0
AD0EMUX1
ADC0 external multiplexer
control output 1
AD0EMUX2
ADC0 external multiplexer
control output 2
In addition, P1.4 also serves as emergency
shut-off input for certain I/O lines (e.g. GPTA
related outputs).
Data Sheet
11
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
P2
P2.0
P2.1
P2.2
General Device Information
VDDP
I/O
74
75
76
Power Functions
Supply
Port 2
Port 2 is a 14-bit bi-directional generalpurpose I/O port which can be alternatively
used for GPTA I/O, and interface for MLI0,
MSC0 or SSC0/1.
A2
TCLK0A
A2
IN32 / OUT32
TREADY0A
A2
IN33 / OUT33
SLSO03
SLSO13
TVALID0A
P2.3
77
A2
IN34 / OUT34
TDATA0A
P2.4
78
A1
IN35 / OUT35
RCLK0A
P2.5
79
A2
IN36 / OUT36
RREADY0A
A1
IN37 / OUT37
RVALID0A
A1
IN38 / OUT38
RDATA0A
P2.6
P2.7
80
81
IN39 / OUT39
Data Sheet
12
MLI0 transmit channel clock
output A
line of GPTA
MLI0 transmit channel ready
input A
line of GPTA
SSC0 slave select output 3
SSC1 slave select output 3
MLI0 transmit channel valid
output A
line of GPTA
MLI0 transmit channel data
output A
line of GPTA
MLI0 receive channel clock
input A
line of GPTA
MLI0 receive channel ready
output A
line of GPTA
MLI0 receive channel valid
input A
line of GPTA
MLI0 receive channel data
input A
line of GPTA
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
P2.8
164
A2
P2.9
160
A2
P2.10
161
A2
P2.11
162
A2
P2.12
163
A2
P2.13
Data Sheet
General Device Information
165
A1
Power Functions
Supply
SLSO04
SLSO14
EN00
SLSO05
SLSO15
EN01
MRST1A
SCLK1A
FCLP0B
MTSR1A
SOP0B
SLSI1
SDI0
13
SSC0 Slave Select output 4
SSC1 Slave Select output 4
MSC0 enable output 0
SSC0 Slave Select output 5
SSC1 Slave Select output 5
MSC0 enable output 1
SSC1 master receive input /
slave transmit output A
SSC1 clock input/output A
MSC0 clock output B
SSC1 master transmit out /
slave receive input A
MSC0 serial data output B
SSC1 slave select input
MSC0 serial data input
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
P3
P3.0
P3.1
General Device Information
VDDP
I/O
136
135
Power Functions
Supply
A2
A2
Port 3
Port 3 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively
used for ASC0/1, SSC0/1 and CAN lines.
RXD0A
TXD0A
ASC0 receiver inp./outp. A
ASC0 transmitter output A
This pin is sampled at the rising edge of
PORST. If this pin and the BYPASS input pin
are both active, then oscillator bypass mode is
entered.
P3.2
P3.3
129
130
A2
A2
SCLK0
MRST0
P3.4
132
A2
MTSR0
P3.5
126
A2
P3.6
127
A2
P3.7
131
A2
P3.8
128
A2
P3.9
P3.10
P3.11
P3.12
138
137
144
143
A2
A1
A1
A2
P3.13
142
A2
P3.14
134
A2
P3.15
133
A2
SLSO00
SLSO10
SLSO01
SLSO11
SLSI0
SLSO02
SLSO12
SLSO06
TXD1A
RXD1A
REQ0
REQ1
RXDCAN01)
RXD0B
TXDCAN01)
TXD0B
RXDCAN11)
RXD1B
TXDCAN11)
TXD1B
Data Sheet
14
SSC0 clock input/output
SSC0 master receive input/
slave transmit output
SSC0 master transmit
output/slave receive input
SSC0 slave select output 0
SSC1 slave select output 0 2)
SSC0 slave select output 1
SSC1 slave select output 12)
SSC0 slave select input
SSC0 slave select output 2
SSC1 slave select output 2
SSC0 slave select output 6
ASC1 transmitter output A
ASC1 receiver inp./outp. A
External trigger input 0
External trigger input 1
CAN node 0 receiver input
ASC0 receiver inp./outp. B
CAN node 0 transm. output
ASC0 transmitter output B
CAN node 1 receiver input
ASC1 receiver inp./outp. B
CAN node 1 transm. output
ASC1 transmitter output B
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
General Device Information
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
P4
Power Functions
Supply
VDDP
I/O
P4.[3:0]
Port 4 / Hardware Configuration Inputs
HWCFG[3:0]
Boot mode and boot location
inputs; inputs are latched
with the rising edge of
HDRST.
During normal operation, Port 4 pins may be
used as alternate functions for GPTA or
system clock output.
P4.0
P4.1
P4.2
P4.3
Data Sheet
86
87
88
90
A1
A1
A2
A2
IN28 / OUT28 /
IN29 / OUT29 /
IN30 / OUT30 /
IN31 / OUT31 /
SYSCLK
15
IN52 / OUT52 line of GPTA
IN53 / OUT53 line of GPTA
IN54 / OUT54 line of GPTA
IN55 / OUT55 line of GPTA
System Clock Output
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
P5
P5.0
General Device Information
I/O A2
Power Functions
Supply
VDDP
Port 5
Port 5 is a 16-bit bi-directional generalpurpose I/O port. In emulation, it is used as a
trace port for OCDS Level 2 debug lines. In
normal operation, it is used for GPTA I/O or
the MLI0/1 interface.
1
OCDSDBG0
2
IN40 / OUT40
OCDSDBG1
P5.2
3
IN41 / OUT41
OCDSDBG2
P5.3
4
IN42 / OUT42
OCDSDBG3
5
IN43 / OUT43
OCDSDBG4
6
IN44 / OUT44
OCDSDBG5
7
IN45 / OUT45
OCDSDBG6
8
IN46 / OUT46
OCDSDBG7
P5.1
P5.4
P5.5
P5.6
P5.7
IN47 / OUT47
Data Sheet
16
OCDS L2 Debug Line 0
(Pipeline Status Sig. PS0)
line of GPTA
OCDS L2 Debug Line 1
(Pipeline Status Sig. PS1)
line of GPTA
OCDS L2 Debug Line 2
(Pipeline Status Sig. PS2)
line of GPTA
OCDS L2 Debug Line 3
(Pipeline Status Sig. PS3)
line of GPTA
OCDS L2 Debug Line 4
(Pipeline Status Sig. PS4)
line of GPTA
OCDS L2 Debug Line 5
(Break Qualification Line
BRK0)
line of GPTA
OCDS L2 Debug Line 6
(Break Qualification Line
BRK1)
line of GPTA
OCDS L2 Debug Line 7
(Break Qualification Line
BRK2)
line of GPTA
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
General Device Information
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
P5.8
13
Power Functions
Supply
OCDSDBG8
TDATA1
RDATA0B
P5.9
14
OCDSDBG9
TVALID1
RVALID0B
P5.10
15
OCDSDBG10
TREADY1
RREADY0B
P5.11
16
OCDSDBG11
TCLK1
RCLK0B
P5.12
17
OCDSDBG12
RDATA1
TDATA0B
P5.13
18
OCDSDBG13
RVALID1
TVALID0B
Data Sheet
17
OCDS L2 Debug Line 8
(Indirect PC Addr. PC0)
MLI1 transmit channel data
output
MLI0 receive channel data
input B
OCDS L2 Debug Line 9
(Indirect PC Addr. PC1)
MLI1 transmit channel valid
output
MLI0 receive channel valid
input B
OCDS L2 Debug Line 10
(Indirect PC Addr. PC2)
MLI1 transmit channel ready
input
MLI0 receive channel ready
output B
OCDS L2 Debug Line 11
(Indirect PC Addr. PC3)
MLI1 transmit channel clock
output
MLI0 receive channel clock
input B
OCDS L2 Debug Line 12
(Indirect PC Addr. PC04)
MLI1 receive channel data
input
MLI0 transmit channel data
output B
OCDS L2 Debug Line 13
(Indirect PC Addr. PC05)
MLI1 receive channel valid
input
MLI0 transmit channel valid
output B
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
General Device Information
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
P5.14
19
Power Functions
Supply
OCDSDBG14
RREADY1
TREADY0B
P5.15
20
OCDSDBG15
RCLK1
TCLK0B
OCDS L2 Debug Line 14
(Indirect PC Address PC6)
MLI1 receive channel ready
output
MLI0 transmit channel ready
input B
OCDS L2 Debug Line 15
(Indirect PC Address PC7)
MLI1 receive channel clock
input
MLI0 transmit channel clock
output B
MSC0 Outputs
C
FCLP0A 157
O
FCLN0
156
O
SOP0A
159
O
SON0
158
O
Data Sheet
VDDP
LVDS MSC Clock and Data Outputs4)
MSC0 Differential Driver Clock Output
Positive A
MSC0 Differential Driver Clock Output
Negative
MSC0 Differential Driver Serial Data Output
Positive A
MSC0 Differential Driver Serial Data Output
Negative
18
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
Symbol
General Device Information
Pin Definitions and Functions (cont’d)
Pins I/O Pad
Driver
Class
Power Functions
Supply
Analog Inputs
AN[35:0]
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
Data Sheet
I
67
66
65
64
63
62
61
36
60
59
58
57
56
55
50
49
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
D
–
Analog Input Port
The Analog Input Port provides altogether 36
analog input lines to ADC0 and FADC.
AN[31:0]: ADC0 analog inputs [31:0]
AN[35:32]: FADC analog differential inputs
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7
Analog input 8
Analog input 9
Analog input 10
Analog input 11
Analog input 12
Analog input 13
Analog input 14
Analog input 15
Analog input 16
Analog input 17
Analog input 18
Analog input 19
Analog input 20
Analog input 21
Analog input 22
Analog input 23
Analog input 24
Analog input 25
Analog input 26
Analog input 27
Analog input 28
Analog input 29
Analog input 30
19
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
General Device Information
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
Power Functions
Supply
AN31
AN32
AN33
AN34
AN35
32
31
30
29
28
I
D
–
Analog input 31
Analog input 32
Analog input 33
Analog input 34
Analog input 35
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
JTAG Module Reset/Enable Input
VDDP
VDDP
VDDP
Trace Clock for OCDS_L2 Lines4)
System I/O
TRST
114
I
A23)
TCK
115
I
A23)
TDI
111
I
A13)
TDO
113
O
A2
A2
3)
JTAG Module Clock Input
JTAG Module Serial Data Input
JTAG Module Serial Data Output
TMS
112
I
BRKIN
117
I/O A3
BRK
OUT
116
I/O A3
TRCLK
9
O
A4
NMI
120
I
A26)7)
HDRST
122
I/O A28)
PORST
121
I
A26)7)
VDDP
Power-on Reset Input
BYPASS 119
I
A13)
VDDP
PLL Clock Bypass Select Input
This input has to be held stable during poweron resets. With BYPASS = 1, the spike filters
in the HDRST, PORST and NMI inputs are
switched off.
TEST
MODE
118
I
A26)10)
VDDP
Test Mode Select Input
For normal operation of the TC1165/TC1166,
this pin should be connected to high level.
XTAL1
XTAL2
102
103
I
O
n.a.
VDDOSC Oscillator/PLL/Clock Generator
9)
Data Sheet
JTAG Module State Machine Control Input
OCDS Break Input (Alternate Output)4)5)
OCDS Break Output (Alternate Input)4)5)
Non-Maskable Interrupt Input
Hardware Reset Input /
Reset Indication Output
Input/Output Pins
20
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
General Device Information
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
Power Functions
Supply
N.C.
21,
89
–
–
–
Not Connected
These pins are reserved for future extension
and must not be connected externally.
Power Supplies
VDDM
VSSM
VDDMF
VSSMF
VDDAF
54
–
–
–
ADC Analog Part Power Supply (3.3 V)
53
–
–
–
ADC Analog Part Ground for VDDM
24
–
–
–
FADC Analog Part Power Supply (3.3 V)
25
–
–
–
FADC Analog Part Ground for VDDMF
23
–
–
–
FADC Analog Part Logic Power Supply
(1.5 V)
VSSAF
VAREF0
VAGND0
VFAREF
VFAGND
VDDOSC
22
–
–
–
FADC Analog Part Logic Ground for VDDAF
52
–
–
–
ADC Reference Voltage
51
–
–
–
ADC Reference Ground
26
–
–
–
FADC Reference Voltage
27
–
–
–
FADC Reference Ground
105
–
–
–
Main Oscillator and PLL Power Supply
(1.5 V)
VDDOSC3
VSSOSC
VDDFL3
VDD
106
–
–
–
Main Oscillator Power Supply (3.3 V)
104
–
–
–
Main Oscillator and PLL Ground
141
–
–
–
Power Supply for Flash (3.3 V)
10, –
68,
84,
99,
123,
153,
170
–
–
Core Power Supply (1.5 V)
Data Sheet
21
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-1
General Device Information
Pin Definitions and Functions (cont’d)
Symbol
Pins I/O Pad
Driver
Class
Power Functions
Supply
VDDP
11, –
69,
83,
100,
124,
154,
171,
139
–
–
Port Power Supply (3.3 V)
VSS
12, –
70,
85,
101,
125,
155,
172,
140,
82
–
–
Ground
1) Not applicable to TC1165
2) The logical AND function of the two slave select outputs is available as a third alternate output function.
3) These pads are I/O pads with input only function. Its input characteristics are identical with the input
characteristics as defined for class A pads.
4) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range),
an undefined output driving level may occur at these pins.
5) Programmed by software as either break input or break output.
6) These pads are input only pads with input characteristics.
7) Input only pads with input spike filter.
8) Open drain pad with input spike filter.
9) The dual input reset system of TC1165/TC1166 assumes that the PORST reset pin is used for power on reset
only.
10) Input only pads without input spike filter.
Data Sheet
22
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 2-2
General Device Information
List of Pull-up/Pull-down Reset Behavior of the Pins
Pins
PORST = 0
PORST = 1
All GPIOs, TDI, TMS, TDO
Pull-up
HDRST
Drive-low
Pull-up
BYPASS
Pull-up
High-impedance
TRST, TCK
High-impedance
Pull-down
TRCLK
High-impedance
BRKIN, BRKOUT, TESTMODE Pull-up
NMI, PORST
Data Sheet
Pull-down
23
V0.2, 2006-02
TC1165/TC1166
Advance Information
3
Functional Description
Functional Description
Chapter 3 provides an overview of the TC1165/TC1166 functional description.
3.1
System Architecture and On-Chip Bus Systems
The TC1165/TC1166 has two independent on-chip buses (see also TC1165/TC1166
block diagram on Page 2-6):
•
•
Local Memory Bus (LMB)
System Peripheral Bus (SPB)
The LMB Bus connects the CPU local resources for data and instruction fetch. The Local
Memory Bus interconnects the memory units and functional units, such as CPU and
PMU. The main target of the LMB bus is to support devices with fast response times,
optimized for speed. This allows the DMI and PMI fast access to local memory and
reduces load on the FPI bus. The Tricore system itself is located on LMB bus.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable
length 64-bit block transfers.
The SPB Bus is mainly governed by the PCP and is accessible to the CPU via the LMB
Bus bridge. The System Peripheral Bus (SPB Bus) in TC1165/TC1166 is an on-chip FPI
Bus. The FPI Bus interconnects the functional units of the TC1165/TC1166, such as the
DMA and on-chip peripheral components. The FPI Bus is designed to be quick to be
acquired by on-chip functional units, and quick to transfer data. The low setup overhead
of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for
time-critical applications.The FPI Bus is designed to sustain high transfer rates. For
example, a peak transfer rate of up to 320 Mbyte/s can be achieved with a 80 MHz bus
clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI
Bus to operate at close to its peak bandwidth.
Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed
is 80 MHz.
Additionally, two simplified bus interfaces are connected to and controlled by the DMA
Controller:
•
•
DMA Bus
SMIF Interface
Data Sheet
24
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.2
Functional Description
On-Chip Memories
As shown in the TC1165/TC1166 block diagram on Page 2-6, some of the
TC1165/TC1166 units provide on-chip memories that are used as program or data
memory.
•
•
•
•
•
•
Program memory in PMU
– 16 Kbyte Boot ROM (BROM)
– 1504 Kbyte Program Flash (PFlash)
Program memory in PMI
– 16 Kbyte Scratch-Pad RAM (SPRAM)
– 8 Kbyte Instruction Cache (ICACHE)
Data memory in PMU
– 32 Kbyte Data Flash (DFlash)
– 8 Kbyte Overlay RAM (OVRAM)
Data memory in DMI
– 56 Kbyte Local Data RAM (LDRAM)
Memory of PCP2
– 12 Kbyte Code Memory (CMEM) with parity error protection
– 8 Kbyte Parameter RAM (PRAM) with parity error protection
On-chip SRAM with parity error protection
Features of Program Flash
•
•
•
•
•
•
•
•
•
•
1504 Kbyte on-chip program Flash memory
Usable for instruction code or constant data storage
256-byte program interface
– 256 bytes are programmed into PFLASH page in one step/command
256-bit read interface
– Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers
Dynamic correction of single-bit errors during read access
Detection of double-bit errors
Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte, one 512 Kbyte and one 480 Kbyte
sectors
– Each sector separately erasable
– Each sector separately write-protectable
Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
Password mechanism for temporary disabling of write and read protection
Data Sheet
25
V0.2, 2006-02
TC1165/TC1166
Advance Information
•
•
•
Functional Description
On-chip generation of programming voltage
JEDEC-standard based command sequences for PFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic PFLASH bits
Features of Data Flash
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32 Kbyte on-chip data Flash memory, organized in two 16 Kbyte banks
Usable for data storage with EEPROM functionality
128 Byte of program interface
– 128 bytes are programmed into one DFLASH page by one step/command
64-bit read interface (no burst transfers)
Dynamic correction of single-bit errors during read access
Detection of double-bit errors
Fixed sector architecture
– Two 16 Kbyte banks/sectors
– Each sector separately erasable
Configurable read protection (combined with write protection) for complete DFLASH
together with PFLASH read protection
Password mechanism for temporary disabling of write and read protection
Erasing/programming of one bank possible while reading data from the other bank
Programming of one bank while erasing the other bank possible
On-chip generation of programming voltage
JEDEC-standard based command sequences for DFLASH control
– Write state machine controls programming and erase operations
– Status and error reporting by status flags and interrupt
Margin check for detection of problematic DFLASH bits
Data Sheet
26
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3
Functional Description
Memory Maps
This chapter gives an overview of the TC1165/TC1166 memory map and describes the
address locations and access possibilities for the units, memories, and reserved areas
as “seen” from different on-chip buses’ (SPB and LMB) point of view.
3.3.1
Architectural Address Map
Table 3-1 shows the overall architectural address map as defined for the TriCore and as
implemented in TC1165/TC1166.
Table 3-1
TC1165/TC1166 Architectural Address Map
Segment
Contents
Size
Description
0-7
Global
8 x 256
Mbyte
Reserved (MMU space); cached
8
Global
Memory
256 Mbyte
Reserved (246 Mbyte); PMU, Boot ROM;
cached
9
Global
Memory
256 Mbyte
FPI space; cached
10
Global
Memory
256 Mbyte
Reserved (246 Mbyte), PMU, Boot ROM; noncached
11
Global
Memory
256 Mbyte
FPI space; non-cached
12
Local LMB
Memory
256 Mbyte
Reserved; bottom 4 Mbyte visible from FPI bus
in segment 14; cached
13
DMI
64 Mbyte
Local Data Memory RAM; non-cached
PMI
64 Mbyte
Local Code Memory RAM; non-cached
EXT_PER
96 Mbyte
Reserved; non-cached
EXT_EMU
16 Mbyte
Reserved; non-cached
BOOTROM
16 Mbyte
Boot ROM space, Boot ROM mirror;
non-cached
Data Sheet
27
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-1
Functional Description
TC1165/TC1166 Architectural Address Map (cont’d)
Segment
Contents
Size
Description
14
EXTPER
128 Mbyte
Reserved;
non-speculative; non-cached; no execution
CPU[0 ..15]
image region
16 x 8
Mbyte
Non-speculative; non-cached; no execution
LMB_PER
CSFRs
INT_PER
256
Mbyte
CSFRs of CPUs[0 ..15];
LMB & FPI Peripheral Space;
non-speculative; non-cached;
no execution
15
Data Sheet
28
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3.2
Functional Description
How to Read the Address Maps
The bus-specific address maps describe how the different bus master devices react on
accesses to on-chip memories and modules, and which address ranges are valid or
invalid for the corresponding buses.
The FPI Bus address map shows the system addresses from the point of view of the
SPB master agents. SPB master agents are PCP2 and OCDS, and DMA.
The LMB address map shows the system addresses from the point of view of the LMB
master agents. LMB master agents are PMI and DMI.
Table 3-2 defines the acronyms and other terms that are used in the address maps
(Table 3-3 to Table 3-5).
Table 3-2
Definition of Acronyms and Terms
Term
Description
…BE
Means “Bus error” generation.
…BET
Means “Bus error & trap” generation.
SPBBE
A bus access is terminated with a bus error on the SPB.
SPBBET
A bus access is terminated with a bus error on the SPB and a DSE
trap (read access) or DAE trap (write access).
LMBBE
A bus access is terminated with a bus error on the LMB.
LMBBET
A bus access is terminated with a bus error on the LMB and a DSE
trap (read access) or DAE trap (write access).
access
A bus access is allowed and is executed.
ignore
A bus access is ignored and is not executed. No bus error is
generated.
trap
A DSE trap (read access) or DAE trap (write access) is generated.
32
Only 32-bit word bus accesses are permitted to that
register/address range.
nE
A bus access generates no bus error, although the bus access
points to an undefined address or address range. This is valid e.g.
for CPU accesses (MTCR/MFCR) to undefined addresses in the
CSFR range.
Data Sheet
29
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3.3
Functional Description
Contents of the Segments
This section summarizes the contents of the segments.
Segments 0-7
These segments are reserved segments in the TC1165/TC1166.
Segment 8
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
Segment 9
This memory segment is reserved in the TC1165/TC1166.
Segment 10
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM).
Segment 11
This memory segment is reserved in the TC1165/TC1166.
Segment 12
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is
reserved in the TC1165/TC1166.
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to the PMU memory, OVRAM.
Segment 13
From the SPB point of view (PCP, DMA and Cerberus), this memory segment is
reserved in the TC1165/TC1166.
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to the PMI scratch-pad RAM, read access to the boot ROM and test ROM
(BROM and TROM) and the DMI memories (LDRAM).
Data Sheet
30
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Segment 14
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to the PMU Overlay memory (OVRAM), the DMI Local Data RAM (LDRAM),
and the PMI scratch-pad RAM (SPRAM).
From the CPU point of view (PMI and DMI), this memory segment is reserved in the
TC1165/TC1166.
Segment 15
From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows
accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows.
From the CPU point of view (PMI and DMI), this memory segment allows accesses to all
SFRs and CSFRs, the PCP memories, and the MLI transfer windows.
Data Sheet
31
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3.4
Functional Description
Address Map of the FPI Bus System
Table 3-3 and Table 3-4 shows the address maps of the FPI Bus System.
3.3.4.1
Segments 0 to 14
Table 3-3 shows the address maps of segments 0 to 14 as it is seen from the SPB bus
masters PCP, DMA and OCDS.
Table 3-3
SPB Address Map of Segment 0 to 14
Seg- Address
ment Range
Size
0-7
0000 0000H 0000 0007H
8 byte
0000 0008H 7FFF FFFFH
8
9
Description
Access Type
Read
Write
MPN trap
MPN trap
8 × 256
Mbyte
SPBBE
SPBBE
8000 0000H 8017 7FFFH
1.5 Mbyte Program Flash (PFLASH)
access
access1)
8017 8000H 807F FFFFH
6.5 Mbyte Reserved
LMBBE &
SPBBE
LMBBE
8080 0000H 8FDF FFFFH
246
Mbyte
Reserved
LMBBE &
SPBBE
LMBBE
8FE0 0000H 8FE0 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 0
access
access1)
8FE0 4000H 8FE0 FFFFH
48 Kbyte
Reserved
LMBBE &
SPBBE
LMBBE
8FE1 0000H 8FE1 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 1
access
access1)
8FE1 4000H 8FF1 FFFFH
1 Mbyte
Reserved
LMBBE &
SPBBE
LMBBE
8FF2 0000H 8FF5 FFFFH
256
Kbyte
Reserved
8FF6 0000H 8FFF BFFFH
624
Kbyte
Reserved
Reserved (virtual address
space)
8FFF C000H - 16 Kbyte
8FFF FFFFH
Boot ROM (BROM)
access
9000 0000H 9FFF FFFFH
Reserved
SPBBE
Data Sheet
256
Mbyte
32
SPBBE
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-3
Functional Description
SPB Address Map of Segment 0 to 14 (cont’d)
Seg- Address
ment Range
Size
10
A000 0000H A017 FFFFH
Description
Access Type
Read
Write
1.5 Mbyte Program Flash (PFLASH)
access
access1)
A017 8000H A07F FFFFH
6.5 Mbyte Reserved
LMBBE &
SPBBE
LMBBE
A080 0000H AFDF FFFFH
246
Mbyte
Reserved
LMBBE &
SPBBE
LMBBE
AFE0 0000H AFE0 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 0
access
access1)
AFE0 4000H AFE0 FFFFH
48 Kbyte
Reserved
LMBBE &
SPBBE
LMBBE
AFE1 0000H AFE1 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 1
access
access1)
AFE1 4000H AFF1 FFFFH
1 Mbyte
Reserved
LMBBE &
SPBBE
ignore
AFF2 0000H AFF5 FFFFH
256
Kbyte
Reserved
AFF6 0000H AFFF BFFFH
624
Kbyte
Reserved
AFFF C000H - 16 Kbyte
AFFF FFFFH
Boot ROM (BROM)
access
11
B000 0000H BFFF FFFFH
256
Mbyte
Reserved
SPBBE
SPBBE
12
C000 0000H C000 1FFFH
8 Kbyte
Overlay memory
(OVRAM)
SPBBE
SPBBE
C000 2000H CFFF FFFFH
≈ 256
Mbyte
Reserved
SPBBE
SPBBE
Data Sheet
33
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-3
Functional Description
SPB Address Map of Segment 0 to 14 (cont’d)
Seg- Address
ment Range
Size
13
D000 0000H D000 DFFFH
56 Kbyte
D000 E000H D3FF FFFFH
14
15
Description
Access Type
Read
Write
SPBBE
SPBBE
64 Mbyte Reserved
SPBBE
SPBBE
D400 0000H D400 3FFFH
16 Kbyte
SPBBE
SPBBE
D400 4000H D7FF FFFFH
64 Mbyte Reserved
SPBBE
SPBBE
D800 0000H DEFF FFFFH
112
Mbyte
Reserved
SPBBE
SPBBE
DF00 0000H DFFF FFEFH
≈ 16
Mbyte
Reserved (for Boot Rom)
SPBBE
SPBBE
DFFF FFF0H - 16 byte
DFFF FFFFH
microROM
SPBBE
SPBBE
E000 0000H E7FF FFFFH
128 MB
Reserved
LMBBE
LMBBE
E800 0000H E800 1FFFH
8 Kbyte
Overlay memory
(OVRAM)
access
access
E800 2000H E83F FFFFH
≈4
Mbyte
Reserved
LMBBE
LMBBE
E840 0000H E840 DFFFH
56 Kbyte
DMI Local Data RAM
(LDRAM)
access
access
E840 E000H E84F FFFFH
≈ 1 Mbyte Reserved
LMBBE
LMBBE
E850 0000H E850 3FFFH
16 Kbyte
access
access
E850 4000H E85F FFFFH
≈ 1 Mbyte Reserved
LMBBE
LMBBE
E860 C000H EFFF FFFFH
≈ 122
Mbyte
Reserved
LMBBE
LMBBE
F000 0000H FFFF FFFFH
256
Mbyte
see Table 3-4
DMI Local Data RAM
(LDRAM)
PMI Scratch-Pad RAM
(SPRAM)
PMI Scratch-Pad RAM
(SPRAM)
1) Only applicable when writing Flash command sequences.
Data Sheet
34
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3.4.2
Functional Description
Segment 15
Table 3-4 shows the address map of segment 15 as seen from the SPB bus masters
PCP, DMA and OCDS. Please note that access in Table 3-4 means only that an access
to an address within the defined address range is not automatically incorrect or ignored.
If an access is really addressing a correct address, it can be found in the detailed tables
in the TC116x User’s Manual, Register Overview’s chapter.
Table 3-4
SPB Address Map of Segment 15
Unit
Address
Range
Size
F000 0000H F000 00FFH
Access Type
Read
Write
256
byte
access
access
System Peripheral Bus Control Unit F000 0100H (SBCU)
F000 01FFH
256
byte
access
access
System Timer (STM)
F000 0200H F000 02FFH
256
byte
access
access
Reserved
F000 0300H F000 03FFH
–
SPBBE
SPBBE
On-Chip Debug Support (Cerberus) F000 0400H F000 04FFH
256
byte
access
access
Reserved
F000 0500H F000 07FFH
–
SPBBE
SPBBE
MicroSecond Bus Controller 0
(MSC0)
F000 0800H F000 08FFH
256
byte
access
access
Reserved
F000 0900H F000 09FFH
–
SPBBE
SPBBE
Async./Sync. Serial Interface 0
(ASC0)
F000 0A00H F000 0AFFH
256
byte
access
access
Async./Sync. Serial Interface 1
(ASC1)
F000 0B00H F000 0BFFH
256
byte
access
access
Port 0
F000 0C00H F000 0CFFH
256
byte
access
access
Port 1
F000 0D00H F000 0DFFH
256
byte
access
access
Port 2
F000 0E00H F000 0EFFH
256
byte
access
access
System Control Unit (SCU) and
Watchdog Timer (WDT)
Data Sheet
35
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-4
Functional Description
SPB Address Map of Segment 15 (cont’d)
Unit
Address
Range
Size
Port 3
F000 0F00H F000 0FFFH
Port 4
Access Type
Read
Write
256
byte
access
access
F000 1000H F000 10FFH
256
byte
access
access
Port 5
F000 1100H F000 11FFH
256
byte
access
access
Reserved
F000 1200H F000 12FFH
–
SPBBE
SPBBE
Reserved
F000 1300H F000 13FFH
–
SPBBE
SPBBE
Reserved
F000 1400H F000 14FFH
–
SPBBE
SPBBE
Reserved
F000 1500H F000 15FFH
–
SPBBE
SPBBE
Reserved
F000 1600H F000 16FFH
–
SPBBE
SPBBE
Reserved
F000 1700H F000 17FFH
–
SPBBE
SPBBE
General Purpose Timer Array 0
(GPTA0)
F000 1800H F000 1FFFH
8 × 256
byte
access
access
Reserved
F000 2000H F000 27FFH
–
SPBBE
SPBBE
Reserved
F000 2800H F000 2FFFH
–
SPBBE
SPBBE
Reserved
F000 3000H F000 3BFFH
–
SPBBE
SPBBE
Direct Memory Access Controller
(DMA)
F000 3C00H F000 3EFFH
3 × 256
byte
access
access
Reserved
F000 3F00H F000 3FFFH
–
SPBBE
SPBBE
MultiCAN Controller (CAN)
F000 4000H F000 5FFFH
8 Kbyte access1)
Data Sheet
36
access1)
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-4
Functional Description
SPB Address Map of Segment 15 (cont’d)
Unit
Address
Range
Size
Reserved
F000 6000H F003 FFFFH
Reserved
Access Type
Read
Write
–
SPBBE
SPBBE
F004 0000H F004 3EFFH
–
SPBBE
SPBBE
PCP Registers
F004 3F00H F004 3FFFH
256
byte
access
access
Reserved
F004 4000H F004 FFFFH
–
SPBBE
SPBBE
PCP Data Memory (PRAM)
F005 0000H F005 1FFFH
8 Kbyte nE, 32
nE, 32
Reserved
F005 2000H F005 FFFFH
–
SPBBE
SPBBE
PCP Code Memory (PCODE)
F006 0000H F006 2FFFH
12
Kbyte
nE, 32
nE, 32
Reserved
F006 3000H F007 FFFFH
–
SPBBE
SPBBE
Reserved
F008 0000H F00F FFFFH
–
SPBBE
SPBBE
Reserved
F010 0000H F010 00FFH
–
SPBBE
SPBBE
Synchronous Serial Interface 0
(SSC0)
F010 0100H F010 01FFH
256
byte
access
access
Synchronous Serial Interface 1
(SSC1)
F010 0200H F010 02FFH
256
byte
access
access
Fast Analog-to-Digital Converter
(FADC)
F010 0300H F010 03FFH
256
byte
access
access
Analog-to-Digital Converter 0
(ADC0)
F010 0400H F010 05FFH
2 × 256
byte
access
access
Reserved
F010 0600H F010 07FFH
–
SPBBE
SPBBE
Reserved
F010 0800H F010 9FFFH
–
SPBBE
SPBBE
Data Sheet
37
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-4
Functional Description
SPB Address Map of Segment 15 (cont’d)
Unit
Address
Range
Size
Reserved
F010 A000H F010 BFFFH
Micro Link Interface 0 (MLI0)
Access Type
Read
Write
–
SPBBE
SPBBE
F010 C000H F010 C0FFH
256
byte
access
access
Micro Link Interface 1(MLI1)
F010 C100H F010 C1FFH
256
byte
access
access
Memory Checker (MCHK)
F010 C200H F010 C2FFH
256
byte
access
access
Reserved
F010 C300H F01D FFFFH
–
SPBBE
SPBBE
MLI0 Small Transfer Windows
F01E 0000H F01E 7FFFH
4×8
Kbyte
access
access
MLI1 Small Transfer Windows
F01E 8000H F01E FFFFH
4×8
Kbyte
access
access
Reserved
F01F 0000H F01F FFFFH
–
SPBBE
SPBBE
MLI0 Large Transfer Windows
F020 0000H F023FFFFH
4 × 64
Kbyte
access
access
MLI1 Large Transfer Windows
F024 0000H F027 FFFFH
4 × 64
Kbyte
access
access
Reserved
F028 0000H F7E0 FEFFH
–
SPBBE
SPBBE
CPU
CPU Slave Interface
Registers (CPS)
F7E0 FF00H F7E0 FFFFH
256
byte
access
access
CPU Core SFRs & GPRs
F7E1 0000H F7E1 FFFFH
64
Kbyte
access
access
Reserved
F7E2 0000H F7FF FFFFH
–
SPBBE
SPBBE
Reserved
F800 0000H F800 03FFH
–
SPBBE
SPBBE
Reserved
F800 0400H F800 04FFH
–
LMBBE &
SPBBE
LMBBE
Data Sheet
38
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-4
Functional Description
SPB Address Map of Segment 15 (cont’d)
Unit
Address
Range
Size
Program Memory Unit (PMU)
F800 0500H F800 05FFH
Reserved
Access Type
Read
Write
256
byte
access
access
F800 0600H F800 0FFFH
–
LMBBE &
SPBBE
LMBBE
Flash Register
F800 1000H F800 23FFH
5 Kbyte access
access
Reserved
F800 2400H F801 00FFH
–
LMBBE &
SPBBE
LMBBE
Reserved
F801 0100H F801 01FFH
–
LMBBE &
SPBBE
LMBBE
Reserved
F801 0200H F87F F9FFH
–
LMBBE &
SPBBE
LMBBE
Reserved
F87F FA00H F87F FAFFH
–
LMBBE &
SPBBE
LMBBE
Reserved
F87F FB00H F87F FBFFH
–
LMBBE &
SPBBE
LMBBE
CPU
DMI Registers
F87F FC00H - 256
F87F FCFFH byte
access
access
PMI Registers
F87F FD00H - 256
F87F FDFFH byte
access
access
Local Memory Bus Control Unit
(LBCU)
F87F FE00H F87F FEFFH
256
byte
access
access
LFI Bridge
F87F FF00H F87F FFFFH
256
byte
access
access
Reserved
F880 0000H FFFF FFFFH
–
LMBBE &
SPBBE
LMBBE
1) For TC1165, read and write accesses to this address range will not generate any traps.
Data Sheet
39
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.3.5
Functional Description
Address Map of the Local Memory Bus (LMB)
Table 3-5 shows the address map as seen from the LMB bus masters (PMI and DMI).
Table 3-5
LMB Address Map
Seg- Address
ment Range
Size
0-71)
0000 0000H 0000 0007H
8 byte
0000 0008H 7FFF FFFFH
8 × 256
Mbyte
8000 0000H 8017 7FFFH
1.5 Mbyte Program Flash (PFLASH) access
access2)
8017 8000H 807F FFFFH
6.5 Mbyte Reserved
LMBBET
LMBBET
8080 0000H 8FDF FFFFH
246
Mbyte
Reserved
LMBBET
LMBBET
8FE0 0000H 8FE0 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 0
access
access2)
8FE0 4000H 8FE0 FFFFH
48 Kbyte
Reserved
LMBBET
LMBBET
8FE1 0000H 8FE1 3FFFH
16 Kbyte
Data Flash (DFLASH)
Bank 1
access
access2)
8FE1 4000H 8FF1 FFFFH
1 Mbyte
Reserved
LMBBET
LMBBET
8FF2 0000H 8FF5 FFFFH
256 Kbyte Reserved
8FF6 0000H 8FFF BFFFH
624 Kbyte Reserved
81)
91)
Description
Action
Read
Reserved (virtual address MPN trap
space)
SPBBET
8FFF C000H - 16 Kbyte
8FFF FFFFH
Boot ROM (BROM)
access
9000 0000H 9FFF FFFFH
Reserved
SPBBET
Data Sheet
256
Mbyte
40
Write
MPN trap
SPBBE
SPBBE
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-5
LMB Address Map (cont’d)
Seg- Address
ment Range
10
3)
Functional Description
Size
Description
Action
Read
Write
A000 0000H A017 FFFFH
1.5 Mbyte Program Flash (PFLASH) access
access2)
A017 8000H A07F FFFFH
6.5 Mbyte Reserved
LMBBET
LMBBET
A080 0000H AFDF FFFFH
246
Mbyte
Reserved
LMBBET
LMBBET
AFE0 0000H - 16 Kbyte
AFE0 3FFFH
Data Flash (DFLASH)
Bank 0
access
access2)
AFE0 4000H - 48 Kbyte
AFE0 FFFFH
Reserved
LMBBET
LMBBET
AFE1 0000H - 16 Kbyte
AFE1 3FFFH
Data Flash (DFLASH)
Bank 1
access
access2)
AFE1 4000H - 1 Mbyte
AFF1 FFFFH
Reserved
LMBBET
LMBBET
AFF2 0000H AFF5 FFFFH
256 Kbyte Reserved
AFF6 0000H AFFF BFFFH
624 Kbyte Reserved
AFFF C000H - 16 Kbyte
AFFF FFFFH
Boot ROM (BROM)
access
113)
B000 0000H BFFF FFFFH
256
Mbyte
Reserved
SPBBET
SPBBE
121)
C000 0000H C000 1FFFH
8 Kbyte
Overlay memory
(OVRAM)
access
access
C000 2000H CFFF FFFFH
256
Mbyte
Reserved
LMBBET
LMBBET
Data Sheet
41
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-5
LMB Address Map (cont’d)
Seg- Address
ment Range
13
3)
143)
Functional Description
Size
Description
Action
Read
Write
DMI Local Data RAM
(LDRAM)
access
SPBBE
access
SPBBE
D000 E000H - 64 Mbyte
D3FF FFFFH
Reserved
LMBBET
LMBBET
D400 0000H D400 3FFFH
16 Kbyte
PMI Scratch-Pad RAM
(SPRAM)
access
access
D400 4000H D7FF FFFFH
≈ 64
Mbyte
Reserved
LMBBET
LMBBET
D800 0000H DEFF FFFFH
112
Mbyte
Reserved
DF00 0000H DFFF FFEFH
16 Mbyte
Reserved (for Boot Rom)
E000 0000H E7FF FFFFH
128
Mbyte
Reserved
LMBBET
LMBBET
E800 0000H EFFF FFFFH
128
Mbyte
Reserved
LMBBET
LMBBET
D000 0000H D000 DFFFH
Data Sheet
56 Kbyte
42
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-5
Functional Description
LMB Address Map (cont’d)
Seg- Address
ment Range
Size
15
F000 0000H F7FF FFFFH
128
Mbyte
F800 0000H F800 03FFH
Description
Action
Read
Write
Address map is identical
to FPI Bus segment 15
address map (see
Table 3-5)
Reserved areas give an
bus error.
SPBBET
SPBBE
1 Kbyte
Reserved
LMBBET
LMBBET
F800 0400H F800 04FFH
256 byte
Reserved
LMBBET
LMBBET
F800 0500H F800 05FFH
256 byte
Program Memory Unit
(PMU)
access
access
F800 0600H F800 0FFFH
≈ 2 Kbyte Reserved
LMBBET
LMBBET
F800 1000H F800 23FFH
5 Kbyte
access
access
F800 2400H F87F FBFFH
≈ 8 Mbyte Reserved
LMBBET
LMBBET
Flash Registers
F87F FC00H - 256 byte
F87F FCFFH
Data Memory Interface
Unit
access
access
F87F FD00H - 256 byte
F87F FDFFH
Program Memory
Interface Unit
access
access
F87F FE00H - 256 byte
F87F FEFFH
LBCU register space
access
access
F87F FF00H F87F FFFFH
256 byte
LFI Bus Bridge
access
access
F880 0000H FFFF FFFFH
≈ 119
Mbyte
Reserved
LMBBET
LMBBET
1) Cached area
2) Only applicable when writing Flash command sequences
3) Non-cached area
Data Sheet
43
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.4
Functional Description
Memory Protection System
The TC1165/TC1166 memory protection system specifies the addressable range and
read/write permissions of memory segments available to the current executing task. The
memory protection system controls the position and range of addressable segments in
memory. It also controls the types of read and write operations allowed within
addressable memory segments. Any illegal memory access is detected by the memory
protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to
handle the error. Thus, the memory protection system protects critical system functions
against both software and hardware errors. The memory protection hardware can also
generate signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1165/TC1166, numbered 0
and 1, which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU. As
the TC1165/TC1166 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive a particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive a particular protection modes.
Each Data Protection Register Sets and Code Protection Register Sets determines the
range and protection modes for a separate memory area. Each set contains a pair of
registers which determine the address range (the Data Segment Protection Registers
and Code Segment Protection Registers) and one register (Data Protection Mode
Register) which determines the memory access modes that applies to the specified
range.
3.5
Peripheral Control Processor
The Peripheral Control Processor (PCP2) in the TC1165/TC1166 performs tasks that
would normally be performed by the combination of a DMA controller and its supporting
CPU interrupt service routines in a traditional computer system. It could easily be
considered as the host processor’s first line of defence as an interrupt-handling engine.
The PCP can unload the CPU from having to service time-critical interrupts. This
provides many benefits, including:
•
•
•
•
Avoiding large interrupt-driven task context-switching latencies in the host processor
Reducing the cost of interrupts in terms of processor register and memory overhead
Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations
Easing the implementation of multitasking operating systems
The PCP2 has an architecture that efficiently supports DMA-type transactions to and
from arbitrary devices and memory addresses within the TC1165/TC1166 and also has
reasonable stand-alone computational capabilities.
Data Sheet
44
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
The PCP2 in the TC1165/TC1166 contains an improved version of the TC1775’s PCP
with the following enhancements:
•
•
•
•
•
Optimized context switching
Support for nested interrupts
Enhanced instruction set
Enhanced instruction execution speed
Enhanced interrupt queueing
The PCP2 is made up of several modular blocks as follows (see Figure 3-1):
•
•
•
•
•
•
PCP Processor Core
Code Memory (CMEM)
Parameter Memory (PRAM)
PCP Interrupt Control Unit (PICU)
PCP Service Request Nodes (PSRN)
System bus interface to the Flexible Peripheral Interface (FPI Bus)
Code
Memory
CMEM
Parameter
Memory
PRAM
PCP
Processor
Core
PCP Service
Req. Nodes
PSRNs
FPI-Interface
FPI Bus
PCP Interrupt
Arbitration Bus
CPU Interrupt
Arbitration Bus
Figure 3-1
Data Sheet
PCP Interrupt
Control Unit
PICU
MCB06135
PCP2 Block Diagram
45
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 3-6
Functional Description
PCP2 Instruction Set Overview
Instruction Group
Description
DMA primitives
Efficient DMA channel implementation
Load/Store
Transfer data between PRAM or FPI memory and the general
purpose registers, as well as move or exchange values
between registers
Arithmetic
Add, subtract, compare and complement
Divide/Multiply
Divide and multiply
Logical
And, Or, Exclusive Or, Negate
Shift
Shift right or left, rotate right or left, prioritize
Bit Manipulation
Set, clear, insert and test bits
Flow Control
Jump conditionally, jump long, exit
Miscellaneous
No operation, Debug
Data Sheet
46
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.6
Functional Description
DMA Controller and Memory Checker
The DMA Controller of the TC1165/TC1166 transfers data from data source locations to
data destination locations without intervention of the CPU or other on-chip devices. One
data move operation is controlled by one DMA channel. Eight DMA channels are
provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA
Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the
TC1165/TC1166, the FPI Bus interfaces are connected to the System Peripheral Bus
and the DMA Bus. The third specific bus interface provides a connection to Micro Link
Interface modules (two MLI modules in the TC1165/TC1166) and other DMA-related
devices (Memory Checker module in the TC1165/TC1166). Clock control, address
decoding, DMA request wiring, and DMA interrupt service request control are
implementation-specific and managed outside the DMA controller kernel. Figure 3-2
shows the implementation details and interconnections of the DMA module.
fDMA
DMA Sub-Block 0
DMA
Requests
of
On-chip
Periph.
Units
Request
Selection/
CH0n_OUT
Arbitration
DMA
Channels
00-07
Transaction
Control Unit
Bus
Switch
FPI Bus
Int erface 0
DMA Controller
System
Periphera
Bus
FPI Bus
Interface 1
Clock
Control
DMA Bus
MLI
Interfac e
MLI0
Address
Decoder
MLI1
Memory
Checker
Interrupt
Request
Nodes
SR[15:0]
DMA Interrupt Control
Arbiter/
Switch
Control
MCB06149
Figure 3-2
Data Sheet
DMA Controller Block Diagram
47
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Features
•
•
•
•
•
•
•
•
•
•
•
8 independent DMA channels
– 8 DMA channels in the DMA Sub-Block
– Up to 8 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
Programmable priority of the DMA Sub-Blocks on the bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered).
Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Support of circular buffer addressing mode
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Micro Link bus interface support
Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
All buses connected to the DMA module must work at the same frequency.
Read/write requests of the System Bus side to the peripherals on DMA Bus are
bridged to the DMA Bus (only the DMA is the master on the DMA bus), allowing easy
access to these peripherals by PCP and CPU
Memory Checker
The Memory Checker Module (MCHK) makes it possible to check the data consistency
of memories. Any SPB bus master may access the memory checker. It is preferable the
DMA does it as described hereafter. It uses DMA 8-bit, 16-bit, or 32-bit moves to read
from the selected address area and to write the value read in a memory checker input
register. With each write operation to the memory checker input register, a polynomial
checksum calculation is triggered and the result of the calculation is stored in the
memory checker result register.
The memory checker uses the standard Ethernet polynomial, which is given by:
G32 = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1
Data Sheet
48
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Note: Although the polynomial above is used for generation, the generation algorithm
differs from the one that is used by the Ethernet protocol.
3.7
Interrupt System
The TC1165/TC1166 interrupt system provides a flexible and time-efficient means of
processing interrupts. An interrupt request can be serviced either by the CPU or by the
Peripheral Control Processor (PCP). These units are called “Service Providers”.
Interrupt requests are called “Service Requests” rather than “Interrupt Requests” in this
document because they can be serviced by either Service Providers.
Each peripheral in the TC1165/TC1166 can generate service requests. Additionally, the
Bus Control Units, the Debug Unit, the PCP, and even the CPU itself can generate
service requests to either of the two Service Providers.
As shown in Figure 3-3, each TC1165/TC1166 unit that can generate service requests
is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a
Service Request Control Register mod_SRCx, where “mod” is the identifier of the
service requesting unit and “x” an optional index. Two arbitration buses connect the
SRNs with two Interrupt Control Units, which handle interrupt arbitration among
competing interrupt service requests, as follows:
•
•
The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and
administers the CPU Interrupt Arbitration Bus.
The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP
and administers the PCP Interrupt Arbitration Bus.
The PCP can make service requests directly to itself (via the PICU), or it can make
service requests to the CPU. The Debug Unit can generate service requests to the PCP
or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can
make service requests to the PCP. The CPU Service Request Nodes are activated
through software.
Depending on the selected system clock frequency fSYS, the number of fSYS clock cycles
per arbitration cycle must be selected as follows:
•
•
fSYS < 60 MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1
fSYS > 60 MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Data Sheet
49
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
PCP
Interrupt
Arbitration Bus
Service
Requestors
CPU
Interrupt
Arbitration Bus
Service Req.
Nodes
PCP Interrupt
Control Unit
Interrupt
Service
Providers
PICU
MSC0
MLI0
MLI1
SSC0
SSC1
ASC0
ASC1
MultiCAN1)
ADC0
FADC
GPTA0
STM
FPU
Flash
Ext. Int
2
4
2
3
3
4
4
6
4
2
38
2
1
1
2
Int. Req.
2
2 SRNs
Int. Ack.
PIPN
2
CCPN
4
4 SRNs
4
Service Req.
Nodes
2
2 SRNs
2
5
3
3 SRNs
3 SRNs
3
5
3
5
3
2
4
4 SRNs
4 SRNs
4
5
4
5
5
5 SRNs
2
2 SRNs
5
5 SRNs
CPU Interrupt
Control Unit
6
4
4 SRNs
5
5 SRNs
4
6
6 SRNs
PCP2
4
ICU
Int. Req.
2
PIPN
2 SRNs
2
38 SRNs
38
Software
and
Breakpoint
Interrupts
CPU
Int. Ack.
CCPN
38
2 SRNs
1 SRN
1 SRN
2 SRNs
2
1
2
1
1
1
1
1
1
4
1
4
2
1
2
1
Service Req.
Nodes
1 SRN
1 SRN
4 SRNs
1 SRN
1
1
1) MultiCAN module and the 6 SRNs are not applicable to TC1165.
1 SRN
Service
Requestors
1
1
4
1
1
LBCU
SBCU
DMA
Cerberus
DMA Bus
TC1165/TC1166 Interrupt System
Figure 3-3
Block Diagram of the TC1165/TC1166 Interrupt System
Data Sheet
50
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.8
Functional Description
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)
Figure 3-4 shows a global view of the functional blocks and interfaces of the two
Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1.
Clock
Control
fASC
A2
P3.0 /
RXD0A
A2
P3.1 /
TXD0A
A2
P3.12 /
RXD0B
A2
P3.13 /
TXD0B
RXD_I0
Address
Decoder
Interrupt
Control
RXD_I1
ASC0
Module
(Kernel)
RXD_O
TXD_O
EIR
TBIR
TIR
RIR
ASC0_RDR
To
DMA
Port 3
Control
ASC0_TDR
RXD_I0
RXD_I1
ASC1
Module
(Kernel)
Interrupt
Control
To
DMA
Figure 3-4
P3.9 /
A2 RXD1A
A2
P3.8 /
TXD1A
A2
P3.14 /
RXD1B
A2
P3.15 /
TXD1B
RXD_O
TXD_O
EIR
TBIR
TIR
RIR
ASC1_RDR
ASC1_TDR
MCB06211
Block Diagram of the ASC Interfaces
The ASC provides serial communication between the TC1165/TC1166 and other
microcontrollers, microprocessors, or external peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock that is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
Data Sheet
51
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data is double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal, which can be accurately adjusted
by a prescaler implemented as fractional divider.
Features
•
•
•
•
Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity-bit generation/checking
– One or two stop bits
– Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
Half-duplex 8-bit synchronous operating mode
– Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock)
Double-buffered transmitter/receiver
Interrupt generation
– On a transmit buffer empty condition
– On a transmit last bit of a frame condition
– On a receive buffer full condition
– On an error condition (frame, parity, overrun error)
Data Sheet
52
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.9
Functional Description
High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)
Figure 3-5 shows a global view of the functional blocks and interfaces of the two highspeed Synchronous Serial Interfaces, SSC0 and SSC1.
fSSC0
Clock
Control
Master
fCLC0
Slave
Address
Decoder
Interrupt
Control
Slave
EIR
TIR
RIR
SSC0
Module
(Kernel)
Master
MRSTA
MRSTB
MTSR
A2 P3.4 /MTSR0
MTSRA
MTSRB
MRST
A2 P3.3 /MRST0
SCLKA
SCLKB
SCLK
A2 P3.2 /SCLK0
SLSI1
Slave
SLSI[7:2] 1)
A2 P3.7 /SLSI0
Port 3
Control
SLSO[2:0]
A2 P3.5 /SLSO0
.
.
.
SSC0_RDR
To
DMA
SSC0_TDR
Master
SLSO[5:3]
A2 P3.7 /SLSO2
SLSO6
M/S Select 1)
SLSO7 1)
Enable 1)
A2 P3.8 /SLSO6
A2 P2.1 /SLSO3
SLSO[2:0]
fSSC1
Clock
Control
A2 P2.8 /SLSO4
SLSO[5:3]
fCLC1
A2 P2.9 /SLSO5
Master
SLSO6
1)
SLSO7
Address
Decoder
Interrupt
Control
To
DMA
SLSI1
EIR
TIR
RIR
SSC1_RDR
SSC1
Module
(Kernel)
Slave
SLSI[7:2] 1)
Master
MRSTA
MRSTB
MTSR
Slave
Port 2
Control
A1 P2.13 /SLSI1
A2 P2.12 /MTSR1A
MTSRA
MTSRB
MRST
A2 P2.10 /MRST1A
A2 P2.11 /SCLK1A
SSC1_TDR
A2 P1.10 /SLSO7
M/S Select 1)
Enable 1)
Slave
Master
SCLKA
SCLKB
SCLK
1) These lines are not connected
Figure 3-5
Data Sheet
Port 1
Control
A2 P1.8 /MTSR1B
A2 P1.9 /MRST1B
A2 P1.11 /SCLK1B
MCB06225
Block Diagram of the SSC Interfaces
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Advance Information
Functional Description
The SSC supports full-duplex and half-duplex serial synchronous communication up to
40.0 MBaud (@ 80 MHz module clock). The serial clock signal can be generated by the
SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data
width, shift direction, clock polarity and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is
double-buffered. A shift clock generator provides the SSC with a separate serial clock
signal. Seven slave select inputs are available for Slave Mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Features
•
•
•
•
•
•
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
– Automatic pad control possible
Flexible data format
– Programmable number of data bits: 2 to 16 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
Baud rate generation from 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Flexible SSC pin configuration
Seven slave select inputs SLSI[7:1] in Slave Mode
Eight programmable slave select outputs SLSO[7:0] in Master Mode
– Automatic SLSO generation with programmable timing
– Programmable active level and enable control
Data Sheet
54
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.10
Functional Description
Micro Second Bus Interface (MSC0)
The MSC interface provides a serial communication link typically used to connect power
switches or other peripheral devices. The serial communication link includes a fast
synchronous downstream channel and a slow asynchronous upstream channel.
Figure 3-6 shows a global view of the MSC interface signals.
SR15 (from CAN)
fMSC0
FCLP
fCLC0
Address
Decoder
To DMA
SR[1:0]
MSC0
Module
(Kernel)
SR[3:2]
ALTINL[15:0]
(from GPTA)
ALTINH[15:0]
EMGSTOPMSC
(from SCU)
C SON0
A2 P2.11 / FCLP0B
A2 P2.12 / SOP0B
EN0
SDI[0]1)
1) SDI[7:1] are connected to high level
Figure 3-6
C SOP0A
SON
16
16
C FCLN0
SOP
EN1
Upstream
Channel
Interrupt
Control
C FCLP0A
FCLN
Downstream Channel
Clock
Control
A2 P2.8 / EN00
Port 2
Control
A2 P2.9 / EN01
A1 P2.13 / SDI0
MCA06255
Block Diagram of the MSC Interface
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided at the ALTINL/ALTINH input lines. These input
lines are typically connected to other on-chip peripheral units (for example with a timer
unit like the GPTA). An emergency stop input signal makes it possible to set bits of the
serial data stream to dedicated values in emergency cases.
Data Sheet
55
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Features
•
•
•
Fast synchronous serial interface to connect power switches in particular, or other
peripheral devices via serial buses
High-speed synchronous serial transmission on downstream channel
– Serial output clock frequency: fFCL = fMSC/2
– Fractional clock divider for precise frequency control of serial clock fMSC
– Command, data, and passive frame types
– Start of serial frame: Software-controlled, timer-controlled, or free-running
– Programmable upstream data frame length (16 or 12 bits)
– Transmission with or without SEL bit
– Flexible chip select generation indicates status during serial frame transmission
– Emergency stop without CPU intervention
Low-speed asynchronous serial reception on upstream channel
– Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256
– Standard asynchronous serial frames
– Parity error checker
– 8-to-1 input multiplexer for SDI lines
– Built-in spike filter on SDI lines
Data Sheet
56
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.11
Functional Description
MultiCAN Controller (CAN)
Note: Section 3.11 is not applicable to TC1165.
Figure 3-7 shows a global view of the MultiCAN module with its functional blocks and
interfaces.
fCAN
Clock
Control
MultiCAN Module Kernel
fCLC
Address
Decoder
Message
Object
Buffer
DMA
INT_O
[1:0]
Interrupt
Control
64
Objects
Linked
List
Control
CAN
Node 1
TXDC1
CAN
Node 0
TXDC0
RXDC1
RXDC0
P3.15 /
TXDCAN1
P3.14 /
A2
RXDCAN1
A2
Port 3
Control
P3.13 /
TXDCAN0
P3.12 /
A2
RXDCAN0
A2
INT_O
[5:2]
INT_O15
CAN Control
MCA06281
Figure 3-7
Block Diagram of MultiCAN Module
The MultiCAN module contains two independently-operating CAN nodes with Full-CAN
functionality that are able to exchange Data and Remote Frames via a gateway function.
Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
Both CAN nodes share a common set of message objects. Each message object can be
individually allocated to one of the CAN nodes. Besides serving as a storage container
for incoming and outgoing frames, message objects can be combined to build gateways
between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to the message object list of the CAN node, and it transmits
only messages belonging to this message object list. A powerful, command-driven list
controller performs all message object list operations.
Data Sheet
57
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
The bit timings for the CAN nodes are derived from the module timer clock (fCAN), and
are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected
to a CAN node via a pair of receive and transmit pins.
MultiCAN Features
•
•
•
•
•
•
•
•
•
•
CAN functionality conforms to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
Two independent CAN nodes
64 independent message objects (shared by the CAN nodes)
Dedicated control registers for each CAN node
Data transfer rate up to 1Mbit/s, individually programmable for each node
Flexible and powerful message transfer control and error handling capabilities
Full-CAN functionality: message objects can be individually
– assigned to one of the two CAN nodes
– configured as transmit or receive object
– configured as message buffer with FIFO algorithm
– configured to handle frames with 11-bit or 29-bit identifiers
– provided with programmable acceptance mask register for filtering
– monitored via a frame counter
– configured for Remote Monitoring Mode
Automatic Gateway Mode support
6 individually programmable interrupt nodes
CAN analyzer mode for bus monitoring
Data Sheet
58
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.12
Functional Description
Micro Link Serial Bus Interface (MLI0, MLI1)
The Micro Link Interface is a fast synchronous serial interface that allows data exchange
between microcontrollers of the 32-bit AUDO microcontroller family without intervention
of a CPU or other bus masters. Figure 3-8 shows how two microcontrollers are typically
connected together via their MLI interfaces. The MLI operates in both microcontrollers
as a bus master on the system bus.
Controller 1
Controller 2
CPU
CPU
Peripheral
A
Peripheral
B
Peripheral
C
Peripheral
D
Memory
MLI
MLI
Memory
System Bus
System Bus
MCA06061
Figure 3-8
Typical Micro Link Interface Connection
Features
•
•
•
•
•
•
•
•
•
Synchronous serial communication between MLI transmitters and MLI receivers
located on the same or on different microcontroller devices
Automatic data transfer/request transactions between local/remote controller
Fully transparent read/write access supported (= remote programming)
Complete address range of remote controller available
Specific frame protocol to transfer commands, addresses and data
Error control by parity bit
32-bit, 16-bit, and 8-bit data transfers
Programmable baud rate: max. module clock fMLI/2
Multiple remote (slave) controllers are supported
MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI
transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are
available outside the MLI module kernel as four-line output or input buses.
Figure 3-9 shows a global view of the functional blocks of the two MLI modules with its
interfaces.
Data Sheet
59
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
A2 P2.0 / TCLK0A
TCLK
A2 P2.1 / TREADY0A
Clock
Control
Transmitter
TREADYA
fMLI0
Address
Decoder
Interrupt
Control
To DMA
SR[3:0]
A2 P2.2 / TVALID0A
TREADYB
TREADYD
Port 2
Control
TVALIDA
TVALIDB
TVALIDD
TDATA
A2 P2.3 / TDATA0
A1 P2.4 / RCLK0A
A2 P2.5 / RREADY0A
A1 P2.6 / RVALID0A
MLI0
Module
(Kernel)
RCLKA
A1 P2.7 / RDATA0A
RCLKB
RCLKD
A2 P5.15 / TCLK0B
RREADYA
SR[4:7]
RREADYB
Receiv er
Break
A2 P5.14 / TREADY0B
RREADYD
A2 P5.13 / TVALID0B
RVALIDA
RVALIDB
Port 5
Control
RVALIDD
RDATAA
RDATAB
A2 P5.12 / TDATA0B
A2 P5.11 / RCLK0B
A2 P5.10 / RREADY0B
RDATAD
A2 P5.9 / RVALID0B
A2 P5.8 / RDATA0B
MCB06322
TCLK
Interrupt SR[1:0]
Control
To DMA
Break
TREADYA
A2 P5.11 / TCLK1
TREADYD
A2 P5.10 / TREADY1
TVALIDA
TVALIDD
A2 P5.9 / TVALID1
TDATA
Address
Decoder
N.C.
Transmitter
fMLI1
SR[3:2]
SR[4:7]
A2 P5.8 / TDATA1
RCLKA
MLI1
Module
(Kernel)
Port 5
Control
RCLKD
A2 P5.15 / RCLK1
RREADYA
Receiver
Clock
Control
RREADYD
A2 P5.14 / RREADY1
RVALIDA
A2 P5.13 / RVALID1
RVALIDD
RDATAA
A2 P5.12 / RDATA1
RDATAD
MCB06323
Figure 3-9
Data Sheet
Block Diagram of the MLI Modules
60
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.13
Functional Description
General Purpose Timer Array
The GPTA provides a set of timer, compare, and capture functionalities that can be
flexibly combined to form signal measurement and signal generation units. They are
optimized for tasks typical of electrical motor control applications, but can also be used
to generate simple and complex signal waveforms needed in other industrial
applications.
The TC1165/TC1166 contains one General Purpose Timer Array (GPTA0). Figure 3-10
shows a global view of the GPTA module.
GPTA
Clock Generation Unit
FPC0
FPC1
DCM0
PDL0
DCM1
FPC2
FPC3
FPC4
DCM2
DIGITAL
PLL
PDL1
DCM3
FPC5
Clock
Conn.
GT0
GT1
Clock Bus
fGPTA Clock Distribution Unit
Signal
Generation Unit
GTC00
GTC01
GTC02
GTC03
LTC00
LTC01
LTC02
LTC03
Global
Timer
Cell Array
Local
Timer
Cell Array
GTC30
GTC31
LTC62
LTC63
I/O Line Sharing Unit
Interrupt Sharing Unit
MCB06063
Figure 3-10 Block Diagram of the GPTA Module
Data Sheet
61
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.13.1
Functional Description
Functionality of GPTA0
The General Purpose Timer Array GPTA0 provides a set of hardware modules required
for high-speed digital signal processing:
•
•
•
•
•
•
•
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by various external or internal events.
Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA unit.
Clock Generation Unit
•
•
Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
– Selectable input sources:
Port lines, GPTA module clock, FPC output of preceding FPC cell
– Selectable input clocks:
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock
– fGPTA/2 maximum input signal frequency in Filter Modes
Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3-sensor signals)
– fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input
signal frequency in 3-sensor Mode
Data Sheet
62
V0.2, 2006-02
TC1165/TC1166
Advance Information
•
•
•
Functional Description
Duty Cycle Measurement (DCM)
– Four independent units
– 0 - 100% margin and time-out handling
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Digital Phase Locked Loop (PLL)
– One unit
– Arbitrary multiplication factor between 1 and 65535
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Clock Distribution Unit (CDU)
– One unit
– Provides nine clock output signals:
fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock
Signal Generation Unit
•
•
•
Global Timers (GT)
– Two independent units
– Two operating modes (Free-Running Timer and Reload Timer)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Global Timer Cell (GTC)
– 32 units related to the Global Timers
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Local Timer Cell (LTC)
– 64 independent units
– Three basic operating modes (Timer, Capture and Compare) for 63 units
– Special compare modes for one unit
– 16-bit data width
– fGPTA maximum resolution
– fGPTA/2 maximum input signal frequency
Interrupt Control Unit
•
111 interrupt sources, generating up to 38 service requests
Data Sheet
63
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
I/O Sharing Unit
•
Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and
MSC interface
Data Sheet
64
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.14
Functional Description
Analog-to-Digital Converter (ADC0)
Section 3.14 shows the global view of the ADC module with its functional blocks and
interfaces and the features which are provided by the module.
VDDM
VDD
VAGND0 VSS VSSM VAREF0
Clock
Control
fADC
GPRS
fCLC
EMUX0
A1
Port 1
Control
A1 P1.13 /AD0EMUX1
EMUX1
To DMA
SR[3:0]
SR[7:4]
ADC0
Module
Kernel
AIN0
Group 0
Analog Multiplexer
Interrupt
Control
A1 P1.12 /AD0EMUX0
ASGT
SW0TR, SW0GT External
ETR, EGT
Request
Unit
QTR, QGT
(SCU)
TTR, TGT
Address
Decoder
AIN15
AIN16
Group 1
0
P1.14 /
AD0EMUX2 (GRPS)
AIN30
AIN31
1
8
From Ports
2
From MSC0
6
From GPTA
D
AN0
D
AN15
D
AN16
D
AN30
D
AN31
Die
Temperature
Measurement
SCU_CON.DTSON
MCA06427
Figure 3-11 Block Diagram of the ADC Module
The ADC module has 16 analog input channels. An analog multiplexer selects the input
line for the analog input channels from among 32 analog inputs. Additionally, an external
analog multiplexer can be used for analog input extension. External Clock control,
address decoding, and service request (interrupt) control are managed outside the ADC
module kernel. External trigger conditions are controlled by an External Request Unit.
This unit generates the control signals for auto-scan control (ASGT), software trigger
control (SW0TR, SW0GT), the event trigger control (ETR, EGT), queue control (QTR,
QGT), and timer trigger control (TTR, TGT).
An automatic self-calibration adjusts the ADC module to changing temperatures or
process variations. Figure 3-11 shows the global view of the ADC module with its
functional blocks and interfaces.
Data Sheet
65
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit, 10-bit, 12-bit A/D conversion
Conversion time below 2.5µs @ 10-bit resolution
Extended channel status information on request source
Successive approximation conversion method
Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
Integrated sample & hold functionality
Direct control of up to 16 analog input channels
Dedicated control and status registers for each analog channel
Powerful conversion request sources
Selectable reference voltages for each channel
Programmable sample and conversion timing schemes
Limit checking
Flexible ADC module service request control unit
Automatic control of external analog multiplexers
Equidistant samples initiated by timer
External trigger and gating inputs for conversion requests
Power reduction and clock control feature
On-chip die temperature sensor output voltage measurement
Data Sheet
66
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.15
Functional Description
Fast Analog-to-Digital Converter Unit (FADC)
The on-chip FADC module of the TC1165/TC1166 basically is a 2-channel A/D converter
with 10-bit resolution that operates by the method of the successive approximation.
As shown in Figure 3-12, the main FADC functional blocks are:
•
•
•
•
•
•
The Input Stage — contains the differential inputs and the programmable amplifier
The A/D Converter — is responsible for the analog-to-digital conversion
The Data Reduction Unit — contains programmable antialiasing and data reduction
filters
The Channel Trigger Control block — determines the trigger and gating conditions
for the two FADC channels
The Channel Timers — can independently trigger the conversion of each FADC
channel
The A/D Control block is responsible for the overall FADC functionality
The FADC module is supplied by the following power supply and reference voltage lines:
•
•
•
VDDMF/VDDMF:FADC Analog Part Power Supply (3.3 V)
VDDAF/VDDAF:FADC Analog Part Logic Power Supply (1.5 V)
VFAREF/VFAGND:FADC Reference Voltage (3.3 V)/FADC Reference Ground
Data Sheet
67
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
VFAREF VDDAF VDDMF
VFAGND VSSAF
VSSMF
fFADC
Clock
Control
fCLC
FAIN0P
Address
Decoder
FAIN0N
FAIN1P
Interrupt
Control
SR[1:0]
FAIN1N
FADC
Module
Kernel
SR[3:2]
D AN32
D AN33
D AN34
D AN35
DMA
GPTA0
OUT1
OUT9
OUT18
OUT26
OUT2
OUT10
OUT19
OUT27
A1 P3.10 / REQ0
A1 P3.11 / REQ1
GS[7:0]
TS[7:0]
A1 P0.14 / REQ4
A1 P0.15 / REQ5
PDOUT2
External Request Unit
(SCU)
PDOUT3
MCA06445
Figure 3-12 Block Diagram of the FADC Module
Features
•
•
•
•
•
•
•
•
•
•
•
Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)
10-bit A/D conversion
– Higher resolution by averaging of consecutive conversions is supported
Successive approximation conversion method
Two differential input channels
Offset and gain calibration support for each channel
Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable anti-aliasing and data reduction filter block
Data Sheet
68
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.16
Functional Description
System Timer
The TC1165/TC1166’s STM is designed for global system timing applications requiring
both high precision and long period.
Features
•
•
•
•
•
•
•
•
•
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by maximum 80 MHz (= fSYS, default after reset = fSYS/2)
Counting starts automatically after a reset operation
STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST =
0)
STM can be halted in debug/suspend mode (via STM_CLC register)
The STM is an upward counter, running either at the system clock frequency fSYS or at a
fraction of it. The STM clock frequency is fSTM = fSYS/RMC with RMC = 0-7 (default after
reset is fSTM = fSYS/2, selected by RMC = 010B). RMC is a bit field in register STM_CLC.
In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After
one of these reset conditions, the STM is enabled and immediately starts counting up. It
is not possible to affect the content of the timer during normal operation of the
TC1165/TC1166. The timer registers can only be read but not written to.
The STM can be optionally disabled for power-saving purposes, or suspended for
debugging purposes via its clock control register. In suspend mode of the
TC1165/TC1166 (initiated by writing an appropriate value to STM_CLC register), the
STM clock is stopped but all registers are still readable.
Due to the 56-bit width of the STM, it is not possible to read its entire content with one
instruction. It needs to be read with two load instructions. Since the timer would continue
to count between the two load operations, there is a chance that the two values read are
not consistent (due to possible overflow from the low part of the timer to the high part
between the two read operations). To enable a synchronous and consistent reading
operation of the STM content, a capture register (STM_CAP) is implemented. It latches
the content of the high part of the STM each time when one of the registers STM_TIM0
to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the
same time when the lower part is read. The second read operation would then read the
content of the STM_CAP to get the complete timer value.
Data Sheet
69
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
The STM can also be read in sections from seven registers, STM_TIM0 through
STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can
be viewed as individual 32-bit timers, each with a different resolution and timing range.
The content of the 56-bit System Timer can be compared with the content of two
compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be
generated on a compare match of the STM with the STM_CMP0 or STM_CMP1
registers.
The maximum clock period is 256 × fSTM. At fSTM = 80 MHz, for example, the STM counts
28.56 years before overflowing. Thus, it is capable of timing the entire expected product
life-time of a system without overflowing continuously.
Figure 3-13 shows an overview on the System Timer with the options for reading parts
of the STM contents.
Data Sheet
70
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
STM Module
31
23
STM_CMP0
15
7
0
Compare Register 0
31
23
STM_CMP1
15
7
0
Compare Register1
STMIR1
Interrupt
Control
Clock
Control
55
47
39
31
23
15
7
0
56-Bit System Timer
STMIR0
Enable /
Disable
00H
STM_CAP
fSTM
00H
STM_TIM6
STM_TIM5
Address
Decoder
STM_TIM4
STM_TIM3
PORST
STM_TIM2
STM_TIM1
STM_TIM0
MCB06185
Figure 3-13 General Block Diagram of the STM Module Registers
Data Sheet
71
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.17
Functional Description
Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software
or hardware failure. The WDT helps to abort an accidental malfunction of the
TC1165/TC1166 in a user-specified time period. When enabled, the WDT will cause the
TC1165/TC1166 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1165/TC1166 system reset. Hence, routine service
of the WDT confirms that the system is functioning as expected.
In addition to this standard “Watchdog” function, the WDT incorporates the End-ofInitialization (Endinit) feature and monitors its modifications. A system-wide line is
connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection). Registers protected via this line
can only be modified when Supervisor Mode is active and bit ENDINIT = 0.
A further enhancement in the TC1165/TC1166’s WDT is its reset prewarning operation.
Instead of resetting the device upon the detection of an error immediately (the way that
standard Watchdogs do), the WDT first issues a Non-Maskable Interrupt (NMI) to the
CPU before resetting the device at a specified time period later. This step gives the CPU
a chance to save the system state to the memory for later investigation of the cause of
the malfunction; an important aid in debugging.
Features
•
•
•
•
•
•
•
•
•
•
16-bit Watchdog counter
Selectable input frequency: fSYS/256 or fSYS/16384
16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
Incorporation of the ENDINIT bit and monitoring of its modifications
Sophisticated Password Access mechanism with fixed and user-definable password
fields
Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and is limited.
Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
access to its control register in between, a severe system malfunction is assumed
and the TC1165/TC1166 is held in reset until a power-on or hardware reset occurs.
This prevents the device from being periodically reset if, for instance, connection to
Data Sheet
72
V0.2, 2006-02
TC1165/TC1166
Advance Information
•
Functional Description
the external memory has been lost such that system initialization could not even be
performed.
Important debugging support is provided through the reset prewarning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain
period of time.
3.18
System Control Unit
The System Control Unit (SCU) of the TC1165/TC1166 handles several system control
tasks. The system control tasks of the SCU are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock system selection and control
Reset and boot operation control
Power management control
Configuration input sampling
External Request Unit
System clock output control
On-chip SRAM parity control
Pad driver temperature compensation control
Emergency stop input control for GPTA outputs
GPTA input IN1 control
Pad test mode control for dedicated pins
ODCS level 2 trace control
NMI control
Miscellaneous SCU control
Data Sheet
73
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.19
Functional Description
Boot Options
The TC1165/TC1166 booting schemes provide a number of different boot options for the
start of code execution. Table 3-7 shows the boot options available in the
TC1165/TC1166.
Table 3-7
BRKIN
TC1165/TC1166 Boot Selections
HWCFG
[3:0]
TESTMODE Type of Boot
BootROM
Exit Jump
Address
Normal Boot Options
1
0000B
1
Enter bootstrap loader mode 1:
Serial ASC0 boot via ASC0 pins
D400 0000H
0001B1)
Enter bootstrap loader mode 2:
Serial CAN boot via P3.12 and
P3.13 pins
0010B
Start from internal PFLASH
0011B
Alternate boot mode (ABM): Start Defined in
from internal PFLASH after CRC ABM header
check is correctly executed; enter or D400 0000H
a serial bootstrap loader mode2) if
CRC check fails
1111B
Enter bootstrap loader mode 3:
Serial ASC0 boot via P3.12 and
P3.13 pins
D400 0000H
others
Reserved; execute stop loop
–
A000 0000H
Debug Boot Options
0
0000B
1
Tri-state chip
–
others
irrel.
Reserved; execute stop loop
–
1) This option is not applicable to TC1165.
2) The type of the alternate bootstrap loader mode is selected by the value of the SCU_SCLIR.SWOPT[2:0] bit
field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST.
Data Sheet
74
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.20
Functional Description
Power Management System
The TC1165/TC1166 power management system allows software to configure the
various processing units so that they automatically adjust to draw the minimum
necessary power for the application. There are three power management modes:
•
•
•
Run Mode
Idle Mode
Sleep Mode
The operation of each system component in each of these states can be configured by
software. The power-management modes provide flexible reduction of power
consumption through a combination of techniques, including stopping the CPU clock,
stopping the clocks of other system components individually, and individually clockspeed reduction of some peripheral components.
Besides these explicit software-controlled power-saving modes, special attention has
been paid to automatic power-saving in those operating units which are not required at
a certain point of time, or idle in the TC1165/TC1166. In that case, they are shut off
automatically until their operation is required again.
Table 3-8 describes the features of the power management modes.
Table 3-8
Power Management Mode Summary
Mode
Description
Run
The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle
The CPU clock is disabled, waiting for a condition to return it to Run
Mode. Idle Mode can be entered by software when the processor has no
active tasks to perform. All peripherals remain powered and clocked.
Processor memory is accessible to peripherals. A reset, Watchdog
Timer event, a falling edge on the NMI pin, or any enabled interrupt event
will return the system to Run Mode.
Sleep
The system clock signal is distributed only to those peripherals
programmed to operate in Sleep Mode. The other peripheral module will
be shut down by the suspend signal. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a
reset event will return the system to Run Mode. Entering this state
requires an orderly shut-down controlled by the Power Management
State Machine.
In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently
during the run time of an application. For example, system software will typically cause
the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its
tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any
Data Sheet
75
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
enabled interrupt signal is detected, or when the count value (WDT_SR.WDTTIM)
changes from 7FFFH to 8000H.
3.21
On-Chip Debug Support
Figure 3-14 shows a block diagram of the TC1165/TC1166 OCDS system.
OCDS
L1
OCDS
OCDS
TriCore
L2
L1
SPB
Peripheral
Unit n
TDO
TDI
TMS
TCK
JTAG
Controller
Cerberus
Watchdog
Timer
OSCU
JDI
Debug
I/F
TRST
BRKIN
MCBS
Break
Switch
BRKOUT
DMA
System Peripheral Bus
DMA L2
Multiplexer
16
PCP
Break and Suspend Signals
SPB
Peripheral
Unit 1
Enable, Control and Reset
OCDS
L1
OCDS
L2
OCDS2[15:0]
BCU
MCB06195
Figure 3-14 OCDS System Block Diagram
The TC1165/TC1166 basically supports two levels of debug operation:
•
•
OCDS Level 1 debug support
OCDS Level 2 debug support
Data Sheet
76
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
OCDS Level 1 Debug Support
The OCDS Level 1 debug support is mainly assigned for real-time software debugging
purposes which have a demand for low-cost standard debugger hardware.
The OCDS Level 1 is based on a JTAG interface that is used by the external debug
hardware to communicate with the system. The on-chip Cerberus module controls the
interactions between the JTAG interface and the on-chip modules. The external debug
hardware may become master of the internal buses, and read or write the on-chip
register/memory resources. The Cerberus also makes it possible to define breakpoint
and trigger conditions as well as to control user program execution (run/stop, break,
single-step).
OCDS Level 2 Debug Support
The OCDS Level 2 debug support makes it possible to implement program tracing
capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality
with an additional 16-bit wide trace output port with trace clock. With the trace extension,
the following four trace capabilities are provided (only one of the four trace capabilities
can be selected at a time):
•
•
•
•
Trace of the CPU program flow
Trace of the PCP2 program flow
Trace of the DMA Controller transaction requests
Trace of the DMA Controller Move Engine status information
Data Sheet
77
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.22
Functional Description
Clock Generation and PLL
The TC1165/TC1166 clock system performs the following functions:
•
•
•
•
•
•
Acquires and buffers incoming clock signals to create a master clock frequency
Distributes in-phase synchronized clock signals throughout the TC1165/TC1166’s
entire clock tree
Divides a system master clock frequency into lower frequencies required by the
different modules for operation.
Dynamically reduces power consumption during operation of functional units
Statically reduces power consumption through programmable power-saving modes
Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1165/TC1166 can function, so it
contains special logic to handle power-up and reset operations. Its services are
fundamental to the operation of the entire system, so it contains special fail-safe logic.
Features
•
•
•
•
PLL operation for multiplying clock source by different factors
Direct drive capability for direct clocking
Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
Sleep and Power-Down Mode support
The TC1165/TC1166 Clock Generation Unit (CGU) as shown in Figure 3-15 allows a
very flexible clock generation. It basically consists of an main oscillator circuit and a
Phase- Locked Loop (PLL). The PLL can converts a low-frequency external clock signal
from the oscillator circuit to a high-speed internal clock for maximum performance.
The system clock fSYS is generated from an oscillator clock fOSC in either one of the four
hardware/software selectable ways:
•
•
•
•
Direct Drive Mode (PLL Bypass):
In Direct Drive Mode, the TC1165/TC1166 clock system is directly driven by an
external clock signal. input, i.e. fCPU = fOSC and fSYS = fOSC. This allows operation of
the TC1165/TC1166 with a reasonably small fundamental mode crystal.
VCO Bypass Mode (Prescaler Mode):
In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages,
P-Divider and K-Divider. The system clock fSYS is equal to fCPU.
PLL Mode:
In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by
the P factor, multiplied by the PLL (N-Divider). The clock signals fCPU and fSYS are
derived from fVCO by the K-Divider. The system clock fSYS is equal to fCPU.
PLL Base Mode:
In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS
Data Sheet
78
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
are derived from fVCO only by the K-Divider. In this mode, the system clock fSYS is
equal to fCPU.
XTAL1
Clock Generation Unit (CGU)
Oscillator
Circuit
fOSC
1:1
Divider
1
XTAL2
Osc. Run
Detect.
P
Divider
≥1
Phase
Detect.
fVCO
VCO
0
M
U
X
K:1
Divider
M
U
X
fSYS
fCPU
N
Divider
PLL
Lock
Detector
BYPASS
OGC MOSC OSCR
PDIV OSC
[2:0] DISC
PLL_
LOCK
NDIV VCO_
VCO_
KDIV SYS PLL_
[6:0] SEL[1:0] BYPASS [3:0] FSL BYPASS
Register
OSC_CON
OSC_
BYPASS
Register PLL_CLC
System Control Unit (SCU)
MCA06083
Figure 3-15 Clock Generation Unit
Recommended Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
to 25 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and
depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1
and CX2 values shown in Figure 3-16 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
optimized together with the crystal vendor using the negative resistance method.
Data Sheet
79
V0.2, 2006-02
TC1165/TC1166
Advance Information
Functional Description
Oscillation measurement with the final target system is strongly recommended to verify
the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin
negative resistance) for the oscillator-crystal system.
When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is
left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz
if the PLL is bypassed, and 4 - 40 MHz if the PLL is used.
The oscillator can also be used in combination with a ceramic resonator. The final
circuitry must also be verified by the resonator vendor.
Figure 3-16 shows the recommended external oscillator circuitries for both operating
modes, external crystal mode and external input clock mode. A block capacitor is
recommended to be placed between VDDOSC/VDDOSC3 and VSSOSC.
V DDOSC
VDDOSC3
f OSC
XTAL1
4 - 25
MHz
RQ
CX1
R X2
VDDOSC
External Clock
Signal 4 - 40
MHz
TC1165/TC1166
Oscillator
XTAL2
V DDOSC3
fOSC
XTAL1
TC1165/TC1166
Oscillator
XTAL2
CX2
Fundamental
Mode Crystal
VSSOSC
V SSOSC
Crystal Frequency CX1, CX2 1)
R X2 1)
4 MHz
8 MHz
0
0
0
0
12 MHz
16 - 25 MHz
33
18
12
10
pF
pF
pF
pF
1) Note that these are evaluation start values!
TC1165/TC1166 Oscillator Circuitry
Figure 3-16 Oscillator Circuitries
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
Data Sheet
80
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.23
Functional Description
Power Supply
The TC1165/TC1166 has several power supply lines for different voltage classes:
•
•
1.5 V: Core logic, oscillator and A/D converter supply
3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference
voltages
Figure 3-17 shows the power supply concept of the TC1165/TC1166 with the power
supply pins and its connections to the functional units.
VDDM
VDDAF
VAREF
V DDMF
VFAREF
VSSAF
VSSMF
V FAGND
2
2
(3.3V)
(3.3V)
(1.5V)
V SSM
V AGND
2
2
(3.3V)
(3.3V)
2
TC1165/TC1166
FADC
ADC
V SSA
V DDA
(1.5 V) 1
1
PLL
Core
Flash
Memories
Ports
9
7
8
V SS
V DD
V DDP
V DDFL3
(1.5 V)
(3.3 V)
3.3 V
1
OSC
3
V DDOSC3 (3.3 V)
V DDOSC (1.5 V)
V SSOSC
TC1165/TC1166 PwrSupply
Figure 3-17 Power Supply Concept of TC1165/TC1166
Data Sheet
81
V0.2, 2006-02
TC1165/TC1166
Advance Information
3.24
Functional Description
Identification Register Values
Table 3-9 shows the address map and reset values of the TC1165/TC1166 Identification
Registers.
Table 3-9
TC1165/TC1166 Identification Registers
Short Name
Address
Reset Value
SCU_ ID
F000 0008H
002C C002H
MANID
F000 0070H
0000 1820H
CHIPID
F000 0074H
0000 8B02H
RTID
F000 0078H
0000 0001H
SBCU_ID
F000 0108H
0000 6A0AH
STM_ID
F000 0208H
0000 C006H
CBS_ JDPID
F000 0408H
0000 6307H
MSC0_ ID
F000 0808H
0028 C001H
ASC0_ ID
F000 0A08H
0000 4402H
ASC1_ ID
F000 0B08H
0000 4402H
GPTA0_ ID
F000 1808H
0029 C004H
DMA_ID
F000 3C08H
001A C012H
CAN_ID1)
F000 4008H
002B C012H
SSC0_ ID
F010 0108H
0000 4510H
FADC_ ID
F010 0308H
0027 C012H
ADC0_ID
F010 0408H
0030 C001H
MLI0_ ID
F010 C008H
0025 C006H
MCHK_ ID
F010 C208H
001B C001H
CPS_ID
F7E0 FF08H
0015 C006H
CPU_ID
F7E1 FE18H
000A C005H
PMU_ID
F800 0508H
002E C012H
FLASH_ID
F800 2008H
0041 C002H
DMI_ID
F87F FC08H
0008 C004H
PMI_ID
F87F FD08H
000B C004H
LBCU_ID
F87F FE08H
000F C005H
LFI_ID
F87F FF08H
000C C005H
1) The address and reset value of CAN_ID is not applicable to TC1165.
Data Sheet
82
V0.2, 2006-02
TC1165/TC1166
Advance Information
4
Electrical Parameters
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are
implementation-specific for the TC1165/TC1166.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the
parameters mainly in Section 4.2 and Section 4.3. The absolute maximum ratings and
its operating conditions are provided for the appropriate setting in the TC1165/TC1166.
4.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the
TC1165/TC1166 and partly its requirements on the system. To aid interpreting the
parameters easily when evaluating them for a design, they are marked with an two-letter
abbreviation in column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics which are a distinctive feature of
the TC1165/TC1166 and must be regarded for a system design.
SR
Such parameters indicate System Requirements which must provided by the
microcontroller system in which the TC1165/TC1166 designed in.
Data Sheet
83
V0.2, 2006-02
TC1165/TC1166
Advance Information
4.1.2
Electrical Parameters
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in Section 4.2.1.
Table 4-1
Pad Driver and Pad Classes Overview
Leakage1) Termination
Class Power Type
Supply
Sub Class
Speed Load
Grade
A
A1
(e.g. GPIO)
6 MHz
100 pF 500 nA
A2
(e.g. serial
I/Os)
40
MHz
50 pF
6 µA
Series
termination
recommended
A3
80
(e.g. BRKIN, MHz/
BRKOUT)
50 pF
6 µA
Series
termination
recommended
(for f > 25 MHz)
A4
(e.g. Trace
Clock)
80
MHz
25 pF
6 µA
Series
termination
recommended
–
50
MHz
–
Parallel
termination2),
100Ω ± 10%
3.3V
LVTTL
I/O,
LVTTL
outputs
C
3.3V
LVDS
D
–
Analog inputs, reference voltage inputs
No
1) Values are for TJmax = 125 °C.
2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or
properly terminated with the differential parallel termination of 100Ω ± 10%.
Data Sheet
84
V0.2, 2006-02
TC1165/TC1166
Advance Information
4.1.3
Electrical Parameters
Absolute Maximum Ratings
Table 4-2 shows the absolute maximum ratings of the TC1165/TC1166 parameters.
Table 4-2
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
Min.
TA
Storage temperature
TST
Junction temperature
TJ
Voltage at 1.5 V power supply VDD
pins with respect to VSS1)
Voltage at 3.3 V power supply VDDP
pins with respect to VSS2)
Voltage on any Class A input VIN
Ambient temperature
Unit Notes
Max.
SR -40
85
°C
Under bias
SR -65
150
°C
–
SR -40
125
°C
Under bias
SR –
2.25
V
–
SR –
3.75
V
–
SR -0.5
VDDP + 0.5
V
Whatever is
lower
VDDM + 0.5
V
or max. 3.7
Whatever is
lower
Whatever is
lower
pin and dedicated input pins
with respect to VSS
or
max. 3.7
Voltage on any Class D
analog input pin with respect
to VAGND
VAIN,
VAREFx
SR -0.5
Voltage on any Class D
analog input pin with respect
to VSSAF
VAINF,
VFAREF
SR -0.5
VDDMF + 0.5 V
or max. 3.7
CPU & LMB Bus Frequency
fCPU
fSYS
SR –
803)
MHz –
SR –
803)
MHz
FPI Bus Frequency
4)
1) Applicable for VDD, VDDOSC, VDDPLL, and VDDAF.
2) Applicable for VDDP, VDDFL3, VDDM, and VDDMF.
3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
4) The ratio between fCPU and fSYS is fixed at 1:1.
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > related VDD or
VIN < VSS) the voltage on the related VDD pins with respect to ground (VSS) must
not exceed the values defined by the absolute maximum ratings.
Data Sheet
85
V0.2, 2006-02
TC1165/TC1166
Advance Information
4.1.4
Electrical Parameters
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1165/TC1166. All parameters specified in the following table refer to
these operating conditions, unless otherwise noted.
Table 4-3
Operating Condition Parameters
Parameter
Digital supply voltage1)
Digital ground voltage
Ambient temperature under
bias
Analog supply voltages
Symbol
Limit
Values
Min.
Max.
Unit Notes
Conditions
VDD
VDDOSC
VDDP
VDDOSC3
SR
1.42
1.582) V
–
SR
3.13
3.473) V
For Class A
pins
(3.3V ± 5%)
VDDFL3
VSS
TA
SR
3.13
3.473) V
–
SR
0
V
–
SR
-40
+85
°C
–
–
–
–
See separate
specification
Page 4-92,
Page 4-99
–
fCPU
Short circuit current
ISC
Absolute sum of short circuit Σ|ISC|
SR
–4)
805)
MHz –
SR
-5
+5
mA
6)
SR
–
20
mA
See note7)
Absolute sum of short circuit
currents of the device
Σ|ISC|
SR
–
100
mA
See note 7)
Inactive device pin current
(VDD = VDDP = 0)
IID
SR
-1
1
mA
–
External load capacitance
CL
SR
–
See
pF
DC
chara
cterist
ics
CPU clock
currents of a pin group (see
Table 4-4)
Data Sheet
86
Depending on
pin class
V0.2, 2006-02
TC1165/TC1166
Advance Information
Electrical Parameters
1) Digital supply voltages applied to the TC1165/TC1166 must be static regulated voltages which allow a typical
voltage swing of ±5%.
2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 µs and the cumulated summary of the pulses does not exceed 1 h.
3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than
100 µs and the cumulated summary of the pulses does not exceed 1 h.
4) The TC1165/TC1166 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time
restriction no lower frequency boundary is tested, however.
5) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
6) Applicable for digital outputs.
7) See additional document “TC1796 Pin Reliability in Overload“ for overload current definitions.
Data Sheet
87
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 4-4
Electrical Parameters
Pin Groups for Overload/Short-Circuit Current Sum Parameter
Group
Pins
1
TRCLK, P5.[7:0], P0.[7:6], P0.[15:14]
2
P0.[13:12], P0.[5:4], P2.[13:8], SOP0A, SON0, FCLP0A, FCLN0
3
P0.[11:8], P0.[3:0], P3.[13:11]
4
P3[10:0], P3.[15:14]
5
HDRST, PORST, NMI, TESTMODE, BRKIN, BRKOUT, BYPASS, TCK,
TRST, TDO, TMS, TDI, P1.[7:4]
6
P1.[3:0], P1.[11:8], P4.[3:0]
7
P2.[7:0], P1.[14:12]
8
P5.[15:8]
Data Sheet
88
V0.2, 2006-02
TC1165/TC1166
Advance Information
4.2
Electrical Parameters
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
4.2.1
Input/Output Pins
Table 4-5 provides the characteristics of the input/output pins of the TC1165/TC1166.
Table 4-5
Input/Output DC-Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Unit Test Conditions
Max.
General Parameters
Pull-up current1)
|IPUH|
CC 10
100
µA
VIN < VIHAmin;
class A1/A2/Input pads.
20
200
µA
VIN < VIHAmin;
class A3/A4 pads.
Pull-down
current1)
|IPDL|
CC 10
150
µA
VIN > VILAmax;
class A1/A2/Input pads.
20
200
µA
VIN > VILAmax;
class A3/A4 pads.
Pin capacitance1)
(Digital I/O)
CIO
CC –
10
pF
f = 1 MHz
TA = 25 °C
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%)
-0.3
0.34 ×
V
–
0.64 ×
VDDP
VDDP+
V
Whatever is lower
CC 0.53
–
–
–
VILA3
SR
–
0.8
V
–
Input high voltage VIHA3
class A3 pins
SR
2.0
–
V
–
–
V
2)5)
±3000
nA
((VDDP/2)-1) < VIN
< ((VDDP/2)+1)
otherwise3)
VILA
SR
Input high voltage VIHA
class A1/A2 pins
SR
Ratio VIL/VIH
Input low voltage
class A1/A2 pins
Input low voltage
class A3 pins
Input hysteresis
VDDP
HYSA CC 0.1 ×
0.3 or
max. 3.6
VDDP
Input leakage
current
IOZI
CC –
±6000
Data Sheet
89
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 4-5
Electrical Parameters
Input/Output DC-Characteristics (cont’d)(Operating Conditions
Parameter
Symbol
Limit Values
Min.
Unit Test Conditions
Max.
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V ±5%)
Output low
voltage4)
VOLA
CC –
Output high
voltage3)
VOHA
CC 2.4
0.4
V
IOL = 2 mA for strong driver
mode, (Not applicable to
Class A1 pins)
IOL = 1.8 mA for medium
driver mode, A2 pads
IOL = 1.4 mA for medium
driver mode, A1 pads
IOL = 370 µA for weak
driver mode
–
V
IOH = -2 mA for strong
driver mode, (Not
applicable to Class A1
pins)
IOH = -1.8 mA for medium
driver mode, A1/A2 pads
IOH = -370 µA for weak
driver mode
VDDP -
–
-0.3
0.34 ×
V
–
0.64 ×
VDDP
VDDP +
V
Whatever is lower
V
0.4
IOH = -1.4 mA for strong
driver mode, (Not
applicable to Class A1
pins)
IOH = -1 mA for medium
driver mode, A1/A2 pads
IOH = -280 µA for weak
driver mode
VILA
SR
Input high voltage VIHA
class A1/2 pins
SR
Ratio VIL/VIH
CC 0.53
–
–
–
HYSA CC 0.1 ×
–
V
2)5)
Input low voltage
class A1/2 pins
Input hysteresis
VDDP
0.3 or
3.6
VDDP
Data Sheet
90
V0.2, 2006-02
TC1165/TC1166
Advance Information
Table 4-5
Electrical Parameters
Input/Output DC-Characteristics (cont’d)(Operating Conditions
Parameter
Symbol
Limit Values
Min.
Input leakage
current Class
A2/3/4 pins
IOZA24 CC –
Input leakage
current
Class A1 pins
IOZA1
Unit Test Conditions
Max.
±3000
nA
((VDDP/2)-1) < VIN
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