Please note that GaN Systems is an Infineon Technologies Company
The document following this cover page is marked as “GaN Systems”
document as this is the company that originally developed the product.
Please note that Infineon will continue to offer the product to new and
existing customers as part of the Infineon product portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon
product portfolio does not lead to any changes to this document. Future
revisions will occur when appropriate, and any changes will be set out on the
document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use
the ordering part numbers listed in the datasheet for ordering.
Infineon Technologies AG
81726 Munich, Germany
www.infineon.com
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100 V enhancement mode power transistor
Top-side cooled configuration
RDS(on) = 7 mΩ
IDS(max) = 90 A
Ultra-low FOM die
Low inductance GaNPX® package
Simple gate drive requirements (0 V to 6 V)
Transient tolerant gate drive (-20 V / +10 V)
Very high switching frequency (> 10 MHz)
Fast and controllable fall and rise times
Reverse current capability
Zero reverse recovery loss
Small 7.0 x 4.0 mm2 PCB footprint
Dual gate pads for optimal board layout
RoHS 3 (6 + 4) compliant
Applications
•
•
•
•
•
•
•
•
•
Energy Storage Systems
AC-DC Converters (secondary side)
Uninterruptable Power Supplies
Industrial Motor Drives
Fast Battery Charging
Class D Audio amplifiers
Traction Drive
Robotics
Wireless Power Transfer
Package Outline
Circuit Symbol
The top-side thermal pad is internally
connected to Source (S pin 3) and
substrate
Description
The GS61008T is an enhancement mode GaN-onsilicon power transistor. The properties of GaN
allow for high current, high voltage breakdown and
high switching frequency. GaN Systems innovates
with industry leading advancements such as
patented
Island
Technology®
and
GaNPX®
packaging. Island Technology® cell layout realizes
high-current die and high yield. GaNPX® packaging
enables low inductance & low thermal resistance in
a small package. The GS61008T is a top-side cooled
transistor that offers very low junction-to-case
thermal resistance for demanding high power
applications. These features combine to provide
very high efficiency power switching.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
1
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Absolute Maximum Ratings (Tcase = 25 °C except as noted)
Parameter
Symbol
Value
Unit
Operating Junction Temperature
TJ
-55 to +150
°C
Storage Temperature Range
TS
-55 to +150
°C
Drain-to-Source Voltage
VDS
100
V
VDS(transient)
120
V
VGS
-10 to +7
V
VGS(transient)
-20 to +10
V
Continuous Drain Current (Tcase = 25 °C)
IDS
90
A
Continuous Drain Current (Tcase = 100 °C)
IDS
65
A
IDS Pulse
140
A
Drain-to-Source Voltage - transient (Note 1)
Gate-to-Source Voltage
Gate-to-Source Voltage - transient (Note 1)
Pulse Drain Current (Pulse width 50 µs, VGS = 6 V)
(Note 2)
(1) For < 1 µs
(2) Defined by product design and characterization. Value is not tested to full current in production.
Thermal Characteristics (Typical values unless otherwise noted)
Parameter
Symbol
Value
Units
Thermal Resistance (junction-to-case) – Top side
RΘJC
0.55
°C /W
Maximum Soldering Temperature (MSL3 rated)
TSOLD
260
°C
Ordering Information
Ordering
code
Package type
Packing
method
Qty
Reel
Diameter
Reel
Width
GS61008T-TR
GaNPX® Top-Side Cooled
Tape-and-Reel
3000
13” (330
mm)
16 mm
GS61008T-MR
GaNPX® Top-Side Cooled
Mini-Reel
250
7” (178 mm)
16 mm
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
2
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Electrical Characteristics (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise noted)
Parameters
Sym.
Min.
Drain-to-Source Blocking
Voltage
V(BL)DSS
100
Drain-to-Source On Resistance
RDS(on)
7
Drain-to-Source On Resistance
RDS(on)
17.5
Gate-to-Source Threshold
VGS(th)
Gate-to-Source Current
1.1
Typ.
1.7
Max.
9.5
2.6
Units
Conditions
V
VGS = 0 V
IDSS = 50 µA
mΩ
VGS = 6 V, TJ = 25 °C
IDS = 27 A
mΩ
VGS = 6 V, TJ = 150 °C
IDS = 27 A
V
VDS = VGS, IDS = 7 mA
VGS = 6 V, VDS = 0 V
IGS
200
µA
Gate Plateau Voltage
Vplat
3.5
V
Drain-to-Source Leakage
Current
IDSS
0.5
Drain-to-Source Leakage
Current
IDSS
100
µA
Internal Gate Resistance
RG
0.6
Ω
Input Capacitance
CISS
600
pF
Output Capacitance
COSS
250
pF
Reverse Transfer Capacitance
CRSS
12
pF
Effective Output Capacitance,
Energy Related (Note 3)
CO(ER)
302
pF
Effective Output Capacitance,
Time Related (Note 4)
CO(TR)
385
pF
Total Gate Charge
QG
8
nC
Gate-to-Source Charge
QGS
3.5
nC
Gate threshold charge
QG(th)
1.9
nC
Gate switching charge
QG(sw)
3.3
nC
Gate-to-Drain Charge
QGD
1.7
nC
Output Charge
QOSS
20
nC
Reverse Recovery Charge
QRR
0
nC
50
µA
VDS = 50 V
IDS = 90 A
VDS = 100 V, VGS = 0
V
TJ = 25 °C
VDS = 100 V, VGS = 0
V
TJ = 150 °C
f = 5 MHz open drain
VDS = 50 V
VGS = 0 V
f = 100 kHz
VGS = 0 V
VDS = 0 to 50 V
VGS = 0 to 6 V
VDS = 50 V
IDS = 90 A
VGS = 0 V, VDS = 50 V
(3) CO(ER) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0 V to the stated
VDS
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
3
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
(4) CO(TR) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0 V to the stated
VDS.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
4
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Electrical Characteristics cont’d (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise
noted)
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
VDS = 50 V
VGS = 0 V
f = 100 kHz
Output Capacitance Stored
Energy
EOSS
0.4
µJ
Switching Energy during turn-on
Eon
2.8
µJ
Switching Energy during turn-off
Eoff
1.6
µJ
VDS = 50 V, IDS = 20 A
VGS = -3 - 6 V,
RG(on) = 4.7 Ω, RG(off) = 1 Ω
L = 28 µH
LP = 3.8 nH (Notes 5, 6)
(5) LP is the switching circuit parasitic inductance.
(6) See Figure 16 for switching loss test circuit.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
5
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Electrical Performance Graphs
IDS vs. VDS Characteristic
IDS vs. VDS Characteristic
Figure 1: Typical IDS vs. VDS @ TJ = 25 ⁰C
Figure 2: Typical IDS vs. VDS @ TJ = 150 ⁰C
RDS(on) vs. IDS Characteristic
RDS(on) vs. IDS Characteristic
Figure 3: RDS(on) vs. IDS at TJ = 25 ⁰C
Figure 4: RDS(on) vs. IDS at TJ = 150⁰C
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
6
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Electrical Performance Graphs
IDS vs. VDS, TJ dependence
Gate Charge, QG Characteristic
Figure 5: Typical IDS vs. VDS @ VGS = 6 V
Figure 6: Typical VGS vs. QG @ VDS = 50V
Capacitance Characteristics
Stored Energy Characteristic
Figure 7: Typical CISS, COSS, CRSS vs. VDS
Figure 8: Typical COSS Stored Energy
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
7
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Electrical Performance Graphs
Reverse Conduction Characteristics
Reverse Conduction Characteristics
Figure 9: Typical ISD vs. VSD at TJ = 25 ⁰C
Figure 10: Typical ISD vs. VSD at TJ = 150⁰C
IDS vs. VGS Characteristic
RDS(on) Temperature Dependence
Figure 11: Typical IDS vs. VGS
Figure 12: Normalized RDS(on) as a function of
TJ
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
8
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Thermal Performance Graphs
IDS - VDS SOA
Power Dissipation – Temperature Derating
Figure 13: Safe Operating Area @ Tcase = 25
C
Figure 14: Derating vs. Case Temperature
Transient RθJC
Figure 15: Transient Thermal Impedance
1.00 = Nominal DC thermal impedance
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
9
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
10
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Test Circuits
Figure 16: Switching Loss Test Circuit
Application Information
Gate Drive
The recommended gate drive voltage range, VGS, is 0 V to + 6 V for optimal RDS(on) performance. Also, the
repetitive gate to source voltage, maximum rating, VGS(AC), is +7 V to -10 V. The gate can survive nonrepetitive transients up to +10 V and – 20 V for pulses up to 1 µs. These specifications allow designers to
easily use 6.0 V or 6.5 V gate drive settings. At 6 V gate drive voltage, the enhancement mode high
electron mobility transistor (E-HEMT) is fully enhanced and reaches its optimal efficiency point. A 5 V
gate drive can be used but may result in lower operating efficiency. Inherently, GaN Systems E-HEMT do
not require negative gate bias to turn off. Negative gate bias, typically V GS = -3 V, ensures safe operation
against the voltage spike on the gate, however it may increase reverse conduction losses if not driven
properly. For more details, please refer to the gate driver application note "GN001 How to Drive GaN
Enhancement Mode Power Switching Transistors” at www.gansystems.com
Similar to a silicon MOSFET, the external gate resistor can be used to control the switching speed and
slew rate. Adjusting the resistor to achieve the desired slew rate may be needed. Lower turn-off gate
resistance, RG(OFF) is recommended for better immunity to cross conduction. Please see the gate driver
application note (GN001) for more details.
A standard MOSFET driver can be used as long as it supports 6V for gate drive and the UVLO is suitable
for 6V operation. Gate drivers with low impedance and high peak current are recommended for fast
switching speed. GaN Systems E-HEMTs have significantly lower QG when compared to equally sized
RDS(on) MOSFETs, so high speed can be reached with smaller and lower cost gate drivers.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
11
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Many non-isolated half bridge MOSFET drivers are not compatible with 6 V gate drive for GaN
enhancement mode HEMT due to their high under-voltage lockout threshold. Also, a simple bootstrap
method for high side gate drive will not be able to provide tight tolerance on the gate voltage. Therefore,
special care should be taken when you select and use the half bridge drivers. Alternatively, isolated drivers
can be used for a high side device. Please see the gate driver application note (GN001) for more details.
Parallel Operation
Design wide tracks or polygons on the PCB to distribute the gate drive signals to multiple devices. Keep
the drive loop length to each device as short and equal length as possible.
The dual gate drive pins are used to achieve balanced gate drive, especially useful in parallel GaN
transistors operation. Both gate drive pins are internally connected to the gate, so only one needs to be
connected. Connecting both may lead to timing improvements at very high frequencies. The two gates on
the top-side cooled device are not designed to be used as a signal pass-through. When multiple devices
are used in parallel, it is not recommended to use one gate connection to the other (on the same
transistor) as a signal path for the gate drive to the next device. Design wide tracks or polygons on the
PCB to distribute the gate drive signals to multiple devices. Keep the drive loop length to each device as
short and equal length as possible.
GaN enhancement mode HEMTs have a positive temperature coefficient on-state resistance which helps
to balance the current. However, special care should be taken in the driver circuit and PCB layout since
the device switches at very fast speed. It is recommended to have a symmetric PCB layout and equal gate
drive loop length (star connection if possible) on all parallel devices to ensure balanced dynamic current
sharing. Adding a small gate resistor (1-2 Ω) on each gate is strongly recommended to minimize the gate
parasitic oscillation.
Source Sensing
Although the device does not have a dedicated source sense pin, the GaNPX® packaging utilizes no wire
bonds so the source connection is already very low inductance. By simply using a dedicated “source
sense” connection on the PCB to the Source pad in a kelvin configuration, the function can easily be
implemented. It is recommended to implement a “source sense” connection to improve drive
performance.
Thermal
The substrate is internally connected to the thermal pad on the top-side and to the source pin on the
bottom side of the package. The transistor is designed to be cooled using a heat sink on the top of the
device.
The Drain and Source pads are not as thermally conductive as a thermal pad. However, adding more
copper under these two pads will improve thermal performance by reducing the packaging temperature.
Thermal Modeling
RC thermal models are available to support detailed thermal simulation using SPICE. The thermal models
are created using the Cauer model, an RC network model that reflects the real physical property and
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
12
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
packaging structure of our devices. This thermal model can be extended to the system level by adding
extra Rθ and Cθ to simulate the Thermal Interface Material (TIM) or Heatsink.
RC Thermal Model:
RC breakdown of RΘJC
Rθ (°C/W)
Cθ (W∙s/°C)
Rθ1 = 0.017
Cθ1 = 7.0E-05
Rθ2 = 0.253
Cθ2 = 6.7E-04
Rθ3 = 0.264
Cθ3 = 5.9E-03
Rθ4 = 0.016
Cθ4 = 1.8E-03
For more detail, please refer to Application Note GN007 “Modeling Thermal Behavior of GaN Systems’
GaNPX® Using RC Thermal SPICE Models” available at www.gansystems.com.
Reverse Conduction
GaN Systems enhancement mode HEMTs do not have an intrinsic body diode and there is zero reverse
recovery charge. The devices are naturally capable of reverse conduction and exhibit different
characteristics depending on the gate voltage. Anti-parallel diodes are not required for GaN Systems
transistors as is the case for IGBTs to achieve reverse conduction performance.
On-state condition (VGS = +6 V): The reverse conduction characteristics of a GaN Systems enhancement
mode HEMT in the on-state is similar to that of a silicon MOSFET, with the I-V curve symmetrical about
the origin and it exhibits a channel resistance, RDS(on), similar to forward conduction operation.
Off-state condition (VGS ≤ 0 V): The reverse characteristics in the off-state are different from silicon
MOSFET as the GaN device has no body diode. In the reverse direction, the device starts to conduct when
the gate voltage, with respect to the drain, (VGD) exceeds the gate threshold voltage. At this point the
device exhibits a channel resistance. This condition can be modeled as a “body diode” with slightly higher
VF and no reverse recovery charge.
If negative gate voltage is used in the off-state, the source-drain voltage must be higher than VGS(th) +
VGS(off) in order to turn the device on. Therefore, a negative gate voltage will add to the reverse voltage
drop “VF” and hence increase the reverse conduction loss.
Blocking Voltage
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
13
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
The blocking voltage rating, V(BL)DSS, is defined by the drain leakage current. The hard (unrecoverable)
breakdown voltage is approximately 30 % higher than the rated V(BL)DSS. As a general practice, the
maximum drain voltage should be de-rated in a similar manner as IGBTs or silicon MOSFETs. All GaN EHEMTs do not avalanche and thus do not have an avalanche breakdown rating. The maximum drain-tosource rating is 100 V and does not change with negative gate voltage. GaN Systems tests devices in
production with a 120V Drain-to-source voltage pulse to insure blocking voltage margin.
Packaging and Soldering
The package material is high temperature epoxy-based PCB material which is similar to FR4 but has a
higher temperature rating, thus allowing the device to be specified to 150 °C. The device can handle at
least 3 reflow cycles.
It is recommended to use the reflow profile in IPC/JEDEC J-STD-020 REV D.1 (March 2008)
The basic temperature profiles for Pb-free (Sn-Ag-Cu) assembly are:
•
Preheat/Soak: 60 - 120 seconds. Tmin = 150 °C, Tmax = 200 °C.
•
Reflow: Ramp up rate 3°C/s maximum. Peak temperature is 260 °C and time within 5 °C of peak
temperature is 30 seconds.
•
Cool down: Ramp down rate 6 °C/s maximum.
Using “No-Clean” soldering paste and operating at high temperatures may cause a reactivation of the
“No-Clean” flux residues. In extreme conditions, unwanted conduction paths may be created. Therefore,
when the product operates at greater than 100 C it is recommended to also clean the “No-Clean” paste
residues.
Avoid placing printed circuit board traces with high differential voltage to the source or drain directly
underneath the top-cooled GS66508T package on the PCB to avoid potential electro-migration and
solder mask isolation issues during high temperature or/and voltage operation
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
14
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Routing Guidelines
The following layout recommendations are highlighted. Additional detail is provided in Application
Note GN001 at www.gansystems.com.
Keep out area: Avoid placing traces or vias on the top layer of the PCB, directly
underneath the package. This is to prevent potential electro-migration and solder mask
isolation issues during high temperature or/and voltage operation.
Symmetrical dual gates are provided for flexible layout and easy paralleling. Either gate
drive can be used. If the second gate is not used, it should be left floating.
A separate Source Sense pin is not provided on our top-side products because of the
ultra-low inductance of our GaNPX® packaging. The Source Sense pin functionality can be
implemented simply by routing a Kelvin connection at the side of the Source pad. This
can be done at either side of the source pad for layout optimization.
Do not route vias within the Gate pad as it may affect long term solder joint reliability. For
other pads, it is recommended to implement filled vias for better solder joint reliability.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
15
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Recommended PCB Footprint
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
16
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Package Dimensions
Part Marking
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
17
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Tape and Reel Information
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
18
GS61008T
Top-side cooled 100 V E-mode GaN transistor
Datasheet
Tape and Reel Box Dimensions
www.gansystems.com
Important Notice – Unless expressly approved in writing by an authorized representative of GaN Systems, GaN Systems
components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or space applications, nor in
products or systems where failure or malfunction may result in personal injury, death, or property or environmental damage. The
information given in this document shall not in any event be regarded as a guarantee of performance. GaN Systems hereby disclaims any
or all warranties and liabilities of any kind, including but not limited to warranties of non-infringement of intellectual property rights. All
other brand and product names are trademarks or registered trademarks of their respective owners. Information provided herein is
intended as a guide only and is subject to change without notice. The information contained herein or any use of such information does not
grant, explicitly, or implicitly, to any party any patent rights, licenses, or any other intellectual property rights. GaN Systems standard
terms and conditions apply. All rights reserved.
Rev 200402
© 2009-2020 GaN Systems Inc.
Submit Datasheet Feedback
19
