IAUC100N10S5N040

IAUC100N10S5N040 OptiMOSTM-5 Power-Transistor Product Summary 100 VDS V 4 RDS(on) m 100 ID A Features • N-channel - Enhancement mode - Normal level PG-TDSON-8 • AEC qualified • MSL1 up to 260°C peak reflow • 100% Avalanche tested • Feasible for automatic optical inspection (AOI) 1 Type Package Marking IAUC100N10S5N040 PG-TDSON-8 5N1N040 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions Value T C=25°C, V GS=10V 100 T C=100°C, V GS=10V 100 Unit A Pulsed drain current2) I D,pulse T C=25°C 400 Avalanche energy, single pulse E AS I D=50A 234 mJ Avalanche current, single pulse I AS - 100 A Gate source voltage V GS - ±20 V Power dissipation P tot T C=25°C, T J =175°C 167 W Operating and storage temperature T j, T stg - -55 ... +175 °C Rev. 1.0 page 1 2018-06-12 IAUC100N10S5N040 Parameter Symbol Values Conditions Unit min. typ. max. - - 0.9 100 - - Thermal characteristics Thermal resistance, junction - case R thJC - K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0V, I D= 1mA Gate threshold voltage V GS(th) V DS=V GS, I D= 90µA 2.2 3.0 3.8 Zero gate voltage drain current I DSS V DS=100V, V GS=0V, T j=25 °C - 0.1 1 - 10 100 - - 100 nA m V DS=100V, V GS=0V, T j=125°C2) Gate-source leakage current I GSS V GS=20V, V DS=0V Drain-source on-state resistance R DS(on) V GS=6V, I D=25A - 4.2 5.6 V GS=10 V, I D=50 A - 3.4 4 - 1.3 - Gate resistance2) Rev. 1.0 RG page 2 V µA  2018-06-12 IAUC100N10S5N040 Parameter Symbol Values Conditions Unit min. typ. max. - 4000 5200 - 660 860 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 28 42 Turn-on delay time t d(on) - 10 - Rise time tr - 5 - Turn-off delay time t d(off) - 19 - Fall time tf - 14 - Gate to source charge Q gs - 20 26 Gate to drain charge Q gd - 13 20 Gate charge total Qg - 60 78 Gate plateau voltage V plateau - 4.6 - V - - 100 A - - 400 - 0.9 1.1 V - 54 - ns - 90 - nC V GS=0 V, V DS=50V, f =1MHz V DD=50V, V GS=10V, I D=100A, R G=3.5 pF ns Gate Charge Characteristics2) V DD=50V, I D=50A, V GS=0 to 10V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25°C V GS=0V, I F=50A, T j=25°C V R=50V, I F=50A, di F/dt =100A/µs 1) Current is limited by package; with an R thJC =0.9K/W the chip is able to carry 140A at 25°C. 2) Defined by design. Not subject to production test. Rev. 1.0 page 3 2018-06-12 IAUC100N10S5N040 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 175 120 150 100 125 100 ID [A] Ptot [W] 80 60 75 40 50 20 25 0 0 0 50 100 150 200 0 50 100 TC [°C] 150 200 TC [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 100 0.5 1 µs 10 µs 0.1 100 µs 100 10-1 ZthJC [K/W] ID [A] 1 ms 10 0.01 10-2 1 single pulse 10-3 0.1 1 10 100 VDS [V] Rev. 1.0 0.05 10-6 10-5 10-4 10-3 10-2 10-1 100 tp [s] page 4 2018-06-12 IAUC100N10S5N040 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = (I D); T j = 25 °C parameter: V GS parameter: V GS 10 400 5.5 V 7V 10 V 6.5 V 9 6V 8 200 RDS(on) [m] ID [A] 300 5.5 V 7 6V 6 5 100 6.5 V 7V 4 10 V 3 0 0 1 2 3 4 0 5 100 200 300 400 ID [A] VDS [V] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6V R DS(on) = f(T j);I D = 50 A; V GS = 10 V I D = 25 A; V GS = 6 V parameter: T j 400 7 25 °C 350 6.5 175 °C -55 °C 6V 6 300 5.5 RDS(on) [m] ID [A] 250 200 150 10V 5 4.5 4 3.5 100 3 50 2.5 2 0 3 4 5 6 7 -20 20 60 100 140 180 Tj [°C] VGS [V] Rev. 1.0 -60 page 5 2018-06-12 IAUC100N10S5N040 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 4 Ciss 3.5 900 µA 103 90 µA C [pF] VGS(th) [V] 3 2.5 Coss 102 2 1.5 Crss 101 1 -60 -20 20 60 100 140 0 180 25 50 75 VDS [V] Tj [°C] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I AS = f(t AV) parameter: T j parameter: Tj(start) 1000 1000 100 100 175 °C 25 °C IF [A] IAV [A] 25 °C 10 100 °C 150 °C 10 1 1 0.4 0.6 0.8 1 1.2 VSD [V] Rev. 1.0 100 1 10 100 1000 tAV [µs] page 6 2018-06-12 IAUC100N10S5N040 13 Typical avalanche energy 14 Drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 112 500 450 25 A 108 400 350 VBR(DSS) [V] EAS [mJ] 300 250 50 A 200 104 100 150 100 A 96 100 50 92 0 25 75 125 -60 175 -20 20 Tj [°C] 60 100 140 180 Tj [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 10 V GS 9 20 V 80 V 8 Qg 50 V 7 VGS [V] 6 5 4 3 2 Q gate 1 Q gs Q gd 0 0 20 40 60 Qgate [nC] Rev. 1.0 page 7 2018-06-12 IAUC100N10S5N040 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2018 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 8 2018-06-12 IAUC100N10S5N040 Revision History Version Date Changes Revision 1.0 2018-06-12 Final Data Sheet Rev. 1.0 page 9 2018-06-12