ICE3A1065LJHKLA1

V er s io n 2 . 3 , 3 0 J u n 2 0 1 1 I CE 3A1 065 LJ O ff - L in e S M P S Cu r r e n t M o d e C o n tr o lle r wit h in t e g r a te d 6 5 0 V S t a r tu p C e ll/ De p l e tio n C o o lM O S ™ ( L a tc h e d a n d f r e q u e n c y j itt e r Mode ) Po we r M an a ge me nt & Su pp l y N e v e r s t o p t h i n k i n g . CoolSET™-F3 ICE3A1065LJ Revision History: 2011-06-30 Datasheet Previous Version: 2.2 Page Subjects (major changes since last revision) 22 revised outline dimension for PG-DIP-8 package For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS™, CoolSET™ are trademarks of Infineon Technologies AG. Edition 2011-06-30 Published by Infineon Technologies AG, 81726 Munich, Germany, © 2007 Infineon Technologies AG. All Rights Reserved. Legal disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CoolSET™-F3 ICE3A1065LJ Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™ ( Latched and frequency jitter Mode ) Product Highlights • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW • Built-in latched Off Mode and external latch enable function to increase robustness of the system • Built-in and extendable blanking Window for high load jumps to increase system reliability • Built-in soft start • Frequency jitter for low EMI • Pb-free lead plating; RoHS compilant PG-DIP-8 Features Description • The CoolSET™-F3 meets the requirements for Off-Line Battery Adapters and low cost SMPS for the lower power range. Adopting the BiCMOS technology, the IC can provide a wider VCC range up to 26V. Furthermore the Active Burst Mode is integrated to achieve the lowest Standby Power Requirements 24V and the FB is > 4.5V, the overvoltage detection is activated. That means the overvoltage detection is only activated if the FB signal is outside the operating range > 4.5V, e.g. when Open Loop happens. The logic can eliminate the possible of entering Latch off mode if there is a small voltage overshoots of VVCC during normal operating. The internal Voltage Reference is switched off most of the time once Latched Off Mode is entered in order to minimize the current consumption of the IC. This Latched Off Mode can only be reset if the VVCC < 6.23V. In this mode, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 250mA. As there is no longer a self-supply by the auxiliary winding, the VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 10.5V. The Startup Cell is switched off again when VCC has exceeded 18V. Once the Latched Off Mode was entered, there is no Start Up Phase whenever the VCC exceeds the switch-on level of the Undervoltage Lockout. Therefore the VCC voltage changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 19). Furthermore, a short winding or short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal operating mode, comparator C10 controls the maximum level of the CS signal at 1.06V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1.06V. Instead the comparator C11 detects the peak current voltage > 1.66V and enters the Latched Off Mode immediately in order to keep the SMPS in a safe stage. In case the pre-defined Latch Off features are not sufficient, there is a customer defined external Latch Enable feature. The Latch Off Mode can be triggered by pulling down the BL pin to < 0.1V. It can simply add a trigger signal to the base of the externally added transistor, TLE at the BL pin. To ensure this latch function will not be mis-triggered during start up, a 1ms delay time is implemented to blank the unstable signal. 3.6.3.2 Auto Restart Mode BL # CBK 5.0V IBK VVCC 0.9V 1 S1 G2 18V C3 10.5V Spike Blanking 8.0us 4.0V IVCCStart t & 4.5V 0.9mA FB C4 20ms Blanking Time G5 Auto Restart Mode Control Unit Figure 20 VOUT Figure 19 t In case of Overload or Open Loop, the FB exceeds 4.5V which will be observed by comparator C4. Then the internal blanking counter starts to count. When it reaches 20ms, the switch S1 is released. Then the clamped voltage 0.9V at VBL can increase. When there is no external capacitor CBK connected, the VBL will reach 4.0V immediately. When both the input signals at AND gate G5 is positive, the Auto-Restart Mode will be activated after the extra spike blanking time of 8.0us is elapsed. However, when an extra blanking time is needed, it can be achieved by adding an external capacitor, CBK. A constant current source of IBK will start Signals in Latched Off Mode The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than latched thermal shutdown temperature; TjSD, the Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0ms in order to ensure the system reliability. Version 2.3 Auto Restart Mode 14 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Functional Description to charge the capacitor CBK from 0.9V to 4.0V after the switch S1 is released. The charging time from 0.9V to 4.0V are the extendable blanking time. If CBK is 0.22uF and IBK is 8.4uA, the extendable blanking time is around 80ms and the total blanking time is 100ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode. Version 2.3 15 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Parameter Symbol Limit Values min. max. Unit Remarks Tj=110°C Drain Source Voltage VDS - 650 V Pulse drain current, tp limited by max. Tj=150°C ID_Puls - 3.4 A Avalanche energy, repetitive tAR limited EAR by max. Tj=150°C1) - 0.07 mJ Avalanche current, repetitive tAR limited IAR by max. Tj=150°C - 1.0 A VCC Supply Voltage VVCC -0.3 27 V FB Voltage VFB -0.3 5.0 V CS Voltage VCS -0.3 5.0 V Junction Temperature Tj -40 150 °C Storage Temperature TS -55 150 °C Thermal Resistance Junction -Ambient RthJA1 - 90 K/W PG-DIP-8 ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2) Controller & CoolMOSTM 1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f 2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor) 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values min. max. Unit VCC Supply Voltage VVCC VVCCoff 26 V Junction Temperature of Controller TjCon -25 130 °C Junction Temperature of CoolMOS™ TjCoolMOS -25 150 °C Version 2.3 16 Remarks Max value limited due to thermal shut down of controller 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Electrical Characteristics 4.3 4.3.1 Note: Characteristics Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from – 25 °C to 130 °C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Start Up Current IVCCstart - 150 250 mA VVCC =17V VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V IVCCcharge2 0.55 0.90 1.60 mA VVCC = 1V IVCCcharge3 - 0.7 - mA VVCC =17V Leakage Current of Start Up Cell and CoolMOS™ IStartLeak - 0.2 50 mA VDrain = 450V at Tj=100°C Supply Current with Inactive Gate IVCCsup1 - 1.5 2.5 mA Supply Current with Active Gate IVCCsup2 - 2.5 4.2 mA IFB = 0A Supply Current in Latched Off Mode IVCClatch - 250 - mA IFB = 0A Supply Current in Auto Restart Mode with Inactive Gate IVCCrestart - 250 - mA IFB = 0A Supply Current in Active Burst Mode with Inactive Gate IVCCburst1 - 450 950 mA VFB = 2.5V IVCCburst2 - 450 950 mA VVCC = 11.5V,VFB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis VVCCon VVCCoff VVCChys 17.0 9.8 - 18.0 10.5 7.5 19.0 11.2 - V V V 4.3.2 Internal Voltage Reference Parameter Trimmed Reference Voltage Version 2.3 Symbol VREF Limit Values min. typ. max. 4.90 5.00 5.10 17 Unit Test Condition V measured at pin FB IFB = 0 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Electrical Characteristics 4.3.3 PWM Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. fOSC1 87 100 113 kHz fOSC2 92 100 108 kHz Tj = 25°C Frequency Jittering Range fjitter - ±4.0 - kHz Tj = 25°C Max. Duty Cycle Dmax 0.70 0.75 0.80 Min. Duty Cycle Dmin 0 - - PWM-OP Gain AV 3.0 3.2 3.4 Voltage Ramp Offset VOffset-Ramp - 0.6 - V VFB Operating Range Min Level VFBmin - 0.5 - V VFB Operating Range Max level VFBmax - - 4.3 V FB Pull-Up Resistor RFB 9 15.4 22 kW Fixed Oscillator Frequency 1) VFB < 0.3V CS=1V, limited by Comparator C41) The parameter is not subjected to production test - verified by design/characterization 4.3.4 Soft Start time Parameter Soft Start time 4.3.5 Symbol tSS Limit Values min. typ. max. - 20.0 - Unit Test Condition ms Control Unit Parameter Symbol Limit Values min. typ. max. Unit Test Condition VFB = 4V Clamped VBL voltage during Normal Operating Mode VBLclmp 0.85 0.90 0.95 V Blanking time voltage limit for Comparator C3 VBKC3 3.85 4.00 4.15 V Over Load & Open Loop Detection Limit for Comparator C4 VFBC4 4.28 4.50 4.72 V Active Burst Mode Level for Comparator C5 VFBC5 1.23 1.35 1.43 V Active Burst Mode Level for Comparator C6a VFBC6a 3.48 3.61 3.76 V Version 2.3 18 After Active Burst Mode is entered 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Electrical Characteristics Parameter Symbol Limit Values min. typ. max. Unit Test Condition Active Burst Mode Level for Comparator C6b VFBC6b 2.88 3.00 3.12 V After Active Burst Mode is entered Overvoltage Detection Limit VVCCOVP 23 24 25 V VFB = 5V Latch Enable level at BL pin VLE 0.07 0.1 0.2 V > 30ms Charging current at BL pin IBK 5.8 8.4 10.9 mA Charge starts after the built-in 20ms blanking time elapsed Latched Thermal Shutdown1) TjSD 130 140 150 °C Built-in Blanking Time for Overload Protection or enter Active Burst Mode tBK - 20 - ms without external capacitor at BL pin Inhibit Time for Latch Enable function during Start up tIHLE - 1.0 - ms Count when VCC > 18V Spike Blanking Time before Latch off tSpike - 8.0 - ms VVCCPD 5.2 6.23 7.8 V or Auto Restart Protection Power Down Reset for Latched Mode 1) After Latched Off Mode is entered The parameter is not subjected to production test - verified by design/characterization. The thermal shut down temperature refers to the junction temperature of the controller. Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD 4.3.6 Current Limiting Parameter Symbol Limit Values min. typ. max. Unit Test Condition dVsense / dt = 0.6V/ms (see Figure 13) Peak Current Limitation (incl. Propagation Delay) Vcsth 0.99 1.06 1.09 V Peak Current Limitation during Active Burst Mode VCS2 0.27 0.31 0.37 V Leading Edge Blanking tLEB - 220 - ns CS Input Bias Current ICSbias -1.5 -0.2 - mA Over Current Detection for Latched Off Mode VCS1 1.570 1.66 1.764 V CS Spike Blanking for Comparator C11 tCSspike - 190 - ns Version 2.3 19 VCS =0V 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Electrical Characteristics 4.3.7 CoolMOS™ Section Parameter Symbol Limit Values min. typ. max. Unit Test Condition Drain Source Breakdown Voltage V(BR)DSS 600 650 - - V V Tj = 25°C Tj = 110°C Drain Source On-Resistance RDSon - 2.95 6.60 3.42 7.56 W W Tj = 25°C Tj=125°C1) at ID = 1.0A Effective output capacitance, energy related Co(er) - 7.0 - pF VDS = 0V to 480V Rise Time trise - 302) - ns - 2) - ns Fall Time tfall 30 1) The parameter is not subjected to production test - verified by design/characterization 2) Measured in a Typical Flyback Converter Application Version 2.3 20 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Temperature derating curve 5 Temperature derating curve Figure 21 Safe Operating area ( SOA ) curve Figure 22 SOA temperature derating coefficient curve Version 2.3 21 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Outline Dimension 6 Outline Dimension PG-DIP-8 (Plastic Dual In-Line Package) Figure 23 PG-DIP-8 (PB-free Plating Plastic Dual In-Line Outline) Version 2.3 22 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Marking 7 Marking Marking Figure 24 Marking Version 2.3 23 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Schematic for recommended PCB layout 8 Schematic for recommended PCB layout Figure 25 Schematic for recommended PCB layout General guideline for PCB layout design using F3 CoolSET (refer to Figure 25): 1. “Star Ground “at bulk capacitor ground, C11: “Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 25): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern) Version 2.3 24 30 Jun 2011 CoolSET™-F3 ICE3A1065LJ Schematic for recommended PCB layout b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11. Version 2.3 25 30 Jun 2011 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. 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