CoolS ET ™ F3R80
ICE3AR2280VJZ
O f f - L i n e S MP S C u r r e n t Mo d e C o n t r o l l e r wi t h
i n t e g r a t e d 8 0 0 V CoolMOS™ a n d S t a r t u p c e l l
(input OVP & frequency jitter) in DIP -7
Dat a Sheet
V2.1 2013-10-22
Po wer Manag em ent & Mult im ar k et
Edition 2013-10-22
Published by Infineon Technologies AG,
81726 Munich, Germany.
© 2013 Infineon Technologies AG
All Rights Reserved.
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CoolSET™ F3R80
ICE3AR2280VJZ
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™,
TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS
Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of
Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems
Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc.
SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software
Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc.
TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™
of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™
of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2011-11-11
Data Sheet
3
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Revision History
Major changes since previous revision
Date
Version
22 Oct 2013
2.1
Changed By
Change Description
New datasheet format
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Data Sheet
4
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Table of Contents
Revision History .............................................................................................................................................. 4
Table of Contents ............................................................................................................................................ 5
Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS™ and Startup cell (input OVP &
frequency jitter) in DIP-7................................................................................................................. 7
1
1.1
1.2
Pin Configuration and Functionality ........................................................................................... 8
Pin Configuration with PG-DIP-7 .................................................................................................... 8
Pin Functionality............................................................................................................................. 8
2
Representative Block Diagram .................................................................................................. 10
3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.2.1
3.7.2.2
3.7.2.3
3.7.2.4
3.7.3
3.7.3.1
3.7.3.2
3.7.4
3.7.5
Functional Description............................................................................................................... 11
Introduction .................................................................................................................................. 11
Power Management ..................................................................................................................... 11
Improved Current Mode ............................................................................................................... 12
PWM-OP................................................................................................................................. 14
PWM-Comparator ................................................................................................................... 14
Startup Phase .............................................................................................................................. 14
PWM Section ............................................................................................................................... 17
Oscillator................................................................................................................................. 17
PWM-Latch FF1 ...................................................................................................................... 17
Gate Driver ............................................................................................................................. 17
Current Limiting............................................................................................................................ 18
Leading Edge Blanking ........................................................................................................... 19
Propagation Delay Compensation (patented)........................................................................... 19
Control Unit .................................................................................................................................. 20
Basic and Extendable Blanking Mode...................................................................................... 20
Active Burst Mode (patented) .................................................................................................. 21
Selectable burst entry level................................................................................................. 22
Entering Active Burst Mode ................................................................................................ 23
Working in Active Burst Mode ............................................................................................. 23
Leaving Active Burst Mode ................................................................................................. 23
Protection Modes .................................................................................................................... 24
Vcc OVP, OTP and Vcc under voltage................................................................................ 25
Over load, open loop protection .......................................................................................... 26
Input OVP Mode...................................................................................................................... 27
Action sequence at BV pin ...................................................................................................... 28
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Electrical Characteristics........................................................................................................... 30
Absolute Maximum Ratings .......................................................................................................... 30
Operating Range.......................................................................................................................... 31
Characteristics ............................................................................................................................. 31
Supply Section ........................................................................................................................ 31
Internal Voltage Reference ...................................................................................................... 32
PWM Section .......................................................................................................................... 32
Soft Start time ......................................................................................................................... 32
Control Unit ............................................................................................................................. 33
Current Limiting....................................................................................................................... 34
Data Sheet
5
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
4.3.7
CoolMOS™ Section ................................................................................................................ 34
5
Typical Controller Performance Characteristics ...................................................................... 35
6
CoolMOS™ Performance Characteristics ................................................................................. 36
7
Input Power Curve ..................................................................................................................... 38
8
Outline Dimension ..................................................................................................................... 39
9
Marking ....................................................................................................................................... 40
10
Schematic for recommended PCB layout ................................................................................. 41
Data Sheet
6
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS™
and Startup cell (input OVP & frequency jitter) in DIP-7
Product Highlights
800V avalanche rugged CoolMOS™ with startup cell
Active Burst Mode to reach the lowest Standby Power =6.8nF (5%,X7R)
17V) during the 1st start up but it does not detect in the
subsequent re-start due to auto-restart protection. In case there is protection triggered such as input OVP before
starts up, the detection will be held until the protection is removed. When the Vcc reaches the UVLO “ON” in the 1st
start up, the capacitor CFB at FBB pin is charged by a 5V voltage source through the RFB resistor. When the voltage
at FBB pin hits 4.5V, the FF4 will be set, the switch S9 is turned “ON” and the counter will increase by 1. Then the
CFB is discharged through a 500Ω resistor. After reaching 0.5V, the FF4 is reset and the switch S9 is turned “OFF”.
Then the CFB capacitor is charged by the 5V voltage source again until it reaches 4.5V. The process repeats until
the end of 1ms. Then the detection is ended. After that, the total number of count in the counter is compared and
the VFB-burst and the Vcs_burst are selected accordingly (Figure 26)
Data Sheet
22
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
VFB_burst
VCSth_burst
5V
Comparator
logic
counter
UVLO
RFB
4.5V
FBB
C19
S
Q
FF4
CFB
500
S9
0.5V
UVLO during
1st startup
C20
R
1ms
timer
Control Unit
Figure 26:
3.7.2.2
Entry Burst Mode detection
Entering Active Burst Mode
The FBB signal is kept monitoring by the comparator C5 (Figure 25). During normal operation, the internal
blanking time counter is reset to 0. When FBB signal falls below VFB_burst, it starts to count. When the counter reaches
20ms and FBB signal is still below VFB_burst, the system enters the Active Burst Mode. This time window prevents a sudden
entering into the Active Burst Mode due to large load jumps.
After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the
current consumption of the IC to about 620µA.
It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5V such that the
Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The
minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest
VCC level is reached at no load condition.
3.7.2.3
Working in Active Burst Mode
After entering the Active Burst Mode, the FBB voltage rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors the FBB signal. If the voltage level is larger than 3.5V, the
internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active
Burst Mode the gate G10 is released and the current limit is reduced to Vcsth_burst (Figure 3 and Figure 25). In one
hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at V OUT is
still kept unchanged, the FBB signal will drop to 3.2V. At this level the C6b deactivates the internal circuit again
by switching off the Internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst
Mode. In Active Burst Mode, the FBB voltage is changing like a saw tooth between 3.2V and 3.5V (Figure 27).
3.7.2.4
Leaving Active Burst Mode
The FBB voltage will increase immediately if there is a high load jump. This is observed by the comparator C13
(Figure 25). Since the current limit is reduced to 31%~45% of the maximum current during active burst mode, it
needs a certain load jump to raise the FBB signal to exceed 4.0V. At that time the comparator C5 resets the
Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can
then be resumed to stabilize VOUT.
Data Sheet
23
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
VFBB
Entering
Active Burst
Mode
4.0V
3.5V
3.2V
Leaving Active
Burst Mode
VFB_burst
Blanking Timer
t
20ms Blanking Time
VCS
Vcsth
t
Current limit level during
Active Burst Mode
Vcsth_burst
VVCC
t
10.5V
IVCC
t
5.7mA
620uA
VOUT
t
t
Figure 27:
3.7.3
Signals in Active Burst Mode
Protection Modes
The IC provides Auto Restart mode as the major protection feature. Auto Restart mode can prevent the SMPS from
destructive states. There are 3 kinds of auto restart mode; normal auto restart mode, odd skip auto restart mode
and non switch auto restart mode. Odd skip auto restart mode is that there is no detect of fault and no switching
pulse for the odd number restart cycle. At the even number of restart cycle the fault detect and soft start switching
pulses maintained. If the fault persists, it would continue the auto-restart mode. However, if the fault is removed,
it can release to normal operation only at the even number auto restart cycle (Figure 28).
VVCC
Fault
detected
Startup and detect
No detect
No detect
17V
10.5V
VCS
t
t
Figure 28:
Data Sheet
Odd skip auto restart waveform
24
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
Non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are also
suppressed at the even number of the restart cycle. The detection of fault still remains at the even number of the
restart cycle. When the fault is removed, the IC will resume to normal operation at the even number of the restart
cycle (Figure 29).
Fault
detected
VVCC
Startup and detect
No detect
No detect
17V
10.5V
VCS
t
No switching
t
Figure 29:
Non switch auto restart waveform
The main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto
restart protection can be reduced. This feature is particularly good for smaller Vcc capacitor where the restart time
is shorter.
The following table lists the possible system failures and the corresponding protection modes.
VCC Over voltage (1)
Odd skip Auto Restart Mode
VCC Over voltage (2)
Odd skip Auto Restart Mode
Over load
Odd skip Auto Restart Mode
Open Loop
Odd skip Auto Restart Mode
VCC Undervoltage
Normal Auto Restart Mode
Short Optocoupler
Normal Auto Restart Mode
Over temperature
Non switch Auto Restart Mode
3.7.3.1
Vcc OVP, OTP and Vcc under voltage
Auto Restart
Mode Reset
VVCC < 10.5V
Thermal Shutdown
Tj >130°C
25.5V
C2
120μs blanking
time
Spike
Blanking
30μs
Auto Restart
mode
VCC
C1
20.5V
4.5V
C4
&
Voltage
Reference
G1
Control Unit
FBB
softs_period
Figure 30:
Vcc OVP and OTP
There are 2 types of Vcc over voltage protection; Vcc OVP (1) and Vcc OVP (2). The Vcc OVP (1) takes action
only during the soft start period. The Vcc OVP (2) takes the action in any conditions.
Vcc OVP (1) condition is when VVCC voltage is > 20.5V, VFBB voltage is > 4.5V and during soft start period, the IC
enters into odd skip Auto Restart Mode. This condition likely happens during start up at open loop fault (Figure 30).
Data Sheet
25
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
Vcc OVP (2) condition is when V VCC voltage is > 25.5V, the IC enters into odd skip Auto Restart Mode (Figure
30).
The over temperature protection OTP is sensed inside the controller IC. The Thermal Shutdown block keeps on
monitoring the junction temperature of the controller. After detecting a junction temperature higher than 130°C, the
IC will enter into the non switch Auto Restart mode. The ICE3AR2280VJZ has also implemented with a 50°C
hysteresis. That means the IC can only be recovered when the controller junction temperature is dropped 50 °C
lower than the over temperature trigger point (Figure 30).
The VCC undervoltage and short opto-coupler will go into the normal auto restart mode inherently.
In case of VCC undervoltage, the Vcc voltage drops indefinitely. When it drops below the Vcc under voltage lock out
“OFF” voltage (10.5V), the IC will turn off the IC and the startup cell will turn on again. Then the Vcc voltage will be
charged up to UVLO “ON” voltage (17V) and the IC turns on again provided the startup cell charge up current is not
drained by the fault. If the fault is not removed, the Vcc will continue to drop until it hits UVLO “OFF” voltage and the
restart cycle repeats.
Short Optocoupler can lead to Vcc undervoltage because once the opto-coupler (transistor side) is shorted, the
feedback voltage will drop to zero and there will be no switching pulse. Then the Vcc voltage will drop same as
the Vcc undervoltage.
3.7.3.2
Over load, open loop protection
Voltage
Reference
5.0V
Auto Restart
Mode Reset
VVCC < 10.5V
Ichg_EB
Auto
Restart
Mode
S1
ROV2 CBK
#
4.5V
BV
C11
counter
500
0.9V
C3
CT1
Spike
Blanking
30us
&
G5
S2
FBB
20ms
Blanking
Time
C4
4.5V
Figure 31:
Control Unit
Over load, open loop protection
In case of Overload or Open Loop, the FBB exceeds 4.5V which will be observed by comparator C4. Then the builtin blanking time counter starts to count. When it reaches 20ms, the extended blanking time counter CT1 is
activated. The switch S2 is turned on and the voltage at the BV pin will be discharged through 500Ω resistor. When
it drops to 0.9V, the switch S2 is turned off and the Switch S1 is turned on. Then a constant current source Ichg_EB
will start to charge up BV pin. When the voltage hits 4.5V which is monitored by comparator C11, the switch S1 is
turned off and the count will increase by 1. Then the switch S2 will turn on again and the voltage will drop to 0.9V
and rise to 4.5V again. The count will then increase by 1 again. When the total count reaches 256, the counter
CT1 will stop and it will release a high output signal. When both the input signals at AND gate G5 is high, the
odd skip Auto Restart Mode is activated after the 30µs spike blanking time (Figure 31).
The total blanking time depends on the addition of the built-in and the extended blanking time. If there is no CBK
capacitor at BV pin, the count will finish within 0.1ms and the equivalent blanking time is just the built-in time of
20ms.
Since the BV pin is a multi-function pin, it would share with different functions. The resistor ROV2 from input OVP
feature application may however affect the extendable blanking time (Figure 31). Thus it should take the ROV2
into the calculation of the extendable blanking time. For example the extended blanking time may be changed
from 181ms to 212ms for 42.2KΩ to 15KΩ ROV2 resistor. The list below shows one particular CBK, ROV2 vs
blanking time.
Data Sheet
26
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
CBK
ROV2
Extended blanking time
Overall blanking time
0.1uF
42.2KΩ
161ms
181ms
0.1uF
39.6KΩ
162ms
182ms
0.1uF
15KΩ
192ms
212ms
Another factor to affect the extended blanking time is the input voltage through the ROV1 and ROV2. It would, on the
contrary, reduce the extended blanking time.
3.7.4
Input OVP Mode
When the AC input voltage is out of the designed operating range (e.g. > 300Vac), the voltage at the input bulk
capacitor will increase at the same time. If the MOSFET keeps on switching, the drain voltage may be too high and
the MOSFET will exceed the maximum voltage rating and causes damages. The input OVP mode is to prevent this
phenomenon. The IC will sense the input voltage through the input bulk capacitor to the BV pin by 2 potential divider
resistors, ROV1 and ROV2 (Figure 32). During normal operation, the BV pin voltage is lower than VOVP_ref (1.98V). The
output of C14a is low and the output of G21 is high. Together with UVLO high signal (IC operating) the “S” input of
FF5 is low. The “Q” output of FF5 is low and the input OVP mode remains not activated. When there is an input over
voltage case, the input bulk capacitor voltage is increased and the BV voltage is increased to larger than VOVP_ref. The
output of C14a is high and the output of G21 is low. If the OVP persists for 400µs (blanking time) and the UVLO
signal is still high, the output of G20 is high. Then the “S” input of FF5 is high and the “Q” output of FF5 is high. The
input OVP mode is set. The case of UVLO signal low is not considered as it means the IC is not working.
UVLO
Q
S
G20
Vbulk
400µs Blanking
time
1.98V
ROV1
R
Q
FF5
G21
C14a
Input OVP
BV
G22
5µs Blanking
time
C14b
ROV2
1.91V
Control Unit
Figure 32:
Input OVP detection circuit
Once the system enters the input OVP mode, there will be no switching pulse and the IC keeps on monitoring the
BV signal. If the input OVP signal is not reset, there is no switching pulse in each restart cycle (Figure 33).
VBV
Input OVP
detected
Input OVP
released
1.98V
1.91V
VVCC
Switching start at the
following restart cycle
t
17V
10.5V
VCS
t
No switching
t
Figure 33:
Data Sheet
Input OVP mode waveform
27
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
The IC implemented with hysteresis voltage to leave the input OVP protection. The hysteresis voltage at BV pin is
VOVP_hys (0.07V) and the input OVP reset voltage at BV pin is VOVP_ref - VOVP_hys; i.e. 1.91V. After the input OVP
protection is triggered, the voltage at BV pin needs to drop VOVP_hys from VOVP_ref before it can be reset.
When the BV voltage drops below 1.91V, the output of C14b and G22 are high (Figure 32). The “R” input of the
FF5 is high. Then the “Q” output of FF5 is low. The input OVP is reset. The system will turn on with soft start in the
coming restart cycle when Vcc reaches the Vcc “ON” voltage at 17V.
The input OVP feature can also be applied to customer defined protection circuit by pulling up the BV pin to
larger than VOVP_ref.
The formula to calculate the ROV1 and ROV2 are as below.
Set ROV1 to a particular value.
ROV2= ROV1* VOVP_ref /(VOVP - VOVP_ref)
The formula to calculate the input OVP reset voltage is as below.
VOVP_reset=(VOVP_ref - VOVP_hys)*( ROV1+ROV2)/ROV2
where VOVP: input over voltage; VOVP_reset: input over reset voltage; VOVP_ref: IC reference voltage for OVP; VOVP_hys: IC
hysteresis voltage for OVP; ROV1 and ROV2: resistors divider from input voltage to BV pin.
For example,
VOVP_ref=1.98V, VOVP_hys=0.07V
If input OVP voltage, VOVP=424Vdc (300Vac), ROV1=9MΩ, ROV2=42.2KΩ
Input OVP reset, VOVP_reset=408Vdc (289Vac)
To disable input OVP feature, the BV pin must be connected with a resistor ROV2≥15KΩ to IC ground and
remove ROV1.
(Remark: ROV2 must be always ≥15KΩ in all conditions, otherwise overload protection may not work)
3.7.5
Action sequence at BV pin
Since there are 2 functions at the same BV pin; input OVP and extended blanking time, the action of sequence is
whichever starts first takes the priority. When the “Extended blanking time” is triggered by OLP and follows with the
“Input OVP” triggering, then the OLP will continue to work until it ends. The IC would recheck the signal at BV pin
after one skip cycle. If the BV signal exceeds the input OVP threshold, it would go to input OVP mode.
Data Sheet
28
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
OLP
detected
OLP
released
VFB
4.5V
Extended OLP
blanking time
Built in 20ms OLP
blanking time
VBV
4.5V
Input OVP
Input OVP fault started( but
overridden by extended blanking
OLP time)
Input OVP
detected
t
Input OVP
released
1.98V
1.91V
0.9V
t
Switching start at the
following restart cycle
VVCC
17V
10.5V
t
VCS
No switching
t
Figure 34:
Input OVP during extended blanking time
One typical case happened is that the overload happened first and it follows with the “Input OVP” feature at the 1st
20ms blanking time. Since the overload protection is still not triggered at the 1st 20ms blanking time period and the
extended blanking time is not running, the input OVP mode will trigger right away.
OLP
detected
OLP
released
VFB
4.5V
Built in 20ms OLP
blanking time
t
Input OVP
VBV
Input OVP
detected
Input OVP
released
1.98V
1.91V
VVCC
Switching start at the
following restart cycle
t
17V
10.5V
t
VCS
No switching
t
Figure 35:
Data Sheet
Input OVP during first 20ms blanking time
29
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings
are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
°
(VCC) is discharged before assembling the application circuit. Ta=25 C unless otherwise specified.
Parameter
Symbol
Limit Values
Unit
min.
max.
VDS
-
800
V
ID_Puls
-
4.9
A
Avalanche energy, repetitive tAR limited
by max. Tj=150°C1)
EAR
-
0.047
mJ
Avalanche current, repetitive tAR limited
by max. Tj=150°C
IAR
-
1.5
A
Drain Source Voltage
Pulse drain current, tp limited by Tjmax
VCC Supply Voltage
VVCC
-0.3
27
V
FBB Voltage
VFBB
-0.3
5.5
V
BV Voltage
VBV
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
Junction Temperature
Storage Temperature
-40
Tj
V
150
°
°
TS
-55
150
Thermal Resistance
Junction -Ambient
RthJA
-
96
Soldering temperature,
wavesoldering only allowed at leads
Tsold
-
260
ESD Capability (incl. Drain Pin)
VESD
-
2
Remarks
C
Controller & CoolMOS™
C
K/W
°
1.6mm (0.063in.) from
case for 10s
kV
Human body model2)
C
1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5KΩ series resistor)
Data Sheet
30
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Electrical Characteristics
4.2
Operating Range
Note: Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
V
Max value limited due to Vcc OVP
VCC Supply Voltage
VVCC
VVCCoff
25
Junction Temperature of
Controller
TjCon
-40
130
°
Junction Temperature of
CoolMOS™
TjCoolMOS
-40
150
°
4.3
Characteristics
4.3.1
Supply Section
C
Max value limited due to thermal
shut down of controller
C
Note: The electrical characteristics involve the spread of values within the specified supply voltage and
junction temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 17 V is assumed.
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
IVCCstart
-
200
300
μA
VVCC =16V
IVCCcharge1
-
-
5.0
mA
VVCC = 0V
IVCCcharge2
0.55
0.9
1.60
mA
VVCC = 1V
IVCCcharge3
0.38
0.7
-
mA
VVCC =16V
Leakage Current of
Start Up Cell and CoolMOS™
IStartLeak
-
0.2
50
μA
Supply Current with
Inactive Gate
IVCCsup1
-
1.9
3.2
mA
Supply Current with Active Gate
IVCCsup2
-
3.4
4.8
mA
IFBB = 0A
Supply Current in
Auto Restart Mode with Inactive
Gate
IVCCrestart
-
320
-
μA
IFBB = 0A
Supply Current in Active Burst
Mode with Inactive Gate
IVCCburst1
-
620
950
μA
VFBB = 2.5V
IVCCburst2
-
620
950
μA
VVCC = 11.5V, VFBB
= 2.5V
VVCCon
VVCCoff
VVCChys
16.0
9.8
-
17.0
10.5
6.5
18.0
11.2
-
V
V
V
Start Up Current
VCC Charge Current
VCC Turn-On
ThresholdVCC Turn-Off
Threshold VCC Turn-On/Off
Hysteresis
VDrain = 650V
1)
at Tj=100°C
1) The parameter is not subjected to production test - verified by design/characterization
Data Sheet
31
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Electrical Characteristics
4.3.2
Internal Voltage Reference
Parameter
Trimmed Reference Voltage
4.3.3
Symbol
VREF
Limit Values
Unit
min.
typ.
max.
4.90
5.00
5.10
V
Test Condition
measured at pin FBB
IFBB = 0
PWM Section
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
fOSC1
87
100
113
kHz
fOSC2
90
100
108
kHz
Tj = 25°C
Frequency Jittering Range
fjitter
-
±4.0
-
kHz
Tj = 25°C
Frequency Jittering period
Tjitter
-
4.0
-
ms
Tj = 25°C
Max. Duty Cycle
Dmax
0.70
0.75
0.80
Min. Duty Cycle
Dmin
0
-
-
PWM-OP Gain
AV
3.05
3.25
3.45
Voltage Ramp Offset
VOffset-Ramp
-
0.60
-
V
VFBB Operating Range
Min Level
VFBmin
-
0.7
-
V
VFBB Operating Range Max
level
VFBmax
-
-
4.3
V
RFB
9.0
15.4
23.0
kΩ
Fixed Oscillator Frequency
FBB Pull-Up Resistor
VFBB < 0.3V
CS=1V, limited by
Comparator C41)
1) The parameter is not subjected to production test - verified by design/characterization
4.3.4
Soft Start time
Parameter
Soft Start time
Data Sheet
Symbol
tSS
Limit Values
Unit
min.
typ.
max.
-
10
-
32
Test Condition
ms
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Electrical Characteristics
4.3.5
Control Unit
Parameter
Symbol
Input OVP reference voltage for
comparator C14a
VOVP_ref
Input OVP hysteresis C14b
VOVP_hys
Limit Values
Unit
min.
typ.
max.
1.90
1.98
2.06
0.07
Test Condition
V
Tj = 25°C
V
Tj = 25°C
Blanking time voltage lower limit
for Comparator C3
VBKC3
0.80
0.90
1.00
V
Blanking time voltage upper limit
for Comparator C11
VBKC11
4.28
4.50
4.72
V
Over Load Limit for Comparator C4
VFBC4
4.28
4.50
4.72
V
Entry Burst select High level for
Comparator C19
VFBC19
4.28
4.50
4.72
V
Entry Burst select Low level for
Comparator C20
VFBC20
0.40
0.50
0.60
V
10% Pin_max
VFB_burst1
1.51
1.60
1.69
V
< 7 counts
6.67% Pin_max
VFB_burst2
1.34
1.42
1.50
V
8 ~ 39 counts
4.38% Pin_max
VFB_burst3
1.20
1.27
1.34
V
40 ~ 191 counts
Active Burst Mode High Level for
Comparator C6a
VFBC6a
3.35
3.50
3.65
V
In Active Burst Mode
Active Burst Mode Low Level for
Comparator C6b
VFBC6b
3.06
3.20
3.34
V
Active Burst Mode Level for
Comparator C13
VFBC13
3.85
4.00
4.15
V
Overvoltage Detection Limit for
Comparator C1
VVCCOVP1
19.5
20.5
21.5
V
Overvoltage Detection Limit for
Comparator C2
VVCCOVP2
25.0
25.5
26.3
V
Ichg_EB
460
720
864
μA
TjSD
130
140
150
°
Active Burst Mode
Entry Level for
Comparator C5
Charging current for extended
blanking time
Thermal Shutdown1)
C
TjSD_hys
-
50
-
°
tBK
-
20
-
ms
Timer for entry burst select
tEBS
-
1
-
ms
Spike Blanking Time for Auto-Restart
Protection
tSpike
-
30
-
μs
Hysteresis for thermal Shutdown1)
Built-in Blanking Time for Overload
Protection or enter Active Burst Mode
1)
VFBB = 5V, during soft
start
Controller
C
The parameter is not subjected to production test - verified by design/characterization. The thermal shutdown temperature refers to the
junction temperature of the controller.
Note:
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except
VVCCOVP and VVCCPD
Data Sheet
33
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Electrical Characteristics
4.3.6
Current Limiting
Parameter
Symbol
Peak Current Limitation
(incl. Propagation Delay)
Peak Current
20% Pin_max
Limitation during
Active Burst Mode 13.3% Pin_max
9.6% Pin_max
Leading Edge
Blanking
Vcsth
Unit
min.
typ.
max.
0.98
1.06
1.13
V
Test Condition
dVsense / dt = 0.6V/µs
(Figure 21)
Vcsth_burst1
0.37
0.45
0.51
V
< 7 counts
Vcsth_burst2
0.30
0.37
0.44
V
8 ~ 39 counts
Vcsth_burst3
0.23
0.31
0.37
V
40 ~ 191 counts
Normal mode
tLEB_normal
-
220
-
ns
Burst mode
tLEB_burst
-
180
-
ns
ICSbias
-1.5
-0.2
-
μA
CS Input Bias Current
4.3.7
Limit Values
VCS =0V
CoolMOS™ Section
Parameter
Drain Source Breakdown Voltage
Drain Source On-Resistance
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
V(BR)DSS
800
870
-
-
V
V
Tj = 25°C
Tj = 110°C1)
RDSon
-
2.26
5.02
2.62
5.81
Ω
Ω
Tj = 25°C
Effective output capacitance, energy
related
Co(er)
-
16.3
-
pF
Rise Time
trise
-
302)
-
ns
Tj=125°C1)
at ID = 0.81A
VDS = 0V to 480V
2)
30
ns
tfall
1) The parameter is not subjected to production test - verified by design/characterization
Fall Time
2) Measured in a Typical Flyback Converter Application
Data Sheet
34
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Typical Controller Performance Characteristics
5
Typical Controller Performance Characteristics
Characterisrtic graphs are normalized at Ta=25°C
Figure 36:
Line OVP (VOVP_ref) vs. T a
Figure 37:
Hystersis of Line OVP (VOVP_hys) vs. T a
Data Sheet
35
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
CoolMOS™ Performance Characteristics
6
CoolMOS™ Performance Characteristics
Figure 38:
Safe Operating Area (SOA) curve for ICE3AR2280VJZ
Figure 39:
SOA temperature derating coefficient curve
Data Sheet
36
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
CoolMOS™ Performance Characteristics
Figure 40:
Power dissipation; P tot=f(T a)
Figure 41:
Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA
Data Sheet
37
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Input Power Curve
7
Input Power Curve
Two input power curves giving the typical input power versus ambient temperature are showed below;
Vin=85Vac~265Vac (Figure 42) and Vin=230Vac+/-15% (Figure 43). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum
secondary to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink
for the device. The input power already includes the power loss at input common mode choke, bridge rectifier
and the CoolMOS.The device saturation current (ID_Puls @ Tj=125°C) is also considered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 42),
operating temperature is 50°C, estimated efficiency is 85%, then the estimated output power is 23W (28W * 85%).
Figure 42:
Input power curve Vin=85~265Vac; Pin=f(T a)
Figure 43:
Input power curve Vin=230Vac; Pin=f(Ta)
Data Sheet
38
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Outline Dimension
8
Figure 44:
Data Sheet
Outline Dimension
PG-DIP-7 (Pb-free lead plating Plastic Dual-in-Line Outline)
39
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Marking
9
Figure 45:
Data Sheet
Marking
Marking for ICE3AR2280VJZ
40
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Schematic for recommended PCB layout
10
Figure 46:
Schematic for recommended PCB layout
Schematic for recommended PCB layout
General guideline for PCB layout design using F3 CoolSET™ (refer to Figure 46):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET™
device effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET™ device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET™ IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller
pin as possible so as to reduce the switching noise coupled into the controller.
Data Sheet
41
V2.1, 2013-10-22
CoolSET™ F3R80
ICE3AR2280VJZ
Schematic for recommended PCB layout
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 46):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke,
L1: Gap separation is around 1.5mm (no safety concern)
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:
These 2 Spark Gaps can be used when the lightning surge requirement is>6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET™
and reduce the abnormal behavior of the CoolSET™. The diode can be a fast speed diode such as 1N4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through
the sensitive components such as the primary controller, IC11.
Data Sheet
42
V2.1, 2013-10-22
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