ICE3AR4780JG
Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
Product Highlights
800 V avalanche rugged CoolMOS™ with startup cell
Active Burst Mode to reach the lowest Standby Power 130°C
C11
Clock
Soft-Start
Comparator
Freq. jitter
&
G7
C7
Counter
500
C3
CT1
C4
20ms
Blanking
Time
4.5V
5.0V
&
G5
Auto
Restart
Mode
Spike
Blanking
30us
Gate
Driver
&
G9
C8
PWM
Comparator
C13
RFB
CFB
FF1
S
R Q
1
G8
0.9V
S2
FBB
PWM Section
0.75
25k
4.0V
2pF
VFB_burst
Burst
detect and
adjust
C5
20ms Blanking Time
C6a
400ns Blanking Time
C6b
400ns Blanking Time
Active Burst
Mode
Propagation-Delay
Compensation
0.62V
C10
Current Limiting
LEB
220ns
Vcsth
x3.25
3.5V
Vcs_burst VFB_burst
3.2V
&
G10
PWM OP
&
G11
Current Mode
or
G13
Control Unit
ICE3ARxx80JZ / CoolSET®-F3R80 ( Brownout & Jitter Mode )
S4
LEB
180ns
C12
10k
1pF
CS
D1
RSense
Vcsth_burst
Propagation-Delay
Compensation-Burst
# : optional external components;
#1 : CBK is used to extend the Blanking Time
#2 : RBO1 & RBO2 are used for brownout feature; RBO1 tie to Vcc if no brownout feature
#3 : TAE is used to enable the external Auto-restart feature
Figure 3
Data Sheet
Representative Block Diagram
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3
Functional Description
All values which are used in the functional description are typical values. For calculating the worst cases the
min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.1
Introduction
CoolSET™-F3R80 brownout and jitter 800 V version (ICE3AR4780JG) is the enhanced version of the CoolSET™F3R 650V version (ICE3BRxx65J). It is particular good for high voltage margin low power SMPS application such
as auxiliary power supply for PC and server. The major characteristics are that the IC is developed with 800 V
CoolMOS™ with start up cell, having adjustable brownout feature, running at 100 kHz switching frequency and
packed in DIP-16/12 package. It is derived from F3R 650 V version. Thus most of the good features are retained.
Besides, it includes some enhanced features and new features.
The retained good features include BiCMOS technology to reduce power consumption and increase the Vcc
voltage range, cycle by cycle current mode control, built-in 10ms soft start to reduce the stress of switching
elements during start up, built-in 20 ms and extended blanking time for short period of peak power before
entering protection, active burst mode for lowest standby power and propagation delay compensation for
close power limit between high line and low line, frequency jittering for low EMI performance, the built-in autorestart mode protections for open loop, over load, Vcc OVP, Vcc under voltage, etc. and also the most flexible
external auto-restart enable, etc.
The enhanced features include narrowing the feedback voltage swing from 0.5V to 0.3V during burst mode so
that the output voltage ripple can be reduced by 40%, reduction of the fast voltage fall time of the MOSFET by
increasing the soft turn-on time and addition of 50 Ω turn-on resistor, faster start up time by optimizing the VCC
capacitor to 10 µF and over temperature protection with 50°C hysteresis.
The new features include adjustable brownout for reliable output performance, selectable entry and exit burst
mode so that smaller entry/exit power to burst mode or even no burst mode is possible and the propagation
delay compensation for burst mode so that the entry/exit burst mode power is close between high line and low
line.
In summary, the CoolSET™ F3R80 provides good voltage margin of MOSFET, lowest standby power, flexible
burst level, reduced output ripple during burst mode, reliable output with brownout feature, accurate power
limit for both maximum power and burst power, low EMI with frequency jittering and soft gate drive, built-in
and flexible protections, etc. Therefore, CoolSET™ F3R80 is a complete solution for the low power SMPS
application.
Data Sheet
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3.2
Power Management
Drain
VCC
Startup Cell
CoolMOS®
Power Management
Undervoltage Lockout
17V
Internal Bias
10.5V
Voltage
Reference
Power-Down Reset
5.0V
Auto Restart
Mode
Soft Start block
Figure 4
Active Burst Mode
Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main
line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the
VCC pin. This VCC charge current is controlled to 0.9 mA by the Startup Cell. When the VVCC exceeds the onthreshold VVCCon = 17 V the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage
Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage.
To avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. The switch-off of the
controller can only take place when VVCC falls below 10.5 V after normal operation was entered. The maximum
current consumption before the controller is activated is about 200 µA.
When VVCC falls below the off-threshold VVCCoff = 10.5 V, the bias circuit is switched off and the soft start counter is
reset. Thus it ensures that at every startup cycle the soft start starts at zero.
The internal bias circuit is switched off if Auto Restart Mode is entered. The current consumption is then
reduced to 320 µA.
Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption below 620 µA.
Data Sheet
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3.3
Improved Current Mode
Soft-Start Comparator
PWM-Latch
FBB
C8
R
Q
Driver
S
Q
0.6V
PWM OP
x3.25
CS
Improved
Current Mode
Figure 5
Current Mode
Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing
the FBB signal with the amplified current sense signal.
Amplified Current Signal
FBB
0.6V
Driver
t
ton
t
Figure 6
Pulse Width Modulation
In case the amplified current sense signal exceeds the FBB signal the on-time ton of the driver is finished by
resetting the PWM-Latch (Figure 6).
The primary current is sensed by the external series resistor RSense inserted in the source of the integrated
CoolMOS™. By means of Current Mode regulation, the secondary output voltage is insensitive to the line
variations. The current waveform slope will change with the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of the maximum source current of the integrated
CoolMOS™.
To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is
superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (Figure
6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When
the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start.
Data Sheet
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Soft-Start Comparator
PWM Comparator
FBB
C8
PWM-Latch
Oscillator
VOSC
time delay
circuit (156ns)
Gate Driver
0.6V
10k
X3.25
R1
T2
V1
PWM OP
Voltage Ramp
Figure 7
Improved Current Mode
In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the comparison with the FBB-signal. The duty cycle is then controlled
by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156 ns delay time (Figure 8). It allows the duty cycle to be reduced continuously
till 0% by decreasing VFBB below that threshold.
VOSC
max.
Duty Cycle
Voltage
Ramp
t
0.6V
FBB
Gate
Driver
t
156ns time delay
t
Figure 8
3.3.1
Light Load Conditions
PWM-OP
The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor
RSense connected to pin CS. RSense converts the source current into a sense voltage. The sense voltage is
amplified with a gain of 3.25 by PWM OP. The output of the PWM-OP is connected to the voltage source V1. The
voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWM-Comparator C8 and the Soft-Start-Comparator (Figure 9).
Data Sheet
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3.3.2
PWM-Comparator
The PWM-Comparator compares the sensed current signal of the integrated CoolMOS™ with the feedback
signal VFBB (Figure 9). VFBB is created by an external optocoupler or external transistor in combination with the
internal pull-up resistor RFB and provides the load information of the feedback circuitry. When the amplified
current signal of the integrated CoolMOS™ exceeds the signal VFBB the PWM-Comparator switches off the Gate
Driver.
5V
RFB
Soft-Start Comparator
FBB
PWM-Latch
C8
PWM Comparator
0.6V
Optocoupler
PWM OP
CS
X3.25
Improved
Current Mode
Figure 9
3.4
PWM Controlling
Startup Phase
Soft Start finish
Soft Start counter
SoftS
Soft Start
Soft Start
Soft-Start
Comparator
C7
&
Gate Driver
G7
0.6V
x3.25
CS
PWM OP
Figure 10
Soft Start
In the Startup Phase, the IC provides a Soft Start period to control the primary current by means of a duty cycle
limitation. The Soft Start function is a built-in function and it is controlled by an internal counter.
Figure 11
Data Sheet
Soft Start Phase
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When the VVCC exceeds the on-threshold voltage, the IC starts the Soft Start mode (Figure 11).
The function is realized by an internal Soft Start resistor, a current sink and a counter. And the amplitude of the
current sink is controlled by the counter (Figure 12).
5V
RSoftS
SoftS
Soft Start 32I
Counter
Figure 12
8I
4I
2I
I
Soft Start Circuit
After the IC is switched on, the VSoftS voltage is controlled such that the voltage is increased step-wisely (32
steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in
every 300 µs such that the current sink decrease gradually and the duty ratio of the gate drive increases
gradually. The Soft Start will be finished in 10 ms (tSoft-Start) after the IC is switched on. At the end of the Soft Start
period, the current sink is switched off.
Within the soft start period, the duty cycle is increasing from zero to maximum gradually (Figure 12).
VSoftS
tSoft-Start
VSOFTS32
t
Gate
Driver
t
Figure 13
Gate drive signal under Soft-Start Phase
In addition to Start-Up, Soft-Start is also activated at each restart attempt during Auto Restart.
Data Sheet
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VSoftS
tSoft-Start
VSOFTS32
VFB
t
4.5V
VOUT
t
VOUT
tStart-Up
t
Figure 14
Start Up Phase
The Start-Up time tStart-Up before the converter output voltage VOUT is settled must be shorter than the SoftStart Phase tSoft-Start (Figure 14). By means of Soft-Start there is an effective minimization of current and voltage
stresses on the integrated CoolMOS™, the clamp circuit and the output rectifier and it helps to prevent
saturation of the transformer during Start-Up.
3.5
PWM Section
0.75
PWM Section
Oscillator
Duty Cycle
max
Clock
Frequency
Jitter
Soft Start
Block
Soft Start
Comparator
PWM
Comparator
FF1
Gate Driver
S
1
R
G8
Q
&
G9
Current
Limiting
CoolMOS®
Gate
Figure 15
3.5.1
PWM Section Block
Oscillator
The oscillator generates a fixed frequency of 100 kHz with frequency jittering of ±4% (which is ±4 kHz) at a
jittering period of 4 ms.
A capacitor, a current source and current sink which determine the frequency are integrated. The charging and
discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a very
Data Sheet
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accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a
maximum duty cycle limitation of Dmax = 0.75.
Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in
range of 100 kHz ± 4 kHz at period of 4 ms.
3.5.2
PWM-Latch FF1
The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the
integrated CoolMOS™. After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator
or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately.
3.5.3
Gate Driver
VCC
PWM-Latch
1
50
Gate
CoolMOS®
Gate Driver
Figure 16
Gate Driver
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the integrated CoolMOS™ threshold. This is achieved by a slope control of
the rising edge at the driver’s output (Figure 17) and adding a 50 Ω gate turn on resistor (Figure 16). Thus the
leading switch on spike is minimized.
(internal)
VGate
typ. t = 160ns
4.6V
t
Figure 17
Gate Rising Slope
Furthermore the driver circuit is designed to eliminate cross conduction of the output stage.
During power up, when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is
set to low in order to disable power transfer to the secondary side.
Data Sheet
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3.6
Current Limiting
PWM Latch
FF1
Current Limiting
Propagation-Delay
Compensation
Vcsth
LEB
220ns
C10
PWM-OP
LEB
180ns
&
C12
G10
S4
VCSth_burst
Propagation-Delay
Compensation-Burst
Active Burst
Mode
or
G13
VFB_burst
10k
C5
1pF
D1
CS
FBB
Figure 18
Current Limiting Block
There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS™ is sensed via an external sense resistor RSense. By means of RSense
the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense
exceeds the internal threshold voltage Vcsth, the comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to support the immediate shut down of the integrated CoolMOS™
with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power
can be reduced to minimal. This compensation applies to both the peak load and burst mode.
In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge Blanking
(LEB) is integrated in the current sense path for the comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. When it is activated,
the current limiting is reduced to Vcsth_burst. This voltage level determines the maximum power level in Active
Burst Mode.
3.6.1
Leading Edge Blanking
VSense
Vcsth
tLEB = 220ns/180ns
t
Figure 19
Leading Edge Blanking
Whenever the integrated CoolMOS™ is switched on, a leading edge spike is generated due to the primary-side
capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to
Data Sheet
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switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is
blanked out with a time constant of tLEB = 220 ns for normal load and tLEB = 180 ns for burst mode.
3.6.2
Propagation Delay Compensation (patented)
In case of overcurrent detection, there is always propagation delay to switch off the integrated CoolMOS™. An
overshoot of the peak current Ipeak is induced to the delay, which depends on the ratio of dI/ dt of the peak
current (Figure 20).
Signal2
Signal1
tPropagation Delay
ISense
IOvershoot2
Ipeak2
Ipeak1
ILimit
IOvershoot1
t
Figure 20
Current Limiting
The overshoot of Signal 2 is larger than of Signal 1 due to the steeper rising waveform. This change in the slope
is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot
due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current
sense threshold Vcsth and the switching off of the integrated CoolMOS™ is compensated over temperature
within a wide input range. Current Limiting is then very accurate.
For example, Ipeak = 0.5 A with RSense = 2. The current sense threshold is set to a static voltage level Vcsth=1 V
without Propagation Delay Compensation. A current ramp of dI/dt = 0.4 A/µs, or dVSense/dt = 0.8 V/µs, and a
propagation delay time of tPropagation Delay =180 ns leads to an Ipeak overshoot of 14.4%. With the propagation
delay compensation, the overshoot is only around 2% (Figure 21).
without compensation
with compensation
V
1,3
1,25
VSense
1,2
1,15
1,1
1,05
1
0,95
0,9
0
0,2
0,4
0,6
0,8
1
1,2
dVSense
dt
Figure 21
1,4
1,6
1,8
2
V
s
Overcurrent Shutdown
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (Figure 21). In
case of a steeper slope the switch off of the driver is earlier to compensate the delay.
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
VOSC
max. Duty Cycle
off time
VSense
t
Propagation Delay
Vcsth
Signal1
Figure 22
Signal2
t
Dynamic Voltage Threshold Vcsth
Similarly, the same concept of propagation delay compensation is also implemented in burst mode with
reduced level, Vcsth_burst (Figure 18). With this implementation, the entry and exit burst mode power can be very
close between low line and high line input voltage.
3.7
Control Unit
The Control Unit contains the functions for Active Burst Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode both have 20 ms internal blanking time. For the over load Auto Restart Mode, the 20
ms blanking time can be further extended by adding an external capacitor at BV pin. With the blanking time, the
IC avoids entering into those two modes accidentally. That buffer time is very useful for the application which
works in short duration of peak power occasionally.
3.7.1
Basic and Extendable Blanking Mode
5.0V
Auto
Restart
Mode
Ichg_EB
S1
Spike
Blanking
30us
4.5V
ROV2
#
C11
BV
Counter
CBK
CT1
500
&
G5
C3
0.9V
S2
FBB
20ms
Blanking
Time
C4
4.5V
Figure 23
Control Unit
Basic and Extendable Blanking Mode
There are 2 kinds of Blanking mode; basic mode and the extendable mode. The basic mode is a built-in 20 ms
blanking time while the extendable mode can extend this blanking time by connecting an external capacitor to
the BBA pin. For the extendable mode, the gate G5 remains blocked even though the 20 ms blanking time is
reached. After reaching the 20 ms blanking time the counter is activated and the switch S1 is turned on to
charge the voltage of BBA pin by the constant current source, Ichg_EB. When the voltage of BBA pin hits 4.5 V,
which is sensed by comparator C11, the counter will increase the counter by 1. Then it switches off the switch
Data Sheet
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S1 and turns on the switch S2. The voltage at BBA pin will be discharged through a 500 Ω resistor. When the
voltage drops to 0.9 V which is sensed by comparator C3, the switch S2 will be turned off and the switch S1 will
be turned on. Then the constant current Ichg_EB will charge the CBK capacitor again. When the voltage at BBA hits
4.5 V which is sensed by comparator C11, the counter will increase the count to 2. The process repeats until it
reaches total count of 256 (Figure 24). Then the counter will release a high output signal. When the AND gate G5
detects both high signals at the inputs, it will activate the 30ms spike blanking circuit and finally the autorestart mode will be activated.
Figure 24
Waveform at extended blanking time
For example, if CBK=0.1 µF, Ichg_EB=720 mA
Extended blanking time = 256*(CBK*(4.5 V-0.9 V)/Ichg_EB + CBK*500*ln(4.5/0.9))
= 148.6 ms
Total blanking time = 20 ms+ 148.6 ms =168.6 ms
If there is a resistor RBO2 connected to BBA pin, the effective charging current will be reduced. The blanking time
will be increased.
For example, if CBK=0.1 µF, Ichg_EB=720 mA, RBO2=12.8 kΩ,
Ichg_EB’=Ichg_EB-(4.5 V+0.9 V)/(2*RBO2)=509 mA
Extended blanking time = 256*(CBK*(4.5 V-0.9 V)/Ichg_EB’ + CBK*500*ln(4.5/0.9))
= 201.6 ms
Total blanking time = 20 ms+201.6 ms = 221.6 ms
where Ichg_EB’=net charging current to CBK
Note: The above calculation does not include the effect of the brown out circuit where there is extra biasing current
flowing from the input. That means the extended blanking time will be shortened with the line voltage
change if brown out circuit is implemented.
3.7.2
Active Burst Mode (patented)
To increase the efficiency of the system at light load, the most effective way is to operate at burst mode.
Starting from CoolSET™ F3, the IC has been employing the active burst mode and it can achieve the lowest
standby power. ICE3AR4780JG adopts the same concept with some more innovative improvements to the
feature. It includes the adjustable entry burst level, close power control between high line and low line and the
smaller output ripple during burst mode.
Most of the burst mode design in the market will provide a fixed entry burst mode level which is a ratio to the
maximum power of the design. ICE3AR4780JG provides a more flexible level which can be selected externally.
The provision also includes not entering burst mode.
Data Sheet
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Propagation delay is the major contributor for the power control variation for DCM flyback converter. It is
proved to be effective in the maximum power control. ICE3AR4780JG also apply the same concept in the burst
mode. Therefore, the entry and exit burst mode power is also finely controlled during burst mode.
The feedback control swing during burst mode will affect the output ripple voltage directly. ICE3AR4780JG
reduces the swing from 0.5 V to 0.3 V. Therefore, it would have around 40% improvement for the output ripple.
Current Limiting
CS
Vcsth_burst
C12
G10 & FF1
Internal
Bias
Burst detect
and adjust
VFB_burst
20 ms Blanking
Time
C5
FBB
CFB
Active Burst
Mode
C13
4.0V
3.5V
C6a
&
G11
C6b
3.2V
Figure 25
Control Unit
Active Burst Mode
3.7.2.1
Selectable burst entry level
The burst mode entry level can be selected by changing the different capacitor CFB at FBB pin. There are 4 levels
to be selected with different capacitor which are targeted for 10%, 6.67%, 4.38% and 0% of the maximum input
power. At the same time, the exit burst levels are targeted to 20%, 13.3%, 9.6% and 0% of the maximum power
accordingly. The corresponding capacitance range is from 6.8 nF to 100 pF. The below table is the
recommended capacitance range for the entry and exit level with the CFB capacitor.
Table 2
CFB versus active burst mode entry/exit level
CFB
Entry level
Exit level
% of Pin_max
VFB_burst
% of Pin_max
Vcsth_burst
≥ 6.8 nF (5%, X7R)
10%
1.60 V
20%
0.45 V
1nF~2.2 nF (1%, COG)
6.67%
1.42 V
13.3%
0.37 V
220pF~470 pF (1%, COG)
4.38%
1.27 V
9.6%
0.31 V
≤ 100 pF (1%, COG)
0%
never
0%
always
The selection is at the 1st 1ms of the UVLO “ON” (VVCC > 17 V) during the 1st start up but it does not detect in the
subsequent re-start due to auto-restart protection. In case there is protection triggered such as brown out
before starts up, the detection will be held until the protection is removed. When the Vcc reaches the UVLO
“ON” in the 1st start up, the capacitor CFB at FBB pin is charged by a 5V voltage source through the RFB
resistor. When the voltage at FBB pin hits 4.5 V, the FF4 will be set, the switch S9 is turned “ON” and the counter
will increase by 1. Then the CFB is discharged through a 500 Ω resistor. After reaching 0.5 V, the FF4 is reset and
the switch S9 is turned “OFF”. Then the CFB capacitor is charged by the 5V voltage source again until it reaches
4.5 V. The process repeats until the end of 1 ms. Then the detection is ended. After that, the total number of
count in the counter is compared and the VFB-burst and the Vcs_burst are selected accordingly (Figure 26)
Data Sheet
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VFB_burst
VCSth_burst
5V
Comparator
logic
counter
UVLO
RFB
4.5V
FBB
C19
S
Q
FF4
CFB
500
S9
0.5V
UVLO during
1st startup
C20
R
1ms
timer
Control Unit
Figure 26
3.7.2.2
Active Burst Mode
Entering Active Burst Mode
The FBB signal is kept monitoring by the comparator C5 (Figure 25). During normal operation, the internal
blanking time counter is reset to 0. When FBB signal falls below VFB_burst, it starts to count. When the counter
reaches 20 ms and FBB signal is still below VFB_burst, the system enters the Active Burst Mode. This time window
prevents a sudden entering into the Active Burst Mode due to large load jumps.
After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the
current consumption of the IC to about 620 µA.
It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5 V such that
the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The
minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest
VCC level is reached at no load condition.
3.7.2.3
Working in Active Burst Mode
After entering the Active Burst Mode, the FBB voltage rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors the FBB signal. If the voltage level is larger than 3.5 V, the
internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the current limit is reduced to Vcsth_burst (Figure 3 and Figure 25).
In one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at
VOUT is still kept unchanged, the FBB signal will drop to 3.2 V. At this level the C6b deactivates the internal
circuit again by switching off the Internal Bias. The gate G11 is active again as the burst flag is set after entering
Active Burst Mode. In Active Burst Mode, the FBB voltage is changing like a saw tooth between 3.2 V and 3.5 V
(Figure 27).
3.7.2.4
Leaving Active Burst Mode
The FBB voltage will increase immediately if there is a high load jump. This is observed by the comparator C13
(Figure 25). Since the current limit is reduced to 31%~45% of the maximum current during active burst mode, it
needs a certain load jump to raise the FBB signal to exceed 4.0 V. At that time the comparator C5 resets the
Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can
then be resumed to stabilize VOUT.
Data Sheet
18
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
VFBB
Entering
Active Burst
Mode
4.0V
3.5V
3.2V
Leaving Active
Burst Mode
VFB_burst
Blanking Timer
t
20ms Blanking Time
VCS
t
Current limit level during
Active Burst Mode
Vcsth
Vcsth_burst
VVCC
t
10.5V
IVCC
t
5.7mA
620uA
VOUT
t
t
Figure 27
3.7.3
Signals in Active Burst Mode
Protection Modes
The IC provides Auto Restart mode as the major protection feature. Auto Restart mode can prevent the SMPS
from destructive states. There are four kinds of auto restart mode; auto restart mode, non switch auto restart
mode, odd skip auto restart mode and odd skip non switch auto restart mode.
VVCC
Fault
detected
Startup and detect
17V
10.5V
VCS
t
t
Figure 28
Data Sheet
Auto restart waveform
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
VVCC
Fault
detected
Startup and detect
17V
10.5V
VCS
t
No switching
t
Figure 29
Non switch auto restart waveform
The main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto
restart protection can be reduced. This feature is particularly good for smaller VCC capacitor where the restart
time is shorter. There is no detecting of fault and no switching pulse for the odd number restart cycle. At the
even number of restart cycle the fault detect and soft start switching pulses maintained. If the fault persists, it
would continue the auto-restart mode. However, if the fault is removed, it can release to normal operation only
at the even number auto restart cycle (Figure 29).
VVCC
Fault
detected
Startup and detect
No detect
No detect
17V
10.5V
VCS
t
t
Figure 30
Odd skip auto restart waveform
Odd skip non switch auto restart mode is similar to odd skip auto restart mode except the start up switching
pulses are also suppressed at the even number of the restart cycle. The detection of fault still remains at the
even number of the restart cycle. When the fault is removed, the IC will resume to normal operation at the even
number of the restart cycle (Figure 30).
VVCC
Fault
detected
Startup and detect
No detect
No detect
17V
10.5V
VCS
t
No switching
t
Figure 31
Data Sheet
Odd skip non switch auto restart waveform
20
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The following table list down the protection modes of the CoolSET™.
Table 3
Protection functions
Protection function
Failure condition
Protection Mode
VCC Overvoltage
1. VCC > 20.5 V and FB > 4.5 V &
during soft start period
2. VCC > 25.5 V
Odd skip Auto Restart
Overtemperature
(controller junction)
TJ > 130°C
Odd skip Auto Restart
Overload / Open loop
VFBB > 4.5 V, last for 20 ms and
extended blanking time
(extended blanking time counted
as 256 times of VBBA charging and
discharging from 0.9 V to 4.5V )
Odd skip Auto Restart
Vcc Undervoltage / Short
Optocoupler
VCC < 10.5 V
Auto Restart
Overtemperature
(controller junction)
TJ > 130°C
Odd skip non switch Auto Restart
External protection enable
VAE < 0.4 V
Non switch Auto Restart
Brownout
VBO_ref < 0.9 V and last for 30 ~ 60 µs
Non switch Auto Restart
3.7.3.1
VCC OVP, OTP and VCC under voltage
Auto Restart
Mode Reset
VVCC < 10.5V
Thermal Shutdown
Tj >130°C
25.5V
C2
120μs blanking
time
Spike
Blanking
30μs
Auto Restart
mode
VCC
C1
20.5V
4.5V
C4
&
Voltage
Reference
G1
Control Unit
FBB
softs_period
Figure 32
Vcc OVP and OTP
There are 2 types of VCC over voltage protection; VCC OVP (1) and VCC OVP (2). The VCC OVP (1) takes action
only during the soft start period. The VCC OVP (2) takes the action in any conditions.
VCC OVP (1) condition is when VVCC voltage is > 20.5 V, VFBB voltage is > 4.5 V and during soft start period, the IC
enters into odd skip Auto Restart Mode. This condition likely happens during start up at open loop fault (Figure
30).
Vcc OVP (2) condition is when VVCC voltage is > 25.5V, the IC enters into odd skip Auto Restart Mode (Figure 30).
The over temperature protection OTP is sensed inside the controller IC. The Thermal Shutdown block keeps on
monitoring the junction temperature of the controller. After detecting a junction temperature higher than
Data Sheet
21
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
130°C, the IC will enter into the odd skip non switch Auto Restart mode. The ICE3AR4780JG has also
implemented with a 50°C hysteresis. That means the IC can only be recovered when the controller junction
temperature is dropped 50°C lower than the over temperature trigger point (Figure 31).
The VCC undervoltage and short opto-coupler will go into the normal auto restart mode inherently.
In case of VCC undervoltage, the Vcc voltage drops indefinitely. When it drops below the Vcc under voltage lock
out “OFF” voltage (10.5 V), the IC will turn off the IC and the startup cell will turn on again. Then the Vcc voltage
will be charged up to UVLO “ON” voltage (17 V) and the IC turns on again provided the startup cell charge up
current is not drained by the fault. If the fault is not removed, the Vcc will continue to drop until it hits UVLO
“OFF” voltage and the restart cycle repeats.
Short Optocoupler can lead to VCC undervoltage because once the opto-coupler (transistor side) is shorted, the
feedback voltage will drop to zero and there will be no switching pulse. Then the VCC voltage will drop same as
the VCC undervoltage.
3.7.3.2
Over load, open loop protection
Voltage
Reference
5.0V
Auto Restart
Mode Reset
VVCC < 10.5V
Ichg_EB
Auto
Restart
Mode
S1
ROV2 CBK
#
BV
4.5V
C11
counter
500
0.9V
C3
CT1
Spike
Blanking
30us
&
G5
S2
FBB
20ms
Blanking
Time
C4
4.5V
Figure 33
Control Unit
Over load, open loop protection
In case of Overload or Open Loop, the VFBB voltage exceeds 4.5 V which will be observed by comparator C4. Then
the built-in blanking time counter starts to count. When it reaches 20 ms, the extended blanking time counter
CT1 is activated. The switch S2 is turned on and the voltage at the BBA pin will be discharged through 500 Ω
resistor. When it drops to 0.9 V, the switch S2 is turned off and the Switch S1 is turned on. Then a constant
current source Ichg_EB will start to charge up BBA pin. When the voltage hits 4.5 V which is monitored by
comparator C11, the switch S1 is turned off and the count will increase by 1. Then the switch S2 will turn on
again and the voltage will drop to 0.9 V and rise to 4.5 V again. The count will then increase by 1 again. When the
total count reaches 256, the counter CT1 will stop and it will release a high output signal. When both the input
signals at AND gate G5 is high, the odd skip Auto Restart Mode is activated after the 30 µs spike blanking time
(Figure 30).
The total blanking time depends on the addition of the built-in and the extended blanking time. If there is no
CBK capacitor at BBA pin, the count will finish within 0.1 ms and the equivalent blanking time is just the built-in
time of 20 ms. However, if the CBK capacitor is big enough, it can be as long as 1 s. If CBK is 0.1 µF and Ichg_EB is 720
µA, the extendable blanking time is around 148.6 ms and the total blanking time is 168.6 ms.
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
Since the BBA pin is a multi-function pin, it would share with different functions. The resistor RBO2 from
brownout feature application may however affect the extendable blanking time (Figure 33). Thus it should take
the RBO2 into the calculation of the extendable blanking time. For example the extended blanking time would be
changed (159.6~191.2 ms) with different resistance values of RBO2 resistor. Table 4 shows some examples of CBK,
RBO2 vs blanking time.
Table 4
Blanking time vs CBK and RBO2
CBK
RBO2
Extended blanking time
Overall blanking time
0.1 µF
15 kΩ
191.2 ms
211.2 ms
0.1 µF
37.5 kΩ
162.8 ms
182.8 ms
0.1 µF
47 kΩ
159.6 ms
179.6 ms
Note:
3.7.4
RBO2 must be always ≥15 kΩ in enable brownout mode, otherwise overload protection may not work.
Brown out Mode
When the AC input voltage is removed, the voltage at the bulk capacitor will fall. When it reaches a point that
the system is greater than the system allowed maximum power, the system may go into over load protection.
However, this kind of protection is not welcome for some of the applications such as auxiliary power for
PC/server system because the output is in hiccup mode due to over load protection (auto restart mode). The
brownout mode is to eliminate this phenomenon. The IC will sense the input voltage through the bulk
capacitor to the BBA pin by 2 potential divider resistors, RBO1 and RBO2 (Figure 34).
When the system is powered up, the bulk capacitor and the Vcc capacitor are charged up at the same time.
When the VCC voltage is charged to > 7 V, the brownout circuit starts to operate (Figure 34). Since the UVLO is
still at low level as the VCC voltage does not reach the 17 V UVLO “ON” voltage. The NAND gate G20 will release
a low signal to the flip flop FF5 and the negative output of FF5 will release a high signal to turn on the switch S3.
The constant load LD6 will start to draw constant current Ichg_BO from the BBA pin. That means the brownout
mode is default “ON” during the system starts up.
Vbulk
5µs
blanking
time
RBO1
Brownout
mode
G21
BBA
S
C14
30µs~60µs
blanking time
0.9V
RBO2
Q
R
FF5
G22
G20
UVLO
S3
LD6
Ichg_BO
Figure 34
Control Unit
Brown out detection circuit
Once the system enters the brown out mode, there will be no switching pulse and the IC keeps on monitoring
the BV signal. If the brown out signal is not reset, there is no switching pulse in each restart cycle (Figure 35).
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
VVCC
Fault
detected
Startup and detect
17V
10.5V
VCS
t
No switching
t
Figure 35
Brown out mode waveform
The voltage at bulk capacitor Vbulk continues to increase and so is the voltage at BBA. When the BBA voltage
reaches 0.9 V, the output of OPAMP C14 will become low. Through the inverter gate G21, the “S” input of the flip
flop FF5 is changed to high. Then the negative output of FF5 is low. The brownout mode is then “OFF” and the
constant current load LD6 is also “OFF” through the turn-off of the S3. The system will turn on with soft start in
the coming restart cycle when Vcc reaches the Vcc “ON” voltage 17 V.
When there is an input voltage drop, the BBA voltage also drops. When the voltage at BBA pin falls below 0.9 V,
the output of OPAMP C14 is changed to high. The inverter gate G22 will change the high input to low output.
Then the NAND gate G22 will have a high output. The negative output of the flip flop FF5 is then become high.
The constant load LD6 is “ON” again and the IC enters the brownout mode where the Vcc swings between 10.5
V and 17 V without any switching pulse.
The formula to calculate the RBO1 and RBO2 are as below.
RBO1=Vhys/Ichg_BO
RBO2=Vref_BO*RBO1/(VBO_l -Vref_BO)
where VBO_l: input brownout voltage (low point); Vhys: input brownout hysteresis voltage; Vref_BO: IC reference
voltage for brownout; RBO1 and RBO2: resistors divider from input voltage to BBA pin
For example,
Ichg_BO=10 µA, Vref_BO=0.9 V,
Case 1:
if brownout voltage is 70 VACon and 100 VAC off,
then brownout voltage, VBO_l=100 VDC,
hysteresis voltage, VBO_hys=43 VDC,
RBO1=4.3 MΩ, RBO2=39 kΩ
Case 2:
if brownout voltage is 100 VAC on and 120 VAC off,
then brownout voltage, VBO_l=141 VDC,
hysteresis voltage, VBO_hys=28 VDC,
RBO1=2.8 MΩ, RBO2=18 kΩ
Case 3:
if brownout voltage is 120 VAC on and 160 VAC off,
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
then brownout voltage, VBO_l=169 VDC,
hysteresis voltage, VBO_hys=56 VDC,
RBO1=5.6 MΩ, RBO2=30 kΩ
The summary is listed below.
Table 5
Brownout resistors vs VBO_hys
Case
VBO_l
VBO_h
VBO_hys
RBO1
RBO2
1
100V
143V
43V
4.3MΩ
39KΩ
2
141V
169V
28V
2.8MΩ
18KΩ
3
169V
225V
56V
5.6MΩ
30KΩ
Note:
The above calculation assumes the tapping point (bulk capacitor) has a stable voltage with no ripple
voltage. If there is ripple in the input voltage, it should take the highest voltage for the calculation;
VBO_l + ripple voltage. Besides that the low side brownout voltage VBO_l added with the ripple voltage at
the tapping point should always be lower than the high side brownout voltage (VBO_h); VBO_h > VBO_l +
ripple voltage. Otherwise, the brownout feature cannot work properly. In short, when there is a high
load running in system before entering brownout, the input ripple voltage will increase and the
brownout voltage will increase (VBO_l = VBO_l + ripple voltage) at the same time. If the VBO_hys is set too
small and is close to the ripple voltage, then the brownout feature cannot work properly (VBO_l = VBO_h).
If the brownout feature is not needed, it needs to tie the BBA pin to the Vcc pin through a current limiting
resistor, 500 kΩ~1 MΩ. The BBA pin cannot be in floating condition. If the brownout feature is disabled with a
tie up resistor, there is a limitation of the capacitor CBK at the BBA pin. It is as below.
Table 6
VCC tie up resistor and CBK_max
VCC tie up resistor
CBK_max
1
500 kΩ
0.47 uF
2
1 MΩ
0.22 uF
3.7.5
Action sequence at BBA pin
Since there are 3 functions at the same BBA pin; brownout, extended blanking time and the auto-restart
enable, the actions of sequence are set as per the below table in case of several features happens
simultaneously.
Table 7
2
Action sequence at BBA pin
nd
1st
Auto-restart enable
Extended blanking time
Brownout
Auto-restart enable
Auto-restart enable
Auto-restart enable
Brownout
Extended blanking time
Auto-restart enable
Extended blanking time
Brownout
Brownout
Auto-restart enable
Extended blanking time
Brownout
The top row of the table is the first happened feature and the left column is the second happened feature. For
example,
Case 1:
Data Sheet
25
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The “Auto-restart enable” feature happened first and it follows with the “Extended blanking time” feature.
Then the “Auto-restart enable” feature will continue to hold and the “Extended blanking time” feature is
ignored.
Case 2:
The “Extended blanking time” feature happened first and it follows with the “Auto-restart enable” feature.
Then the “Auto-restart enable” feature will take the priority and the “Extended blanking time” feature is
overridden.
Case 3:
The “Extended blanking time” feature happened first and it follows with the “Brownout” feature. Then the
“Extended blanking time” feature will continue to work until it ends. After that if the over load fault is removed
the “Brownout” feature takes the action.
Case 4:
The “Brownout” feature happened first and it follows with the “Auto-restart enable” feature. Then the
“Brownout” feature will continue to work and the “Auto-restart enable” feature is ignored.
One typical case happened is that the “Extended blanking time” feature happened first and it follows with the
“Brownout” feature. If, however, the over load fault is removed before the end of the extended blanking time,
the “Brownout” feature can take action only after 20 ms buffer time.
Data Sheet
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4
Note:
4.1
Note:
Table 8
Electrical Characteristics
All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other ratings
are not violated.
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to
destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be
connected to pin 11 (VCC) is discharged before assembling the application circuit. Ta=25°C unless
otherwise specified.
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Drain Source Voltage
VDS
-
800
V
Pulse drain current, tp limited by Tjmax
ID_Puls
-
1.95
A
Avalanche energy, repetitive tAR limited EAR
by max. Tj=150°C1
Avalanche current, repetitive tAR limited IAR
by max. Tj=150°C
VCC Supply Voltage
VVCC
-
FBB Voltage
0.024
Remarks
mJ
-
0.95
A
-0.3
27
V
VFBB
-0.3
5.5
V
BV Voltage
VBV
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
V
Junction Temperature
Tj
-40
150
°
Storage Temperature
TS
-55
150
°
Thermal Resistance
(Junction–Ambient)
RthJA
-
110
K/W
Soldering temperature, wavesoldering
only allowed at leads
ESD Capability (incl. Drain Pin)
Tsold
-
260
°
VESD
-
2
kV
C
Controller & CoolMOS™
C
C
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5 kΩ series resistor)
Data Sheet
27
1.6mm (0.063in.) from case
for 10s
Human body model2
1
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4.2
Note:
Table 9
Absolute Maximum Ratings
Within the operating range the IC operates as described in the functional description.
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
Max value limited due to
VVCCOVP
VCC Supply Voltage
VVCC
VVCCoff
25
V
Junction Temperature of Controller
TjCon
-40
130
°
Junction Temperature of CoolMOS™
TjCoolMOS
-40
150
°
4.3
Characteristics
4.3.1
Supply Section
Note:
Table 10
Max value limited due to
thermal shut down of
controller
C
C
The electrical characteristics involve the spread of values within the specified supply voltage and
junction temperature range TJ from – 40 °C to 125 °C. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 17 V is assumed.
Supply Section
Parameter
Symbol Limit Values
Unit
Test Condition
min.
typ.
max.
-
200
300
μA
VVCC =16V
Start Up Current
IVCCstart
VCC Charge Current
IVCCcharge1 -
-
5.0
mA
VVCC = 0V
IVCCcharge2 0.55
0.9
1.60
mA
VVCC = 1V
IVCCcharge3 0.38
0.7
-
mA
VVCC =16V
Leakage Current of
Start Up Cell and CoolMOS™
IStartLeak
-
0.2
50
μA
VDrain = 650V at Tj=100°C1
Supply Current with Inactive Gate
IVCCsup1
-
1.9
3.2
mA
Supply Current with Active Gate
IVCCsup2
-
3.0
4.4
mA
IFBB = 0A
Supply Current in
Auto Restart Mode with Inactive Gate
IVCCrestart
-
320
-
μA
IFBB = 0A
Supply Current in Active Burst Mode
with Inactive Gate
IVCCburst1
-
620
950
μA
VFBB = 2.5V
IVCCburst2
-
620
950
μA
VVCC = 11.5V, VFBB = 2.5V
VCC Turn-On ThresholdVCC Turn-Off
Threshold VCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
16.0
9.8
-
17.0
10.5
6.5
18.0
11.2
-
V
V
V
The parameter is not subjected to production test - verified by design/characterization
Data Sheet
28
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
4.3.2
Table 11
Internal Voltage Reference
Internal Voltage Reference
Parameter
Symbol Limit Values
Trimmed Reference Voltage
4.3.3
Table 12
VREF
min.
typ.
max.
4.90
5.00
5.10
Unit
Test Condition
V
measured at pin FBB
IFBB = 0
Unit
Test Condition
PWM Section
PWM Section
Parameter
Symbol
Limit Values
min.
typ.
max.
fOSC1
87
100
113
kHz
fOSC2
90
100
108
kHz
Tj = 25°C
Frequency Jittering Range
fjitter
-
±4.0
-
kHz
Tj = 25°C
Frequency Jittering period
Tjitter
-
4.0
-
ms
Tj = 25°C
Max. Duty Cycle
Dmax
0.70
0.75
0.80
Min. Duty Cycle
Dmin
0
-
-
PWM-OP Gain
AV
3.05
3.25
3.45
Voltage Ramp Offset
VOffset-Ramp
-
0.60
-
V
VFBB Operating Range Min Level
VFBmin
-
0.7
-
V
VFBB Operating Range Max level
VFBmax
-
-
4.3
V
FBB Pull-Up Resistor
RFB
9.0
15.4
23.0
kΩ
Fixed Oscillator Frequency
4.3.4
Table 13
Parameter
Soft Start time
VFBB < 0.3 V
CS=1 V, limited by
Comparator C41
Soft Start time
Soft Start time
Symbol Limit Values
tSS
Unit
min.
typ.
max.
-
10
-
The parameter is not subjected to production test - verified by design/characterization
Data Sheet
29
Test Condition
ms
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
4.3.5
Table 14
Control Unit
Control Unit
Parameter
Symbol Limit Values
Unit
min.
typ.
max.
Test Condition
Brown out reference voltage for
comparator C14
Blanking time voltage lower limit for
Comparator C3
Blanking time voltage upper limit for
Comparator C11
Over Load Limit for Comparator C4
VBO_ref
0.8
0.9
1.0
V
VBKC3
0.80
0.90
1.00
V
VBKC11
4.28
4.50
4.72
V
VFBC4
4.28
4.50
4.72
V
Entry Burst select High level for
Comparator C19
Entry Burst select Low level for
Comparator C20
Active Burst Mode
10% Pin_max
Entry Level for
6.67%
Comparator C5
Pin_max
4.38%
Active Burst Mode HighPin_max
Level for
VFBC19
4.28
4.50
4.72
V
VFBC20
0.40
0.50
0.60
V
VFB_burst1 1.51
1.60
1.69
V
< 7 counts
VFB_burst2 1.34
1.42
1.50
V
8 ~ 39 counts
VFB_burst3 1.20
1.27
1.34
V
40 ~ 191 counts
VFBC6a
3.35
3.50
3.65
V
In Active Burst Mode
VFBC6b
3.06
3.20
3.34
V
VFBC13
3.85
4.00
4.15
V
VVCCOVP1
19.5
20.5
21.5
V
VVCCOVP2
25.0
25.5
26.3
V
VAE
0.25
0.40
0.45
V
Ichg_EB
460
720
864
μA
Ichg_BO
9.0
10.0
10.08
μA
Thermal Shutdown
TjSD
130
140
150
°
Hysteresis for thermal Shutdown1
TjSD_hys
-
50
-
°
Built-in Blanking Time for Overload
Protection or enter Active Burst Mode
Timer for entry burst select
tBK
-
20
-
ms
tEBS
-
1
-
ms
Spike Blanking Time for Auto-Restart
Protection
tSpike
-
30
-
μs
Comparator C6a
Active Burst Mode Low Level for
Comparator C6b
Active Burst Mode Level for
Comparator C13
Overvoltage Detection Limit for
Comparator C1
Overvoltage Detection Limit for
Comparator C2
Auto-restart enable reference voltage
for Comparator C9
Charging current for extended
blanking time
Charging current for brownout
1
Note:
C
VFBB = 5V, during soft start
Controller
C
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
and VVCCPD
The parameter is not subject to production test - verified by design/characterization. The thermal shutdown temperature refers to the
junction temperature of the controller.
1
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
4.3.6
Table 15
Current Limiting
Current Limiting
Parameter
Symbol Limit Values
min.
typ.
max.
Unit
Test Condition
Peak Current Limitation (incl.
Propagation Delay)
Vcsth
0.98
1.06
1.13
V
dVsense / dt = 0.6V/µs
(Figure 21)
Peak Current
Limitation during
Active Burst Mode
20% Pin_max
Vcsth_burst1 0.37
0.45
0.51
V
< 7 counts
13.3%
Pin_max
9.6% Pin_max
Vcsth_burst2 0.30
0.37
0.44
V
8 ~ 39 counts
Vcsth_burst3 0.23
0.31
0.37
V
40 ~ 191 counts
Leading Edge
Blanking
Normal mode
tLEB_normal -
220
-
ns
Burst mode
tLEB_burst
-
180
-
ns
ICSbias
-1.5
-0.2
-
μA
CS Input Bias Current
4.3.7
Table 16
VCS =0V
CoolMOS™ Section
CoolMOS™ Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Drain Source Breakdown Voltage
V(BR)DSS
800
870
-
-
V
V
Tj = 25°C
Tj = 110°C1
Drain Source On-Resistance
RDSon
-
4.70
10.45
12.76
5.18
11.50
14.04
Ω
Ω
Ω
Tj = 25°C
Tj=125°C1
Tj=150°C1 at ID = 0.58 A
Effective output capacitance,
energy related
Co(er)
-
7.2
-
pF
VDS = 0 V to 480 V
Rise Time2
trise
-
-
ns
Fall Time2
tfall
-
-
ns
30
30
1
The parameter is not subjected to production test - verified by design/characterization
2
Measured in a Typical Flyback Converter Application
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
5
CoolMOS™ Performance Characteristics
Figure 36
Safe Operating Area (SOA) curve for ICE3AR4780JG
Figure 37
SOA temperature derating coefficient curve
Data Sheet
32
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
Figure 38
Power dissipation; Ptot=f(Ta)
Figure 39
Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
6
Input Power Curve
Two input power curves giving the typical input power versus ambient temperature are showed below; VIN=85
VAC~265 VAC (Figure 40) and VIN=230 VAC +/-15% (Figure 41). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% maximum duty ratio or 100 V maximum
secondary to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink
for the device. The input power already includes the power loss at input common mode choke, bridge rectifier
and the CoolMOS™.The device saturation current (ID_Puls @ Tj=125°C) is also considered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating
ambient temperature with the estimated efficiency for the application. For example, a wide range input voltage
(Figure 41), operating temperature is 50°C, estimated efficiency is 85%, then the estimated output power is
16.15 W (19 W * 85%).
Figure 40
Input power curve VIN=85~265 VAC; Pin=f(Ta)
Figure 41
Input power curve VIN=230 VAC; Pin=f(Ta)
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
7
Figure 42
Data Sheet
Outline Dimension
PG-DSO-12 (Pb-free lead plating Plastic Dual-in-Line Outline)
35
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
8
Figure 43
Data Sheet
Marking
Marking for ICE3AR4780JG
36
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
9
Schematic for recommended PCB layout
Figure 44
Marking for ICE3AR4780JG
General guideline for PCB layout design using F3 CoolSET™ (Figure 44):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET™
device effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET™ device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of
IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400 V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0 mm
b. 600 V traces (drain voltage of CoolSET™ IC11) to nearby trace: > 2.5 mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller
pin as possible so as to reduce the switching noise coupled into the controller.
Guideline for PCB layout design when > 3 kV lightning surge test applied (Figure 44):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
Data Sheet
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Fixed-Frequency, 800V CoolSET™ in DS0-12 Package
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5 mm (no safety
concern)
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:
These 2 Spark Gaps can be used when the lightning surge requirement is > 6 kV.
230 VAC input voltage application, the gap separation is around 5.5mm
115 VAC input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET™
and reduce the abnormal behavior of the CoolSET™. The diode can be a fast speed diode such as 1N4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing
through the sensitive components such as the primary controller, IC11.
Revision History
Major changes since the last revision
Page or Reference
1, 36
Data Sheet
Description of change
change marking
38
Revision 1.1
2017-06-13
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBlade™, EasyPIM™,
EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, Infineon™, ISOFACE™, IsoPACK™,
i-Wafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Trademarks updated August 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2017-06-13
Published by
Infineon Technologies AG
81726 München, Germany
ifx1owners.
© 2017 Infineon Technologies AG.
All Rights Reserved.
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