ICE3AS03LJG

V er s io n 2.0 , 3 J ul 2 00 9 F3 PWM controller ICE3AS03LJG Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell ( Latched and frequency jitter Mode ) Power Management & Supply N e v e r s t o p t h i n k i n g . F3 PWM controller ICE3AS03LJG Revision History: 2009-7-3 Datasheet Previous Version: 0.4 Page 5, 7,12, 13, Subjects (major changes since last revision) Typo error 6, 14, 16, 17, 21 Revise spike blanking time to 25us For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com Edition 2009-7-3 Published by Infineon Technologies AG, 81726 Munich, Germany, © 2008 Infineon Technologies AG. All Rights Reserved. Legal disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. F3 PWM controller ICE3AS03LJG Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell ( Latched and frequency jitter Mode ) Product Highlights • • • • • Active Burst Mode to reach the lowest Standby Power Requirements < 100mW Built-in latched Off protection Mode and external latch enable function to increase robustness of the system Built-in and extendable blanking Window for high load jumps to increase system reliability Frequency jitter for low EMI Pb-free lead plating; RoHS compilant PG-DSO-8 P-DSO-8-3, -6 Features Description • • • • • The ICE3AS03LJG is the latest version of the F3 controller for lowest standby power and low EMI features with both auto-restart and latch off protection features to enhance the system robustness. It targets for off-Line battery adapters, and low cost SMPS for low to medium power range such as application for the DVD R/W, DVD Combi, Blue Ray DVD player and recorder, set top box, charger, note book adapter, etc. The inherited outstanding features includes 500V startup cell, active burst mode (achieve the lowest standby power; i.e. 130°C 20ms Blanking Time 20ms Blanking Time 1 G2 1 G3 & G6 Spike Blanking 25us Thermal Shutdown 120us Blanking Time Spike Blanking 25us 2 ms counter & G11 Active Burst Mode Auto Restart Mode Soft Start Block Latch off Mode Latched off Mode Reset VVCC < 6.23V Power-Down Reset Internal Bias Power Management 18V 5.0V & G7 Current Mode x3.3 C8 PWM Comparator PWM OP 0.67V C7 Soft Start Soft-Start Comparator 10.5V Undervoltage Lockout Voltage Reference HV & G10 C12 C10 Propagation-Delay Compensation 1.66V FF1 S R Q PWM Section VCC 0.25V 1pF & G9 Gate Driver D1 10kΩ CVCC Current Limiting Vcsth Leading Edge Blanking 220ns C11 1 G8 0.75 Startup Cell Spike Blanking 190ns Freq. jitter Clock Duty Cycle max Oscillator # : optional external components; #1 : CBK is used to extend the Blanking Time #2 : TAE is used to enable the external Latch off feature ICE3AS03LJ-F3 PWM controller ( Latch and Jitter Mode ) Control Unit 2pF 25kΩ RFB 5.0V S1 0.9V IBK 3.25kΩ CBulk CS Gate GND RSense Snubber + 2 Converter DC Output VOUT - F3 PWM controller ICE3AS03LJG Representative Blockdiagram Representative Blockdiagram Representative Blockdiagram 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description 3 Functional Description components are necessary to adjust the blanking window. In order to increase the robustness and safety of the system, the IC provides 2 levels of protection modes: Latched Off Mode and Auto Restart Mode. The Latched Off Mode is only entered under dangerous conditions which can damage the SMPS if not switched off immediately. A restart of the system can only be done by recycling the AC line. In addition, for this enhanced version, there is an external Latch Enable function provided to increase the flexibility in protection. When the BL pin is pulled down to less than 0.33V, the Latch Off Mode is triggered. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically retained after the next Start Up Phase. The internal precise peak current control reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the maximum power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage, which is required for wide range SMPS. Thus there is no need for the over-sizing of the SMPS, e.g. the transformer and the output diode. Furthermore, this enhanced version implements the frequency jitter mode to the switching clock and modulated gate drive signal at the Gate pin such that the EMI noise will be effectively reduced. All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. 3.1 Introduction ICE3AS03LJG is an enhanced version of the F3 PWM controller (ICE3xS02) for the low to medium power application. The particular enhanced features are the built-in features for soft start, blanking window and frequency jitter. It also provides the flexibility to increase the blanking window by simply adding capacitor in BL pin. To increase the robustness and flexibility of the protection feature, an external latch-off enable feature is added. Moreover, the proven outstanding features in F3 PWM controller are still remained such as the active burst mode, propagation delay compensation, modulated gate drive, protection for Vcc overvoltage, over temperature, short winding, short diode, over load, open loop, Vcc undervoltage and short optocoupler. The intelligent Active Burst Mode at Standby Mode can effective obtain the lowest Standby Power at minimum load and no load conditions. After entering this burst mode, there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is on well controlled in this mode. The usual externally connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore, a high voltage Startup Cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 18V is exceeded. The external startup resistor is no longer necessary as this Startup Cell can directly connected to the input bulk capacitor. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. Adopting the BiCMOS technology, it can further decrease the power consumption and provide a even better standby input power. Besides, it also increases the design flexibility as the Vcc voltage range is extended to 25V. The built-in soft start time at 10ms can provide sufficient timing to reduce the over-stress at power MOSFET and the output rectifier during startup. There are 2 modes of blanking time for high load jumps; the basic mode and the extendable mode. The blanking time for the basic mode is set at 20ms while the extendable mode will increase the blanking time at basic mode by adding external capacitor at the BL pin. During this time window the overload detection is disabled. With this concept no further external Version 2.0 3.2 Power Management The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line, the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current is controlled to 0.9mA by the Startup Cell. When the VVCC exceeds the on-threshold VCCon=18V, the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on a hysteresis start up voltage is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 10.5V. The maximum current consumption before the controller is activated is about 250µA. When VVCC falls below the off-threshold VCCoff=10.5V, the bias circuit switched off and the soft start counter is 7 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description 3.3 reset. Thus it is ensured that at every startup cycle the soft start starts at zero. HV Improved Current Mode Soft-Start Comparator VCC Startup Cell PWM-Latch FB C8 R Q Driver S Power Management Internal Bias Latched Off Mode Reset V VCC < 6.23V Power-Down Reset Q 0.67V Undervoltage Lockout 18V PWM OP 10.5V Voltage Reference x3.3 5.0V CS Improved Current Mode Auto Restart Mode Soft Start block Active Burst Mode Figure 4 Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FB signal with the amplified current sense signal. Latched Off Mode Figure 3 Current Mode Power Management Amplified Current Signal The internal bias circuit is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 250µA. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require re-cycling the AC line. In case Latched Off Mode is entered, VCC needs to be dropped below 6.23V to reset the Latched Off Mode. This is done usually by re-cycling the AC line. When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference is kept alive in order to reduce the current consumption below 450µA. FB 0.67V Driver t ton t Figure 5 Pulse Width Modulation In case the amplified current sense signal exceeds the FB signal, the on-time ton of the driver is finished by resetting the PWM-Latch (see Figure 5). The primary current is sensed by the external series resistor RSense inserted in the source of the external power MOSFET. By means of Current Mode regulation, the secondary output voltage is insensitive Version 2.0 8 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle. The external RSense allows an individual adjustment of the maximum source current of the external power MOSFET. To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start. In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the Voltage Ramp is a well defined signal for the comparison with the FB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it reaches approximately 156ns delay time (see Figure 7). It allows the duty cycle to be reduced continuously till 0% by decreasing VFB below that threshold. VOSC max. Duty Cycle t Voltage Ramp 0.67V FB t Gate Driver 156ns time delay t Soft-Start Comparator Figure 7 PWM Comparator FB 3.3.1 PWM-Latch VOSC time delay circuit (156ns) 10kΩ R1 T2 Gate Driver 0.67V 3.3.2 X3.3 V1 C1 PWM OP Improved Current Mode Version 2.0 PWM-Comparator The PWM-Comparator compares the sensed current signal of the external power MOSFET with the feedback signal VFB (see Figure 8). VFB is created by an external optocoupler or external transistor in combination with the internal pull-up resistor RFB and provides the load information of the feedback circuitry. When the amplified current signal of the external power MOSFET exceeds the signal VFB the PWMComparator switches off the Gate Driver. Voltage Ramp Figure 6 PWM-OP The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor RSense connected to pin CS. RSense converts the source current into a sense voltage. The sense voltage is amplified with a gain of 3.3 by PWM OP. The output of the PWM-OP is connected to the voltage source V1. The voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWMComparator C8 and the Soft-Start-Comparator (see Figure 6). C8 Oscillator Light Load Conditions 9 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description is a built-in function and it is controlled by an internal counter. 5V Soft-Start Comparator RFB FB PWM-Latch C8 PWM Comparator 0.67V V SoftS Optocoupler PWM OP CS V SoftS2 V SoftS1 X3.3 Improved Current Mode Figure 8 3.4 Figure 10 PWM Controlling Soft Start Phase When the VVCC exceeds the on-threshold voltage, the IC starts the Soft Start mode (see Figure 10). The function is realized by an internal Soft Start resistor, an current sink and a counter. And the amplitude of the current sink is controlled by the counter (see Figure 11). Startup Phase S o ft S ta r t c o u n te r Soft Start finish 5V S o ftS S o ft S ta r t R SoftS SoftS S o ft S ta rt S o ft-S ta rt C o m p a ra to r C7 & G a te D riv e r G7 Soft Start 32I Counter 8I 4I 2I I 0 .6 7 V x 3 .3 CS PW M OP Figure 9 Figure 11 After the IC is switched on, the VSFOFTS voltage is controlled such that the voltage is increased stepwisely (32 steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in every 300us such that the current sink Soft Start In the Startup Phase, the IC provides a Soft Start period to control the maximum primary current by means of a duty cycle limitation. The Soft Start function Version 2.0 Soft Start Circuit 10 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description decrease gradually and the duty ratio of the gate drive increases gradually. The Soft Start will be finished in 10ms (tSoft-Start) after the IC is switched on. At the end of the Soft Start period, the current sink is switched off. VSoftS tSoft-Start VSOFTS32 In addition to Start-Up, Soft-Start is also activated at each restart attempt during Auto Restart. The Start-Up time tStart-Up before the converter output voltage VOUT is settled, must be shorter than the SoftStart Phase tSoft-Start (see Figure 13). By means of Soft-Start there is an effective minimization of current and voltage stresses on the external power MOSFET, the clamp circuit and the output overshoot and it helps to prevent saturation of the transformer during Start-Up. 3.5 0.75 t Gate Driver PWM Section PWM Section Oscillator Duty Cycle max Clock Frequency Jitter t Figure 12 Gate drive signal under Soft-Start Phase Within the soft start period, the duty cycle is increasing from zero to maximum gradually (see Figure 12). Soft Start Block Soft Start Comparator VSoftS PWM Comparator tSoft-Start VSOFTS32 1 G8 Gate Driver S R Q & G9 Current Limiting VFB Gate t Figure 14 4.2V VOUT t VOUT tStart-Up t Figure 13 FF1 Start Up Phase Version 2.0 PWM Section Block 3.5.1 Oscillator The oscillator generates a fixed frequency of 100kHz with frequency jittering of ±4% (which is ±4kHz) at a jittering period of 4ms. A capacitor, a current source and a current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.75. Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the Soft 11 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description Thus the leading switch on spike is minimized. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During power up, when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is set to low in order to disable power transfer to the secondary side. Start block. Then the switching frequency is varied in range of 100kHz ± 4kHz at period of 4ms. 3.5.2 PWM-Latch FF The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the external power MOSFET. After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the gate driver is shut down immediately. 3.5.3 3.6 Gate Driver Current Limiting PWM Latch Latched Off FF1 Mode Current Limiting VCC Spike Blanking 190ns PW M-Latch 1 1.66V C11 Propagation-Delay Compensation OPP Gate Vcsth C10 PWM-OP Leading Edge Blanking 220ns & G10 Gate Driver Figure 15 0.25V Gate Driver D1 CS Figure 17 Current Limiting Block There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The source current of the external power MOSFET is sensed via an external sense resistor RSense. By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth, the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down of the external power MOSFET with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power can be reduced to minimal. In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge ca. t = 130ns 5V t Version 2.0 1pF 10k Active Burst Mode The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the external power MOSFET threshold. This is achieved by a slope control of the rising edge at the gate driver’s output (see Figure 16). Figure 16 C12 Gate Rising Slope 12 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the AND Gate G10 if Active Burst Mode is entered. When it is activated, the current limiting is reduced to 0.25V. This voltage level determines the maximum power level in Active Burst Mode. Furthermore, the comparator C11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the Latched Mode by the comparator C11, a 190ns spike blanking time is integrated in the output path of comparator C11. 3.6.1 induced to the delay, which depends on the ratio of dI/ dt of the peak current (see Figure 19). The overshoot of Signal2 is larger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the external power MOSFET is compensated over temperature within a wide range. Current Limiting is then very accurate. For example, Ipeak = 0.5A with RSense = 2. The current sense threshold is set to a static voltage level Vcsth=1V without Propagation Delay Compensation. A current ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a propagation delay time of tPropagation Delay =180ns leads to an Ipeak overshoot of 14.4%. With the propagation delay compensation, the overshoot is only around 2% (see Figure 20). Leading Edge Blanking V Sense V csth tLEB = 220ns without compensation with compensation V 1,3 1,25 1,2 Figure 18 VSense t Leading Edge Blanking 1,1 1,05 Whenever the power MOSFET is switched on, a leading edge spike is generated due to the primaryside capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns. 3.6.2 1,15 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 V 2 µs dVSense dt Figure 20 Overcurrent Shutdown Propagation Delay Compensation Signal2 ISense Ipeak2 Ipeak1 ILimit V OSC Signal1 t Propagation Delay m ax. D uty C ycle IOvershoot2 off tim e V Sense IOvershoot1 P ropagation D elay t V cs th t Figure 19 S ig nal1 Current Limiting In case of overcurrent detection, there is always propagation delay to switch off the external power MOSFET. An overshoot of the peak current Ipeak is Version 2.0 Figure 21 13 S ign al2 t Dynamic Voltage Threshold Vcsth 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 21). In case of a steeper slope the switch off of the driver is earlier to compensate the delay. 3.7 blanking time is passed, the switch S1 is opened by G2. Then the 0.9V clamped voltage at BL pin is charged to 4.0V through the internal IBK constant current. Then G5 is enabled by comparator C3. After the 25us spike blanking time, the Auto Restart Mode is activated. For example, if CBK = 0.22µF, IBK = 13µA Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 72ms The 20ms blanking time circuit after C4 is disabled by the soft start block before start up and the maximum CBK capacitor is restricted to use less than 1.3µF such that the controller can start up properly. The Active Burst Mode has basic blanking mode only while the Auto Restart Mode has both the basic and the extendable blanking mode. Control Unit The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode both have 20ms internal Blanking Time. For the Auto Restart Mode, a further extendable Blanking Time is achieved by adding external capacitor at BL pin. By means of this Blanking Time, the IC avoids entering into these two modes accidentally. Furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally. 3.7.1 3.7.2 Active Burst Mode The IC enters Active Burst Mode under low load conditions. With the Active Burst Mode, the efficiency increases significantly at light load conditions while still maintaining a low ripple on VOUT and a fast response on load jumps. During Active Burst Mode, the IC is controlled by the FB signal. Since the IC is always active, it can be a very fast response to the quick change at the FB signal. The Start up Cell is kept OFF in order to minimize the power loss. Basic and Extendable Blanking Mode BL 5.0V # CBK IBK 0.9V 1 S1 Soft Start block G2 Internal Bias C3 Spike Blanking 25us 4.0V 4.2V & 4.2V C4 20ms Blanking Time G5 C4 Auto Restart Mode C5 1.23V 20ms Blanking Time & G6 Active Burst Mode C6a 3.5V & Basic and Extendable Blanking Mode G11 C6b There are 2 kinds of Blanking mode; basic mode and the extendable mode. The basic mode has an internal pre-set 20ms blanking time while the extendable mode has extended blanking time to basic mode by connecting an external capacitor to the BL pin. For the extendable mode, the gate G5 is blocked even though the 20ms blanking time is reached if an external capacitor CBK is added to BL pin. While the 20ms Version 2.0 & G6 1.23V Control Unit Figure 22 Active Burst Mode FB C5 FB Current Limiting & G10 20 ms Blanking Time 3.0V Figure 23 Control Unit Active Burst Mode The Active Burst Mode is located in the Control Unit. Figure 23 shows the related components. 14 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description 3.7.2.1 Entering Active Burst Mode The FB signal is kept monitoring by the comparator C4. During normal operation, the internal blanking time counter is reset to 0. When FB signal falls below 1.23V, it starts to count. When the counter reach 20ms and FB signal is still below 1.23V, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps. After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to approx. 450µA. It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5V such that the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest VCC level is reached at no load condition. VFB Entering Active Burst Mode 4.2V 3.5V 3.0V Leaving Active Burst Mode 1.23V Blanking Timer t 20ms Blanking Time VCS 3.7.2.2 Working in Active Burst Mode After entering the Active Burst Mode, the FB voltage rises as VOUT starts to decrease, which is due to the inactive PWM section. The comparator C6a monitors the FB signal. If the voltage level is larger than 3.5V, the internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active Burst Mode the gate G10 is released and the current limit is reduced to 0.25V. In one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at VOUT is still kept unchanged, the FB signal will drop to 3.0V. At this level the C6b deactivates the internal circuit again by switching off the internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst Mode. In Active Burst Mode, the FB voltage is changing like a saw tooth between 3.0V and 3.5V (see Figure 24). 1.06V t Current limit level during Active Burst Mode 0.25V VVCC t 10.5V IVCC t 2.5mA 3.7.2.3 Leaving Active Burst Mode The FB voltage will increase immediately if there is a high load jump. This is observed by the comparator C4. As the current limit is app. 25% during Active Burst Mode, a certain load jump is needed so that the FB signal can exceed 4.2V. At that time the comparator C4 resets the Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can then be resumed to stabilize VOUT. 450uA VOUT t t Figure 24 Version 2.0 15 Signals in Active Burst Mode 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description The VCC voltage is observed by comparator C2. If the VCC voltage is > 25.5V and last for 120µs, the overvoltage detection is activated. It enters the latch off mode.This protection mode is activated in both normal operating mode and burst mode. The internal Voltage Reference is switched off most of the time once Latched Off Mode is entered in order to minimize the current consumption of the IC. This Latched Off Mode can only be reset if the VVCC < 6.23V. In this mode, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 250µA. As there is no longer a self-supply by the auxiliary winding, the VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 10.5V. The Startup Cell is switched off again when VCC has exceeded 18V. Once the Latched Off Mode was entered, there is no Start Up Phase whenever the VCC exceeds the switch-on level of the Undervoltage Lockout. Therefore the VCC voltage changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 26). 3.7.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode and the others enter Auto Restart Mode. Besides the pre-defined protection feature for the Latch off mode, there is also an external Latch off Enable pin for customer defined Latch off protection features. The Latched Off Mode can only be reset if VCC falls below 6.23V. Both modes prevent the SMPS from destructive states.The following table shows the relationship between possible system failures and the chosen protection modes. VCC Overvoltage Latched Off Mode Overtemperature Latched Off Mode Short Winding/Short Diode Latched Off Mode External Protection Enable Latched Off Mode Overload Auto Restart Mode Open Loop Auto Restart Mode VCC Undervoltage Auto Restart Mode Short Optocoupler Auto Restart Mode 3.7.3.1 VVCC Latched Off Mode CS 1.66V C11 UVLO G3 BL IVCCStart Latched Off Mode t 0.9mA 25us Blanking Time C9 # Latch Enable signal 10.5V 1 2ms counter TLE 18V LatchedOff ModeReset VVCC 130°C Control Unit Figure 25 Version 2.0 Signals in Latched Off Mode Latched Off Mode 16 3 Jul 2009 F3 PWM controller ICE3AS03LJG Functional Description operating mode, comparator C10 controls the maximum level of the CS signal at 1.06V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1.06V. Instead the comparator C11 detects the peak current voltage > 1.66V and last for 190ns , it enters the Latched Off Mode immediately in order to keep the SMPS in a safe stage. In case the pre-defined Latch Off features are not sufficient, there is a customer defined external Latch Enable feature. The Latch Off Mode can be triggered by pulling down the BL pin to < 0.33V. It can simply add a trigger signal to the base of the externally added transistor, TLE at the BL pin. To ensure this latch function will not be mis-triggered during start up, a 2ms delay time is implemented to blank the unstable signal. 3.7.3.2 Auto Restart Mode BL # and IBK is 13uA, the extendable blanking time is around 52ms and the total blanking time is 72ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode. CBK 5.0V IBK 0.9V 1 S1 G2 C3 Spike Blanking 25us 4.0V & 4.2V FB C4 20ms Blanking Time G5 Auto Restart Mode Control Unit Figure 27 Auto Restart Mode In case of Overload or Open Loop, the FB exceeds 4.2V which will be observed by comparator C4. Then the internal blanking counter starts to count. When it reaches 20ms, the switch S1 is released. Then the clamped voltage 0.9V at VBL can increase. When there is no external capacitor CBK connected, the VBL will reach 4.0V immediately. When both the input signals at AND gate G5 is positive, the Auto-Restart Mode will be activated after the extra spike blanking time of 25us is elapsed. However, when an extra blanking time is needed, it can be achieved by adding an external capacitor, CBK. A constant current source of IBK will start to charge the capacitor CBK from 0.9V to 4.0V after the switch S1 is released. The charging time from 0.9V to 4.0V are the extendable blanking time. If CBK is 0.22µF Version 2.0 17 3 Jul 2009 F3 PWM controller ICE3AS03LJG Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Ta=25°C unless otherwise specified. Parameter Symbol Limit Values min. max. Unit Remarks HV Voltage VHV - 500 V VCC Supply Voltage VVCC -0.3 27 V FB Voltage VFB -0.3 5.5 V BL Voltage VBL -0.3 5.5 V CS Voltage VCS -0.3 5.5 V Junction Temperature Tj -40 150 °C Storage Temperature TS -55 150 °C Thermal Resistance Junction -Ambient RthJA - 185 K/W Soldering temperature,wave soldering only allowed at leads Tsold - 260 °C 1.6mm(0.063 in.) from case for 10s ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model1) 1) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor) 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values min. max. Unit Remarks VCC Supply Voltage VVCC VVCCoff 25 V Max. value limited due to VCC OVP Junction Temperature of Controller TjCon -25 130 °C Max value limited due to thermal shut down of controller Version 2.0 18 3 Jul 2009 F3 PWM controller ICE3AS03LJG Electrical Characteristics 4.3 4.3.1 Note: Characteristics Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from – 25 °C to 125 °C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Start Up Current IVCCstart - 150 250 µA VVCC =16.5V VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V IVCCcharge2 0.55 0.90 1.60 mA VVCC = 1V IVCCcharge3 - 0.7 - mA VVCC =16.5V Leakage Current of Start Up Cell IStartLeak - 0.2 50 µA VHV = 450V, VVCC=18V Supply Current with Inactive Gate IVCCsup1 - 1.5 2.5 mA Supply Current with Active Gate IVCCsup2 - 2.5 4.2 mA IFB = 0A, CLoad=680pF Supply Current in Latched Off Mode IVCClatch - 250 - µA IFB = 0A Supply Current in Auto Restart Mode with Inactive Gate IVCCrestart - 250 - µA IFB = 0A Supply Current in Active Burst Mode with Inactive Gate IVCCburst1 - 450 950 µA VFB = 2.5V IVCCburst2 - 450 950 µA VVCC = 11.5V,VFB = 2.5V VVCCon VVCCoff VVCChys 17.0 9.8 - 18.0 10.5 7.5 19.0 11.2 - V V V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis 4.3.2 Internal Voltage Reference Parameter Trimmed Reference Voltage Version 2.0 Symbol VREF Limit Values min. typ. max. 4.90 5.00 5.10 19 Unit Test Condition V measured at pin FB IFB = 0 3 Jul 2009 F3 PWM controller ICE3AS03LJG Electrical Characteristics 4.3.3 PWM Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. fOSC1 87 100 113 kHz fOSC2 92 100 108 kHz Tj = 25°C Frequency Jittering Range fjitter - ±4 - kHz Tj = 25°C Max. Duty Cycle Dmax 0.70 0.75 0.80 Min. Duty Cycle Dmin 0 - - PWM-OP Gain AV 3.1 3.3 3.5 Voltage Ramp Offset VOffset-Ramp - 0.67 - V VFB Operating Range Min Level VFBmin - 0.5 - V VFB Operating Range Max level VFBmax - - 4.3 V FB Pull-Up Resistor RFB 9 15.4 22 kΩ Fixed Oscillator Frequency 1) VFB < 0.3V CS=1V, limited by Comparator C41) The parameter is not subjected to production test - verified by design/characterization 4.3.4 Soft Start time Parameter Soft Start time Version 2.0 Symbol tSS Limit Values min. typ. max. - 10 - 20 Unit Test Condition ms 3 Jul 2009 F3 PWM controller ICE3AS03LJG Electrical Characteristics 4.3.5 Control Unit Parameter Symbol Limit Values min. typ. max. Unit Test Condition VFB = 4V Clamped VBL voltage during Normal Operating Mode VBLclmp 0.85 0.90 0.95 V Blanking time voltage limit for Comparator C3 VBKC3 3.85 4.00 4.15 V Over Load & Open Loop Detection Limit for Comparator C4 VFBC4 4.05 4.20 4.35 V Active Burst Mode Level for Comparator C5 VFBC5 1.12 1.23 1.34 V Active Burst Mode Level for Comparator C6a VFBC6a 3.35 3.50 3.65 V After Active Burst Mode is entered Active Burst Mode Level for Comparator C6b VFBC6b 2.88 3.00 3.12 V After Active Burst Mode is entered Overvoltage Detection Limit VVCCOVP 25 25.5 26.5 V Latch Enable level at BL pin VLE 0.25 0.33 0.4 V > 25µs Charging current at BL pin IBK 9.1 13.0 16.9 µA Charge starts after the built-in 20ms blanking time elapsed Latched Thermal Shutdown1) TjSD 130 140 150 °C Built-in Blanking Time for Overload Protection or enter Active Burst Mode tBK - 20 - ms without external capacitor at BL pin Inhibit Time for Latch Enable function during Start up tIHLE - 2.0 - ms After IC turns on Spike Blanking Time before Latch off tSpike - 25 - µs VVCCPD 5.2 6.23 7.8 V or Auto Restart Protection Power Down Reset for Latched Mode 1) After Latched Off Mode is entered The parameter is not subjected to production test - verified by design/characterization. The thermal shut down temperature refers to the junction temperature of the controller. Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD Version 2.0 21 3 Jul 2009 F3 PWM controller ICE3AS03LJG Electrical Characteristics 4.3.6 Current Limiting Parameter Symbol Limit Values min. typ. max. Unit Test Condition dVsense / dt = 0.6V/µs (see Figure 20) Peak Current Limitation (incl. Propagation Delay) Vcsth 0.99 1.06 1.13 V Peak Current Limitation during Active Burst Mode VCS2 0.21 0.25 0.31 V Leading Edge Blanking tLEB - 220 - ns CS Input Bias Current ICSbias -1.5 -0.2 - µA Over Current Detection for Latched Off Mode VCS1 1.57 1.66 1.76 V CS Spike Blanking for Comparator C11 tCSspike - 190 - ns 4.3.7 VCS =0V Driver Section Parameter GATE Low Voltage GATE High Voltage Symbol VGATElow VGATEhigh Limit Values Unit Test Condition min. typ. max. - - 1.2 V VVCC = 5 V IGate = 1 mA - - 1.5 V VVCC = 5 V IGate = 5 mA - 0.8 - V IGate = 0 A - 1.6 2.0 V IGate = 20 mA -0.2 0.2 - V IGate = -20 mA - 10.0 - V VVCC = 25V CL = 680pF - 9.0 - V VVCC = 15V CL = 680pF - 8.0 - V VVCC = VVCCoff + 0.2V CL = 680pF GATE Rise Time (incl. Gate Rising Slope) trise - 150 - ns VGate = 2V ...9V1) CL = 680pF GATE Fall Time tfall - 55 - ns VGate = 9V ...2V1) CL = 680pF GATE Current, Peak, Rising Edge IGATE -0.17 - - A CL = 680pF2) GATE Current, Peak, Falling Edge IGATE - - 0.39 A CL = 680pF2) 1) Transient reference value 2) The parameter is not subjected to production test - verified by design/characterization Version 2.0 22 3 Jul 2009 F3 PWM controller ICE3AS03LJG Outline Dimension 5 Outline Dimension PG-DSO-8 (Plastic Dual Small Outline) Figure 28 PG-DSO-8 (PB-free Plating Plastic Dual Small Outline) Dimensions in mm Version 2.0 23 3 Jul 2009 F3 PWM controller ICE3AS03LJG Marking 6 Marking Marking Figure 29 Marking for ICE3AS03LJG Version 2.0 24 3 Jul 2009 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. 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