D a t as he e t , V e rs io n 2 . 9, 25 M a r 20 1 3
®
CoolSET -F3
( J i tte r Ve r s i on )
I CE3 B0 3 65 J
I CE3 B0 5 65 J
I CE3 B1 5 65 J
I CE3 B2 0 65 J
O f f - Li ne S M P S C ur re nt Mo de
C on t ro ll er w it h in t e gr at e d 6 50 V
C oo lM O S ® a nd S t a rt u p c e l l
(f r eq ue nc y j it t er Mo de ) in D I P - 8
Po we r M a n ag e m e n t & Su p p ly
N e v e r
s t o p
t h i n k i n g .
CoolSET®-F3
ICE3Bxx65J
Revision History:
2013-03-25
Datasheet Version 2.9
Previous Version: 2.8
Page
Subjects (major changes since last revision)
Revised typo (F3)
15
Revised max. limit for VFB, V SOFTS and V CS.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
CoolMOS ®, CoolSET® are trademarks of Infineon Technologies AG.
Edition 2013-03-25
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2013 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
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question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CoolSET®-F3
ICE3Bxx65J
Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-8
Product Highlights
• Active Burst Mode to reach the lowest Standby Power
Requirements < 100mW
• Adjustable Blanking Window for High Load Jumps to
increase Reliability
• Frequency Jittering for Low EMI
• Pb-free lead plating, RoHS compilant
Features
Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650V Avalanche Rugged CoolMOS ® with built in
switchable Startup Cell
Active Burst Mode for lowest Standby Power
@ light load controlled by Feedback Signal
Fast Load Jump Response in Active Burst Mode
67 kHz fixed Switching Frequency
Auto Restart Mode for Over temperature
Detection
Auto Restart Mode for Overvoltage Detection
Auto Restart Mode for Overload and Open Loop
Auto Restart Mode for VCC Undervoltage
User defined Soft Start
Minimum of external Components required
Max Duty Cycle 75%
Overall Tolerance of Current Limiting < ±5%
Internal Leading Edge Blanking
BiCMOS technology provides wide VCC Range
Frequency Jittering for Low EMI
PG-DIP-8
The CoolSET®-F3(Jitter version) meets the requirements
for Off-Line Battery Adapters and low cost SMPS for the
lower power range. By use of a BiCMOS technology a wide
VCC range up to 26V is provided. This covers the changes
in the auxiliary supply voltage if a CV/CC regulation is
implemented on the secondary side. Furthermore an Active
Burst Mode is integrated to fullfill the lowest Standby Power
Requirements 4.5V. Therefore
the overvoltage detection can only be active during Soft
Start Phase (VSoftS < 4.0V) and when FB signal is
outside the operating range > 4.5V. This means any
t
Figure 15
Control Unit
Signals in Active Burst Mode
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CoolSET®-F3
ICE3Bxx65J
small voltage overshoots of VVCC during normal
operating cannot trigger the Auto Restart Mode I.
In Order to ensure system reliability and prevent any
false activation, a blanking time is implemented before
the IC can enter into the Auto Restart Mode I. The
output of the VCC overvoltage detection is fed into a
spike blanking with a time constant of 8.0us.
The other fault detection which can result in the Auto
Restart Mode I and has this 8.0us blanking time is the
Overtemperature detection. This block checks for a
junction temperature of higher than 140°C for
malfunction operation.
Once Auto Restart Mode is entered, the internal bias is
switched off in order to reduce the current consumption
of the IC as much as possible. In this mode, the
average current consumption is only 300uA as the only
working blocks are the reference block and the
Undervoltage Lockout(UVLO) which controls the
Startup Cell by switching on/off at V VCCon/VVCCoff.
As there is no longer a self supply by the auxiliary
winding, VCC starts to drop. The UVLO switches on the
integrated Startup Cell when VCC falls below 10.3V. It
will continue to charge VCC up to 18V whereby it is
switched off again and the IC enters into the Start Up
Phase.
As long as all fault conditions have been removed, the
IC will automatically power up as usual with switching
cycle at the GATE output after Soft Start duration. Thus
the name Auto Restart Mode.
3.6.3.2
This charging of the Soft Start capacitor from
3.2V~3.6V to 4.0V defines a blanking window which
prevents the system from entering into Auto Restart
Mode II unintentionally during large load jumps. In this
event, FB will rise close to 5.0V for a short duration
before the loop regulates with FB less than 4.5V. This
is the same blanking time window as for the Active
Burst Mode and can therefore be adjusted by the
external CSoftS.
In case of VCC undervoltage, ie. VCC falls below
10.3V, the IC will be turned off with the Startup Cell
charging VCC as described earlier in this section. Once
VCC is charged above 18V, the IC will start a new
startup cycle. The same procedure applies when the
system is under Short Optocoupler fault condition, as it
will lead to VCC undervoltage.
Auto Restart Mode II
Internal
Bias
SoftS
C3
4.0V
&
4.5V
C4
G5
Auto
Restart
Mode
FB
Control Unit
Figure 17
Auto Restart Mode II
In case of Overload or Open Loop, FB exceeds 4.5V
which will be observed by C4. At this time, the external
Soft Start capacitor can now be charged further by the
integrated pull up resistor R SoftS via switch S3 (see
Figure 13). If V SoftS exceeds 4.0V which is observed by
C3, Auto Restart Mode II is entered as both inputs of
the gate G5 are high.
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CoolSET®-F3
ICE3Bxx65J
4
Electrical Characteristics
Note:
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
Unit
Remarks
Tj = 110°C
min.
max.
VDS
-
650
V
ICE3B0365J
ID_Puls1
-
1.6
A
ICE3B0565J
ID_Puls2
-
2.3
A
ICE3B1565J
ID_Puls3
-
6.1
A
ICE3B2065J
ID_Puls4
-
10.3
A
ICE3B0365J
EAR1
-
0.005
mJ
ICE3B0565J
EAR2
-
0.01
mJ
ICE3B1565J
EAR3
-
0.15
mJ
ICE3B2065J
EAR4
-
0.4
mJ
ICE3B0365J
IAR1
-
0.3
A
ICE3B0565J
IAR2
-
0.5
A
ICE3B1565J
IAR3
-
1.5
A
ICE3B2065J
IAR4
-
2.0
A
VCC Supply Voltage
VVCC
-0.3
27
V
FB Voltage
VFB
-0.3
5.5
V
SoftS Voltage
VSoftS
-0.3
5.5
V
CS Voltage
VCS
-0.3
5.5
V
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-55
150
°C
Thermal Resistance
Junction-Ambient
RthJA
-
90
K/W
PG-DIP-8
ESD Capability
VESD
-
2
kV
Human body model2)
Drain Source Voltage
Pulse drain current,
tp limited by max.
Tj=150°C
Avalanche energy,
repetitive tAR limited
by max. Tj=150°C1)
Avalanche current,
repetitive tAR limited
by max. Tj=150°C1)
Controller & CoolMOS®
1)
Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR* f
2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor)
Version 2.9
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CoolSET®-F3
ICE3Bxx65J
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
min.
max.
Unit
VCC Supply Voltage
VVCC
V VCCoff
26
V
Junction Temperature of Controller
TjCon
-25
130
°C
Junction Temperature of
CoolMOS ®
TJCoolMOS
-25
150
°C
4.3
4.3.1
Note:
Remarks
Max value limited due to
integrated thermal shut down
Characteristics
Supply Section
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage
and junction temperature range TJ from – 25 oC to 130 oC. Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Start Up Current
IVCCstart
-
300
450
mA
V VCC = 17V
VCC Charge Current
IVCCcharge1
-
-
5.0
mA
V VCC = 0V
IVCCcharge2
0.55
1.05
1.60
mA
V VCC = 1V
IVCCcharge3
-
0.88
-
mA
V VCC = 17V
Leakage Current of
Start Up Cell & CoolMOS
IStartLeak
-
0.2
50
mA
V Drain= 450V
at T j = 100°C
Supply
ICE3B0365J
Current with ICE3B0565J
Inactive Gate ICE3B1565J
IVCCsup_ng1
-
1.7
2.5
mA
Soft Start pin is open
ICE3B2065J
IVCCsup_ng2
-
3.3
4.2
mA
Supply Current with Active Gate IVCCsup_g
-
2.5
3.6
mA
V SoftS = 3.0V
IFB = 0
Supply Current in
Auto Restart Mode
with Inactive Gate
IVCCrestart
-
300
-
mA
IFB = 0
ISofts = 0
Supply Current in
Active Burst Mode
with Inactive Gate
IVCCburst1
-
500
950
uA
V FB = 2.5V
V SoftS = 3.0V
IVCCburst2
-
500
950
uA
V VCC = 11.5V
V FB = 2.5V
V SoftS = 3.0V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
17.0
9.6
-
18.0
10.3
7.7
19.0
11.0
-
V
V
V
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CoolSET®-F3
ICE3Bxx65J
4.3.2
Internal Voltage Reference
Parameter
Trimmed Reference Voltage
4.3.3
Symbol
VREF
Limit Values
min.
typ.
max.
4.90
5.00
5.10
Unit
Test Condition
V
measured at pin FB
IFB = 0
Unit
Test Condition
PWM Section
Parameter
Symbol
Limit Values
min.
typ.
max.
fOSC3
58
67
76
kHz
fOSC4
62
67
74.5
kHz
Tj = 25°C
Frequency Jittering Range
fdelta
-
±2.7
-
kHz
Tj = 25°C
Max. Duty Cycle
Dmax
0.70
0.75
0.80
Min. Duty Cycle
Dmin
0
-
-
PWM-OP Gain
AV
3.0
3.2
3.4
Max. Level of Voltage Ramp
VMax-Ramp
-
0.6
-
V
VFB Operating Range Min Level VFBmin
-
0.5
-
V
VFB Operating Range Max level
VFBmax
-
-
4.3
V
Feedback Pull-Up Resistor
RFB
9
14
22
kW
Soft-Start Pull-Up Resistor
RSoftS
30
45
62
kW
Fixed Oscillator Frequency
1)
V FB < 0.3V
CS=1V limited by
Comparator C41)
This parameter is not subject to production test - verified by design/characterization
4.3.4
Control Unit
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
V FB = 5V
Deactivation Level for SoftS
Comparator C7 by C2
VSoftSC2
2.98
3.10
3.22
V
Clamped V SoftS Voltage during
Burst Mode
VSoftSclmp_bm 2.88
3.00
3.12
V
Activation Limit of
Comparator C3
VSoftSC3
3.85
4.00
4.15
V
V FB = 5V
SoftS Startup Current
ISoftSstart
-
0.9
-
mA
V SoftS = 0V
Over Load & Open Loop
Detection Limit for
Comparator C4
VFBC4
4.33
4.50
4.67
V
V SoftS = 4.5V
Active Burst Mode Level for
Comparator C5
VFBC5
1.23
1.35
1.43
V
V SoftS = 4.5V
Active Burst Mode Level for
Comparator C6a
VFBC6a
3.48
3.61
3.76
V
After Active Burst
Mode is entered
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CoolSET®-F3
ICE3Bxx65J
Active Burst Mode Level for
Comparator C6b
VFBC6b
2.88
3.00
3.12
V
After Active Burst
Mode is entered
Overvoltage Detection Limit
VVCCOVP
19.5
20.5
21.5
V
V FB = 5V, VSoftS = 3V
TjSD
130
140
150
°C
tSpike
-
8.0
-
ms
Thermal Shutdown
1)
Spike Blanking
1)
The parameter is not subject to production test - verified by design/characterization
Note:
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
4.3.5
Current Limiting
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
dVsense / dt = 0.6V/ms
Peak Current Limitation (incl.
Propagation Delay Time)
(see Figure 11)
Vcsth
1.01
1.06
1.11
V
Peak Current Limitation during
Active Burst Mode
VCS2
0.27
0.32
0.37
V
Leading Edge Blanking
tLEB
-
220
-
ns
V SoftS = 3.0V
CS Input Bias Current
ICSbias
-1.0
-0.2
0
µA
V CS = 0V
Unit
Test Condition
4.3.6
CoolMOS® Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Drain Source Breakdown
Voltage
V(BR)DSS
600
650
-
-
V
V
Tj = 25°C
Tj = 110°C
Drain Source
On-Resistance
ICE3B0365J
RDSon1
-
6.45
13.70
7.50
17.00
W
W
Tj = 25°C
Tj = 125°C1)
at ID = 0.3A
ICE3B0565J
RDSon2
-
4.70
10.00
5.44
12.50
W
W
Tj = 25°C
Tj = 125°C1)
at ID = 0.5A
ICE3B1565J
RDSon3
-
1.70
3.57
1.96
4.12
W
W
Tj = 25°C
Tj = 125°C1)
at ID = 1.5A
ICE3B2065J
RDSon4
-
0.92
1.93
1.05
2.22
W
W
Tj = 25°C
Tj = 125°C1)
at ID = 2.0A
ICE3B0365J
Co(er)1
-
3.65
-
pF
V DS = 0V to 480V
ICE3B0565J
Co(er)2
-
4.75
-
pF
ICE3B1565J
Co(er)3
-
11.63
-
pF
ICE3B2065J
Co(er)4
-
21
-
pF
Effective output
capacitance,
energy related
Version 2.9
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CoolSET®-F3
ICE3Bxx65J
Rise Time
trise
-
302)
-
ns
Fall Time
tfall
-
302)
-
ns
1)
The parameter is not subject to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application
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CoolSET®-F3
ICE3Bxx65J
5
Temperature derating curve
Figure 18
Safe Operating area ( SOA ) curve for ICE3B0365J
Figure 19
Safe Operating area ( SOA ) curve for ICE3B0565J
Version 2.9
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CoolSET®-F3
ICE3Bxx65J
Figure 20
Safe Operating area ( SOA ) curve for ICE3B1565J
Figure 21
Safe Operating area ( SOA ) curve for ICE3B2065J
Version 2.9
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CoolSET®-F3
ICE3Bxx65J
Figure 22
Version 2.9
SOA temperature derating coefficient curve
22
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CoolSET®-F3
ICE3Bxx65J
6
Outline Dimension
PG-DIP-8
(Plastic Dual In-Line Outline)
Figure 23
Version 2.9
PG-DIP-8 ( Pb-free lead plating Platic Dual-in-Line Outline )
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CoolSET®-F3
ICE3Bxx65J
7
Marking
Marking
Figure 24
Marking for ICE3B0365J
Marking
Figure 25
Version 2.9
Marking for ICE3B0565J
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CoolSET®-F3
ICE3Bxx65J
Marking
Figure 26
Marking for ICE3B1565J
Marking
Figure 27
Version 2.9
Marking for ICE3B2065J
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CoolSET®-F3
ICE3Bxx65J
Schematic for recommended PCB layout
8
Schematic for recommended PCB layout
Figure 28
Schematic for recommended PCB layout
General guideline for PCB layout design using F3 CoolSET (refer to Figure 26):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of
IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 26):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)
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CoolSET®-F3
ICE3Bxx65J
Schematic for recommended PCB layout
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:
These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and
reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the
sensitive components such as the primary controller, IC11.
Version 2.9
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