ICE3PCS01GXUMA1

CCM-PFC ICE3PCS01G Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) Product Highlights • • • • • • • • High efficiency over the whole load range Lowest count of external components Accurate and adjustable switching frequency Bulk voltage good signal for inrush relay control or PWM IC enabling Integrated digital voltage loop compensation Fast output dynamic response during load jump External synchronization Extra low peak current limitation ICE3PCS01G PG-DSO-14 Features Description • • • The ICE3PCS01G is a 14-pins wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. • • • • • • • • Continuous current operation mode PFC Wide input range of Vcc up to 25V Programmable boost follower step level according to input line and output power conditions Enhanced dynamic response without input current distortion Accurate brown-out protection threshold External current loop compensation for greater user flexibility Open loop protection Second over bulk voltage protection PFC enable function Separate signal and power ground pins Maximum duty cycle of 95% (typical) DBYP R NTC DB LBoos t 90 ~ 270 Vac V CC Line Filter R GATE RGS RSHUNT DBRO1 DBRO2 RBVS 4 R BVS 1 CB CE RBVS 2 RBVS 5 RBVS 3 RBVS 6 RCS Qrel RRel RBRO1 VB_OK ISENSE RBRO2 GATE PGND VSENSE OVP BOP RBRO3 CBRO PWM Feedback RBOFO 1 BOFO SGND VREF VBTHL_EN FREQ ICOMP VCC RBOFO 2 RVB 1 V CC RVB 2 Type Package ICE3PCS01G PG-DSO-14 Version 3.0 1 R FREQ CICOMP CVCC 03 April 2017 CCM-PFC ICE3PCS01G 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.7 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.9 3.10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Frequency Setting and External Synchronization . . . . . . . . . . . . . . . . . . . . .8 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Input Voltage Brownout Protection(BOP) . . . . . . . . . . . . . . . . . . . . . . . .11 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 First Over-Voltage Protection (OVP1) . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Second Over Voltage Protection (OVP2) . . . . . . . . . . . . . . . . . . . . . . . .12 Bulk Voltage Monitor and Enable Function . . . . . . . . . . . . . . . . . . . . . . .12 Boost Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Protection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PFC Brownout Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Boost Follower Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Version 3.0 2 03 April 2017 CCM-PFC ICE3PCS01G 4.3.9 4.3.10 4.3.11 4.3.12 4.3.13 5 Version 3.0 Bulk Voltage Good Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 03 April 2017 CCM-PFC ICE3PCS01G Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration 1.2 Pin Symbol Function 1 BOFO Boost Follower Setting 2 ISENSE 3 SGND 4 ICOMP Current Loop Compensation 5 FREQ Switching Frequency Setting VB_OK Bulk Voltage OK signal 6 7 Current Sense Input ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (RSHUNT). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high negative voltage drop at RSHUNT, driving currents out of pin 2 which could be beyond the absolute maximum ratings. Therefore a series resistor (RCS) of around 50Ω is recommended in order to limit this current into the IC. Signal Ground VBTHL_EN PFC Enable Function 8 VREF Voltage Reference 9 BOP Brownout Protection 10 OVP 11 VSENSE SGND (Signal Ground) The ground potential of the IC. Over Voltage Protection Bulk Voltage Sense 12 VCC IC Supply Voltage 13 GATE Gate Drive 14 PGND Power Ground ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA6 and averages the current sense signal. FREQ (Frequency Setting) This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 21kHz to 100kHz. Package PG-DSO-14 BOFO PGND ISENSE GATE SGND ICOMP VSENSE FREQ OVP VB_OK BOP VBTHL_EN Figure 1 VB_OK (Bulk Voltage OK signal) This pin is pulled up to 5V internally once the bulk voltage is higher than 95% rated voltage and pulled down to ground once VSENSE pin is lower than preset VBTHL_EN threshold. This signal can enable the PWM IC or control the inrush relay. VCC P-DSO-14 VBTHL_EN An external voltage reference can be applied to VBTHL_EN to set the turn-off threshold of VB_OK signal. The IC can be shut down by pulling the pin lower than 0.5V VREF VREF (Voltage Reference) This pin is the 5V regulator output with a 5mA sourcing current (minimum). Pin Configuration (top view) Version 3.0 Pin Functionality BOFO (Boost Follower setting) An external DC voltage to this pin indicating the PWM output power which can be set to enter the Boost follower low step. 4 03 April 2017 CCM-PFC ICE3PCS01G Pin Configuration and Functionality BOP (Brownout Protection) BOP monitors the AC input voltage for Brownout Protection and line range selection OVP A resistive voltage divider from bulk voltage to SGND can set the over voltage protection threshold. This additional OVP is able to ensure system safety operation. VSENSE VSENSE is connected via a resistive divider to the bulk voltage. The voltage of VSENSE relative to SGND represents the output voltage. The bulk voltage is monitored for voltage regulation, over voltage protection and open loop protection. VCC VCC provides the power supply of the ground related to IC section. GATE GATE is the output for driving the PFC MOSFET.Its gate drive voltage is clamped at 15V (typically). PGND (Power Ground) Gate switching ground. Version 3.0 5 03 April 2017 Figure 2 Version 3.0 6 R BRO3 RBRO2 R BRO1 DBRO2 Line Filter CBRO CE R Shunt RCS QB R FREQ R GATE FREQ PGND GATE BOP VREF Oscillator/ Synchronization PWM Logic Driver Brownout Protection Reference Voltage ICE3PCS01G VCC Auxiliary Supply RVB2 DB CISENSE ISENSE C ICOMP ICOMP Current Loop Compensation/ PCL Ramp Generator PWM IC or Relay VB_OK Protection Unit Bulk Voltage Monitor VBTHL_EN R VB1 CVREF R BOFO1 SGND Nonlinear Gain Voltage Loop Compensation Second OVP Boost Follower BOFO R BOFO2 VSENSE OVP PWM Feedback R BVS3 R BVS2 RBVS1 R BVS6 CB R BVS5 RBVS4 2 D BRO1 90 ~ 270 Vac LBoost D BYP CCM-PFC ICE3PCS01G Block Diagram Block Diagram A functional block diagram is given in Figure 2. Note that the figure only shows the brief functional block and does not represent the implementation of the IC. Block Diagram 03 April 2017 CCM-PFC ICE3PCS01G Block Diagram Table 1 Bill Of Material Component Parameters Rectifier Bridge GBU8J CE 100nF/X2/275V LBoost 750uH QB IPP60R199CP DBYP MUR360 DB IDT04S60C CB 220µF/450V DBRO1...2 1N4007 RBRO1...2 3.9MΩ RBRO3 130kΩ CBRO 3μF Rshunt 30mΩ Cisense 1nF RCS 50Ω RGATE 3.3Ω RFREQ 67kΩ CICOMP 4.7nF/25V RBVS1...2 1.5MΩ RBVS3 18.85kΩ RBVS4...5 2MΩ RBVS6 23kΩ RVB1 330kΩ RVB2 200kΩ CVREF 100nF/25V RBOFO1...2 200kΩ Version 3.0 7 03 April 2017 CCM-PFC ICE3PCS01G Functional Description 3 3.1 Functional Description VBULK 100% 95% General 20% VCC The ICE3PCS01G is a 14-pins control IC for power factor correction converters. It is suitable for wide range line input applications from 85 to 265 VAC with overall efficiency above 90%. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM) resulting in a higher harmonics but still meeting the Class D requirement of IEC 1000-3-2. The outer voltage loop controls the output bulk voltage, integrated digitally within the IC. Depending on the load condition, internal PI compensation output is converted to an appropriate DC voltage which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device. 3.2 26V 12V IVCC 0.5V and pin 9 (BOP) >1.25V, the IC begins operating its gate drive and performs its startup as shown in Figure 3. If VCC drops below 11V, the IC is off. The IC will then be consuming typically 1.4mA, whereas consuming 6.7mA during normal operation The IC can be turned off and forced into standby mode by pulling down the voltage at pin 11 (VSENSE) below 0.5V or the voltage at pin 7 (VBTHL_EN) below 0.5V. 3.4 Frequency Setting and External Synchronization The IC can provide external switching frequency setting by an external resistor RFREQ and the online synchronization by external pulse signal at FREQ pin. 3.4.1 Frequency Setting The switching frequency of the PFC converter can be set with an external resistor RFREQ at FREQ pin as shown Figure 2. The pin voltage at VFREQ is typical 1V. The corresponding capacitor for the oscillator is integrated in the device and the RFREQ/frequency is given in Figure 4. The recommended operating frequency range is from 21kHz to 100kHz. As an example, a RFREQ of 67kΩ at pin FREQ will set a switching frequency FSW of 65kHz typically. Version 3.0 8 03 April 2017 CCM-PFC ICE3PCS01G Functional Description 3.5 Voltage Loop The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of sigma-delta ADC which has an internal reference of 2.5V and sampling rate of 3.55kHz (typical). The voltage loop compensation is integrated digitally for better dynamic response and saving design effort. Figure 6 shows the important blocks of this voltage loop. L Boost Figure 4 DB R BVS1 Frequency Versus RFREQ QB Rectified Input Voltage 3.4.2 External Synchronization The switching frequency can be synchronized to the external pulse signal after 6 external pulses delay once the voltage at the FREQ pin is higher than 2.5V. The synchronization means two points. Firstly, the PFC switching frequency is tracking the external pulse signal frequency. Secondly, the falling edge of the PFC signal is triggered by the rising edge of the external pulse signal. Figure 5 shows the blocks of frequency setting and synchronization. The external RSYN combined with RFREQ and the external diode DSYN can ensure pin voltage to be kept between 1.0V (clamped externally) and 5V (maximum pin voltage). If the external pulse signal has disappeared longer than 108μs (typical) the switching frequency will be synchronized to internal clock set by the external resistor RFREQ. R GATE R BVS2 CB R BVS3 Gate Driver Current Loop + PWM Generation GATE VIN Av(IIN ) Nonlinear Gain Sigmadelta ADC Notch Filter PI Filter 2.5V VSENSE t 500 ns OLP C2 a C1 a OVP OVP Q R Q S 0.5V 2.5V 2.7V C1 b Syn. clock IOSC Figure 6 1.0V DSYN OTA7 3.5.1 Notch Filter In the PFC converter, an averaged current through the output diode of rectified sine waveform charges the output capacitor and results in a ripple voltage at the output capacitor with a frequency two times of the line frequency. In this digital PFC, a notch filter is used to remove the ripple of the sensed output voltage while keeping the rest of the signal almost uninfluenced. In this way, an accurate and fast output voltage regulation without influence of the output voltage ripple is achieved. RSYN C9 RFREQ FREQ Figure 5 Version 3.0 Voltage Loop SYN 2.5V/1.25V Frequency Setting and Synchronization 3.5.2 Voltage Loop Compensation The Proportion-Integration (PI) compensation of the voltage loop is integrated digitally inside the IC. The digital data out of the PI compensator is converted to analog voltage for current loop control. 9 03 April 2017 CCM-PFC ICE3PCS01G Functional Description The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the output voltage of integrated PI compensator. This block has been designed to reduce the voltage loop dependency on the input voltage in order to support the wide input voltage range (85VAC-265VAC). Figure 7 gives the relative output power transfer curve versus the digital word from the integrated PI compensator. The output power at the input voltage of 85VAC and maximum digital word of 256 from PI compensator is set as the normative power and the power curves at different input voltage present the relative power to the normative one. power at 85V LBoost Rectified Input Voltage RGATE CB Rshunt GATE RCS Current Loop ISENSE power at 265V Current Loop Compensation ICOMP 10.00000 1.00000 relative output power DB QB CICOMP OTA6 voltage proportional to averaged Inductor current Gate Driver PWM Comparator R Q S C10 PWM Logic 5.0mS +/-50uA (linear range) S2 0.10000 5V Nonlinear Gain Input From Voltage Loop Fault 0.01000 0.00100 Figure 8 Complete System Current Loop 0.00010 3.6.2 Current Loop Compensation The compensation of the current loop is implemented at the ICOMP pin. This is OTA6 output and a capacitor CICOMP has to be installed at this node to ground (see Figure 8). Under normal mode of the operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of standby mode. 0.00001 0 18 37 55 73 91 110 128 146 165 183 201 219 238 256 PI digital output Figure 7 3.6 Power Transfer Curve Average Current Control The choke current is sensed through the voltage across the shunt resistor and averaged by the ICOMP pin capacitor so that the IC can control the choke current to track the instant variation of the input voltage. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous mode (CCM) to achieve the power factor correction. Assuming the loop voltage is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as: 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 8. It consists of the current loop block which averages the voltage at ISENSE pin resulted from the inductor current flowing across Rshunt. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C10 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. Version 3.0 DOFF=VIN/VOUT From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 9 shows the scheme to achieve the objective. 10 03 April 2017 CCM-PFC ICE3PCS01G Functional Description Ramp Profile immediately and maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 11. Ave(Iin) at ICOMP Current limit Latch R Q Toff _min 600ns Peak current limit Gate Drive t Figure 9 Current loop PWM on signal Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 4 (ICOMP). The PWM cycles starts with the Gate turn off for a duration of TOFFMIN (600ns typ.) and the ramp is kept discharged. The ramp is allowed to rise after the TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 10 shows the timing diagrams of the TOFFMIN and the gate waveforms. Figure 11 3.8 S Q PWM LOGIC System Protection 3.8.1 Input Voltage Brownout Protection(BOP) Brownout occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. ICE3PCS01G provides a new BOP feature whereby it senses directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network shown in Figure 12. This network provides a filtered value of VIN which turns the IC on when the voltage at pin 9 (BOP) is more than 1.25V. The IC enters into the fault mode when BOP goes below 1.0V. The hysteresis prevents the system to oscillate between normal and fault mode. Note also that the peak of VIN needs to be at least 20% of the rated VOUT in order to overcome OLP and powerup system. Toff _min 600 ns PWM Cycle VC,ref (1) Vram p Ramp Released GATE t (1) V c,ref is a function of V ICOMP 3.7 PWM on Latch R Q The IC provides numerous protection features in order to ensure the PFC system in safe operation. Clock Figure 10 High = turn on Gate S Q Ramp and PWM waveforms PWM Logic The PWM logic block prioritizes the control input signal and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 65kHz of operation. In case of high input currents which results in Peak Current Limitation, the GATE will be turned off Version 3.0 11 03 April 2017 CCM-PFC ICE3PCS01G Functional Description VSENSE pin with respect to a reference voltage of 2.7V. A VSENSE voltage higher than 2.7V will immediately turn off the gate, thereby preventing damage to bus capacitor. After bulk voltage falls below the rated value, gate drive resumes switching again. Line Filter 90 ~ 270 Vac D BRO2 D BRO1 3.8.5 Second Over Voltage Protection (OVP2) The second OVP is provided in case that the first one fails due to the aging or incorrect resistors connected to the VSENSE pin. This is implemented by sensing the voltage at pin OVP with respect to a reference voltage of 2.5V. When voltage at OVP pin is higher than 2.5V, the IC will immediately turn off the gate, thereby preventing damage to bus capacitor. When the bulk voltage drops out of the hysteresis the IC can be latched further or begin auto soft-start. These two protection modes are distinguished through detecting the external equivalent resistance connecting to VBTHL_EN pin after Vcc is higher than UVLO threshold as shown in Figure 3. If the equivalent resistance is higher than 100kΩ the IC selects latch mode for second OVP, otherwise auto soft-start mode. In normal operation the trigger level of second OVP should be designed higher than the first. However in the condition of mains transient overshoot the bulk voltage may be pulled up to the peak value of mains that is higher than the threshold of OVP1 and OVP2. In this case the OVP1 and OVP2 are triggered in the same time the IC will shut down the gate drive until bulk voltage falls out of the two protection hysteresis, then resume the gate drive again. R BRO1 1.25V C8b BOP R BRO2 Brownout Latch R Q Brownout S Q C BRO R BRO3 C8a 1V Figure 12 Input Brownout Protection 3.8.2 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 2 (ISENSE) reaches -0.2V. This voltage is amplified by a factor of 5 and connected to comparator with a reference voltage of 1.0V as shown in Figure 13. A deglitcher with 200ns after the comparator improves noise immunity to the activation of this protection. Full-wave rectifier ISENSE R CS 3.8.6 200ns AO2 Rshunt C5 Iin Bulk Voltage Monitor and Enable Function The IC monitors the bulk voltage through VSENSE pin and output a TTL signal to enable PWM IC or control inrush relay. During soft-start, once the bulk voltage is higher than 95% rated value, pin VB_OK outputs a high level. The threshold to trigger the low level is decided by the pin VBTHL_EN voltage which can be adjustable externally. When pin VBTHL_EN is pulled down externally lower than 0.5V, IC will enters into standby mode and most of the function blocks are turned off. When the disable signal is released the IC recovers by soft-start. G=-5 PCL 1V SGND Figure 13 Peak Current Limit (PCL) 3.8.3 Open Loop Protection (OLP) Whenever VSENSE voltage falls below 0.5V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. It is implemented using comparator C2a with a threshold of 0.5V as shown in the IC block diagram in Figure 6. 3.8.7 Boost Follower The IC provides adjustable lower bulk voltage in case of low line input and light output power. The low line condition is determined when pin BOP voltage is less than 2.3V. Pin BOFO is connected to PWM feedback voltage through a voltage divider, representing the output power. The light load condition is determined when pin BOFO voltage is less than 0.5V. Once these two conditions are met in the same time, a 20μA current source is flowing out of pin VSENSE so that the bulk voltage should be reduced to a lower level in order 3.8.4 First Over-Voltage Protection (OVP1) Whenever VOUT exceeds the rated value by 8%, the over-voltage protection OVP1 is active as shown in Figure 6. This is implemented by sensing the voltage at Version 3.0 12 03 April 2017 CCM-PFC ICE3PCS01G Functional Description to keep the VSENSE voltage same as the internal reference 2.5V as shown in Figure 14. VCC Reg (17V) D BRO2 RBRO1 RBRO2 DBRO1 VCC RBRO 3 R pullup R BOFO1 C BRO BOFO PWM Logic HIGH to turn on V DD BOP 90 ~ 270 Vac 2.3/ 2.5V C7 Blanking time L2H 34us H2L 1us C6 Blanking time H2L 4ms L2H 32ms VBulk 20uA RBVS 1 0.5V VSENSE Gate Driver LV Z1 R BVS 2 External MOS R BVS 3 R BOFO2 Opto. GATE R BOFO3 GND * LV: Level Shift Figure 14 Boost Follower Figure 15 Gate Driver The reduced bulk voltage can be designed by upper side resistance of voltage divider from pin VSENSE. Thus the low side resistance is designed by the voltage divider ratio from the reference 2.5V to the rated bulk voltage. A internal 300kΩ resistor will be paralleled with external low side resistor of BOFO pin to provide the adjustable hysteresis for PWM feedback voltage when boost follower is activated. The boost follower feature will be disabled internally during PFC soft-start in order to prevent bulk voltage oscillation due to the unstable PWM feedback voltage. This feature can also be disabled externally by pulling up pin BOFO higher than 0.5V continuously. 3.9 Output Gate Driver The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 13 (GATE) is typically clamped at 15V. The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state. Version 3.0 13 03 April 2017 CCM-PFC ICE3PCS01G Functional Description 3.10 Protection Function Description of Fault Fault-Type Min. Duration of Effect Consequence Voltage at Pin ISENSE < -200mV PCL 200 ns Gate Driver is turned off immediately during current switching cycle Voltage at Pin BOP < 1V BOP 20 μs Gate Driver is turned off. Soft-restart after BOP voltage > 1.25V Voltage at Pin VSENSE < 0.5V OLP 1 μs Power down. Soft-restart after VSENSE voltage > 0.5V Voltage at Pin VSENSE < 0.8V when boost follower is active OLP 1 μs Disable boost follower function. Voltage at Pin VSENSE > 108% of rated level OVP1 12 μs Gate Driver is turned off until VSENSE voltage < 2.5V. Voltage at Pin OVP > 2.5V and Voltage at Pin VSENSE > 108% of rated level OVP1 and OVP2 12 μs Gate Driver is turned off until bulk voltage drops out of both OVP hysteresis Voltage at Pin OVP > 2.5V OVP2 (latch mode) 12 μs Latched fault mode. Soft-restart after VCC UVLO Voltage at Pin OVP > 2.5V OVP2 (autorestart mode) 12 μs Gate Driver is turned off. Soft-restart after OVP voltage < 2.3V Voltage at Pin VBTHL_EN < 0.5V after VCC > 7V OVP2 mode 18 μs detection IC enters soft-restart mode after OVP2 released. Voltage at Pin VBTHL_EN > 0.5V after VCC > 7V OVP2 mode 18 μs detection IC enters latch mode after OVP2 released. Voltage at Pin VBTHL_EN < 0.5V when Vref outputs 5V Disable function Version 3.0 9 μs Power down. Soft-restart after disable signal is released. 14 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics 4 Electrical Characteristics All voltages are measured with respect to ground (pin 3). The voltage levels are valid if other ratings are not violated. 4.1 Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 12 (VCC) is discharged before assembling the application circuit. Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. VCC Supply Voltage VVCC -0.3 26 V GATE Voltage VGATE -0.3 17 V Clamped at 15V if driven internally. ISENSE Voltage VISENSE -20 5.3 V 1) mA ISENSE Current IISENSE -1 1 VSENSE Voltage VVSENSE -0.3 5.3 V VSENSE Current IVSENSE -1 1 mA V ICOMP Voltage VICOMP -0.3 5.3 FREQ Voltage VFREQ -0.3 5.3 V VREF Voltage VVREF -0.3 VVREF_0A V BOP Voltage VBOP -0.3 9.5 V 2) BOP Current IBOP -1 35 μA VB_OK Voltage VVB_OK -0.3 5.3 V VBTHL/EN Voltage VVBTHL -0.3 5.3 V BOFO Voltage VBOFO -0.3 5.3 V OVP Voltage VOVP -0.3 5.3 V Junction Temperature TJ -40 150 °C Storage Temperature TA,STO -55 150 °C Thermal Resistance RTHJA 140 K/W Soldering Temperature TSLD 260 °C Wave Soldering3) ESD Capability VESD 2 kV Human Body Model4) 1) 2) 3) 4) Junction to Air Absolute ISENSE current should not be exceeded Absolute BOP current should not be exceeded According to JESD22A111 According to EIA/JESD22-A114-B (discharging an 100 pF capacitor through an 1.5kΩ series resistor) Version 3.0 15 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Values Min. Unit Typ. VCC Supply Voltage @ 25°C VVCC VVCC,OFF 25 V Junction Temperature TJ -25 125 °C PFC switching frequency FPFC 21 100 kHz 4.3 Note: 4.3.1 Note / Test Condition Max. TJ=25°C Characteristics The electrical Characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -25 °C to 125 °C. Typical values represent the median values, which are related to 25 °C. If not otherwise stated, a supply voltage of VVCC = 18V, a typical switching frequency of ffreq=65kHz are assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not otherwise mentioned. Supply Section Parameter Symbol Limit Values Min. Unit Note/Test Condition Typ. Max. VCC Turn-On Threshold VCCon 11.5 12 12.9 V VCC Turn-Off Threshold/ Under Voltage Lock Out VCCUVLO 10.5 11.0 11.9 V VCC Turn-On/Off Hysteresis VCChy 0.7 1 1.45 V Start Up Current Before VCCon ICCstart1 - 380 700 μA VCCon-1.2V Start Up Current Before VCCon ICCstart2 - 1.4 2.4 mA VCCon-0.2V Operating Current with active GATE ICCHG - 6.7 9 mA CL= 1nF Operating Current during Standby ICCStdby - 3.5 4.7 mA VVSENSE= 0.4V VICOMP= 4V Version 3.0 16 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics 4.3.2 Variable Frequency Section Parameter Symbol Limit Values Min. Unit Test Condition Typ. Max. Switching Frequency (Typical) FSWnom 62.5 65 67.5 kHz R5 = 67kΩ Switching Frequency (Min.) FSWmin - 21 - kHz R5 = 212kΩ Switching Frequency (Max.) FSWmax - 100 - kHz R5 = 43kΩ Voltage at FREQ pin VFREQ - 1 - V Max. Duty Cycle Dmax 93 95 98.5 % 4.3.3 PWM Section Parameter Symbol Limit Values Min. Min. Duty Cycle DMIN Min. Off Time TOFFMIN 4.3.4 fSW=fSWnom (RFREQ=67kΩ) 310 Typ. 600 Unit Test Condition Max. 0 % VVSENSE= 2.5V VICOMP= 4.3V 920 ns VVSENSE= 2.5V VISENSE= 0V (R5 = 67kΩ) External Synchronization Parameter Symbol Values Min. Detection threshold of external clock Vthr_EXT Synchronization range fEXT_range Synchronization frequency ratio fEXT:fPFC propagation delay from rising edge of external clock to falling edge of PFC gate drive TEXT2GATE Allowable external duty on time TD_on Version 3.0 Typ. Unit 2.5 50 Note / Test Condition Max. V 100 kHz 500 ns 70 % 1:1 10 17 fEXT=65kHz 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics 4.3.5 PFC Brownout Protection Section Parameter Symbol Values Unit Min. Typ. Max. Input Brownout Protection High to Low Threshold VBOP_H2L 0.98 1 1.02 V Input Brownout Protection Low to High Threshold VBOP_L2H 1.2 1.25 1.3 V 0.5 μA Blanking time for BOP turn_on TBOPon Input Brownout Protection BOP Bias Current IBOP 4.3.6 μs 20 -0.5 - Symbol Values Unit Note / Test Condition Min. Typ. Max. Over Voltage Protection (OVP1) Low to High VOVP1_L2H 2.65 2.7 2.77 V Over Voltage Protection (OVP1) High to Low VOVP1_H2L 2.45 2.5 2.55 V Over Voltage Protection (OVP1) Hysteresis VOVP1_HYS 150 200 270 mV 108%VBULKRated μs Blanking time for OVP1 TOVP1 Over Voltage Protection (OVP2) Low to High VOVP2_L2H 2.45 2.5 2.55 V Over Voltage Protection (OVP2) High to Low IOVP2_H2L 2.25 2.3 2.35 V Blanking time for OVP2 TOVP2 12 OVP2 mode detection threshold VOVP2_mode 0.5 Current source for OVP2 mode detection1) IOVP2_mode Peak Current Limitation (PCL) ISENSE Threshold VPCL Blanking time for PCL turn_on TPCLon 4.3.7 VBOP=1.25V System Protection Section Parameter 1) Note / Test Condition 12 μs V comparator at VBTHL pin 4 5 6 μA current source at VBTHL pin -180 -200 -220 mV 200 ns The parameter is not subject to production test - verified by design/characterization Internal Voltage Reference Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 4.9 5 Output Reference Voltage VVREF_0A 5.1 V Load Regulation ΔVVREF_5mA 50 mV IVREF=-5mA1) Line Regulation ΔVVREF_VCC 25 mV ΔVCC=3V Version 3.0 18 IVREF=0mA 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics Parameter Symbol Values Min. Maximum Source Current IVREF Temperature Stability ΔVVREF_temp Total Variation VVREF_total 1) 4.3.8 Typ. Unit Note / Test Condition Max. -6 mA 1.0 4.85 % 5.2 Line, Load, Temperature Maximum pulling current depends on the maximum operating junction temperature Boost Follower Section Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. BOFO threshold VBOFO 0.47 0.5 0.53 V BOFO hysteresis resistor RBOFO_hys 240 300 360 kΩ Blanking time for BOFO on TBOFO_L2H 32 Blanking time for BOFO off TBOFO_H2L 4 High line detection threshold VLD_H 2.46 2.5 2.56 Low line detection threshold VLD_L 2.25 2.3 2.35 Blanking time for line detection TLD Current source for low step IBOFO 4.3.9 ms 20 V μs 32 18.7 V 21 μA Bulk Voltage Good Section Parameter Symbol Values Min. VB_OK turn-on threshold VVBOKon VB_OK turn-off threshold VVBOKoff Disable function threshold VVBTHL_EN Blanking time for disable function TVBTHL_EN VB_OK max source current IVB_OKMax 1) ms 2.25 Unit Note / Test Condition Typ. Max. 2.375 2.5 VVBTHL_EN 0.45 0.5 9 -11) 0.55 V sensed at pin VSENSE V set by pin VBTHL_EN V μs mA shared with the max source current of the VREF pin. Version 3.0 19 03 April 2017 CCM-PFC ICE3PCS01G Electrical Characteristics 4.3.10 Current Loop Section Parameter Symbol Values Min. OTA6 Transconductance Gain GmOTA6 OTA6 Output Linear Range1) IOTA6 ICOMP Voltage during OLP VICOMPF 1) 3.5 Unit Note / Test Condition Typ. Max. 5.0 6.35 4.8 5.0 mS At Temp = 25°C μA ± 50 5.2 V VVSENSE= 0.4V The parameter is not subject to production test - verified by design/characterization 4.3.11 Voltage Loop Section Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Trimmed Reference Voltage VVSREF 2.47 2.5 2.53 V Open Loop Protection (OLP) VSENSE Threshold VVS_OLP 0.45 0.5 0.55 V VSENSE Input Bias Current IVSENSE -1 - 1 μA 4.3.12 VVSENSE= 2.5V Driver Section Parameter GATE Low Voltage GATE High Voltage 4.3.13 ±1.2% Symbol Values Unit Note / Test Condition Min. Typ. Max. - - 1.2 V VCC =10V IGATE = 5 mA - 0.4 - V IGATE = 0 A - - 1.4 V IGATE = 20 mA -0.2 0.8 - V IGATE = -20 mA - 15 - V VCC = 25V CL = 1nF - 12.4 - V VCC = 15V CL = 1nF 8.0 - - V VCC = VVCCoff + 0.2V CL = 1nF VGATEL VGATEH Gate Drive Section Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. GATE Rise Time tr - 30 - ns VGate = 20% - 80% VGATEH CL = 1nF GATE Fall Time tf - 25 - ns VGate = 80% - 20% VGATEH CL = 1nF Version 3.0 20 03 April 2017 CCM-PFC ICE3PCS01G Outline Dimension 5 Outline Dimension PG-DSO-14 Outline Dimension 1.27 0.41 +0.1 -0.06 0.2 M 14 0.1 A C 14x -0.01 0.2 +0.05 C 8˚ MAX. 4 -0.2 1) 1.75 MAX. 0.1 MIN. (1.5) 0.33 ±0.08 x 45˚ 0.64 ±0.25 6 ±0.2 8 1 7 8.75 -0.2 1) A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side Notes: 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. 2. Dimensions in mm. Version 3.0 21 03 April 2017 CCM-PFC Revision History: Page 4/8/16/ 17 Datasheet Maximum switching frequency was changed to 100kHz Figure 4 Maximum switching frequency was changed to 100kHz Page 17 Maximum synchronization frequency was changed to 100kHz Edition 2017-04-03 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 05/05/10. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.