ICE5AR0680AGXUMA1

ICE5xRxxxxAG Fixed Frequency 700 V/800 V CoolSET™ - in DSO12 Package Product highlights  Integrated 700 V/ 800 V avalanche rugged CoolMOS™  Enhanced Active Burst Mode with selectable entry and exit standby power to reach the lowest standby power Tjcon_OT P 50 µs Blanking time S R VVCC_OVP NonIsolated Detector OTP Mode C20 tVCC_OVP_B Tj < Tjcon_OTP-TjHYS_OTP Autorestart Protect CoolMOSTM fOSC_2 OSC with Jitter and Frequency Reduction Error Amplifier Q R Autorestart Protect DRAIN fOSC OSC D1 VERR ERR VERR_REF Gate Driver VREF RFB Burst Mode detect Gate Drive Protection and PWM Digital Control Overload Protection VFB_OLP/ VFB_LB C12 Gate Drive GND tFB_OLP_B VCS_BLP VCS_BHP C13 FB Active Burst Block C9 25kΩ No burst VCS_Nx C15 tFB_BEB Active Burst Mode 2pF V1 CPWM PWM Comparator Leading Edge Blanking tCS_LEB 10kΩ 1pF CS D2 C15a C10 Soft-start VFB_BOn PWM OP VPWM Delay tCS_STG GPWM C11 VFB_BOff Slope Comp Peak current limit Burst Mode Level Select VFB_EBHP VFB_EBLP VREF Current Mode C19 VCS_STG Slope Compensation/Current Limiting Figure 4 Representative block diagram Note: Junction temperature of the controller chip is sensed for over temperature protection. The CoolMOSTM is a separate chip from the controller chip in the same package. Please refer to the design guide and/or consult a technical expert for the proper thermal design. Datasheet 7 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3 Functional description 3.1 VCC pre-charging and typical VCC voltage during start-up As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor CBUS. The pull up resistor RSTARTUP provides a current to charge the Ciss (input capacitance) of CoolMOS™ and gradually generate one voltage level. If the voltage over Ciss is high enough, CoolMOS™ on and VCC capacitor will be charged through primary inductance of transformer LP, CoolMOS™ and internal diode D1 with two steps constant current source IVCC_ Charge11 and IVCC_ Charge31. A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to protect the controller from VCC pin short to ground during the start up. After this, the second step constant current source (IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold VVCC_ON. As shown in the time phase I in Figure 5, the VCC voltage increase almost linearly with two steps. VVCC II I VVCC_ON III VVCC_OFF tA tB VVCC_SCP t IVCC IVCC_Normal t 0 IVCC_Charge1 IVCC_Charge2/3 -IVCC Figure 5 t1 t2 VCC voltage and current at startup The time taking for the VCC pre-charging can then be approximately calculated as: 𝑡1 = 𝑡A + 𝑡B = 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ∙ 𝐶𝑉𝐶𝐶 (𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ) ∙ 𝐶𝑉𝐶𝐶 + 𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1 𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3 (1) When the VCC voltage exceeds the VCC turn on threshold VVCC_ON at time t1, the IC begins to operate with soft-start. Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage drops (Phase II). Once the output voltage rises close to regulation, the auxiliary winding starts to charge the VCC capacitor from the time t2 onward and delivering the IVCC_ Normal2 to the CoolSET™. The VCC then will reach a constant value depending on output load. 1 2 IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation Datasheet 8 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3.2 Soft-start As shown in Figure 6, the IC begins to operate with a soft-start at time ton. The switching stresses on the power MOSFET, diode and transformer are minimized during soft-start. The soft-start implemented in ICE5xRxxxxAG is a digital time-based function. The preset soft-start time is tSS (12 ms) with 4 steps. If not limited by other functions, the peak voltage on CS pin will increase step by step from 0.3 V to VCS_N (0.8 V) finally. The normal feedback loop will take over the control when the output voltage reaches its regulated value. Figure 6 Maximum current sense voltage during soft start 3.3 Normal operation The PWM controller during normal operation consists of a digital signal processing circuit including regulation control and an analog circuit including a current measurement unit and a comparator. Details about the full operation of the CoolSET™ in normal operation are illustrated in the following paragraphs. 3.3.1 PWM operation and peak current mode control 3.3.1.1 Switch-on determination The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency fSW that corresponds to the voltage level VFB (see Figure 8). 3.3.1.2 Switch-off determination In peak current mode control, the PWM comparator monitors voltage V1 (see Figure 4) which is the representation of the instantaneous current of the power MOSFET. When V1 exceeds VFB, the PWM comparator sends a signal to switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is controlled by the feedback voltage VFB (see Figure 7). At switch on transient of the power MOSFET, a voltage spike across RCS can cause V1 to increase and exceed VFB. To avoid a false switch off, the IC has a blanking time tCS_LEB before detecting the voltage across RCS to mask the voltage spike. Therefore, the minimum turn on time of the power MOSFET is tCS_LEB. For some reason that the voltage level at V1 takes long time to exceed VFB, the IC has implemented a maximum duty cycle control to force the power MOSFET to switch off when DMAX = 0.75 is reached. Datasheet 9 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description Figure 7 Pulse width modulation 3.3.2 Current sense The power MOSFET current generates a voltage VCS across the current sense resistor RCS connected between the CS pin and the GND pin. VCS is amplified with gain GPWM, then, added with an offset VPWM to become V1 as described below in below equation 3. 𝑉CS = 𝐼D × 𝑅CS (2) 𝑉1 = 𝑉CS ∗ 𝐺PWM + 𝑉PWM (3) where, VCS : CS pin voltage ID : power MOSFET current RCS : resistance of the current sense resistor V1 : voltage level compared to VFB as described in section 3.3.1.2 GPWM : PWM-OP gain VPWM : offset for voltage ramp If the voltage at the current sense pin is lower than the preset threshold VCS_STG after the time tCS_STG_SAM for three consecutive pulses during on-time of the power switch, this abnormal VCS will trigger IC into auto restart mode. Datasheet 10 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3.3.3 Frequency reduction Frequency reduction is implemented in ICE5xRxxxxAG to achieve a better efficiency during the light load. At light load, the reduced switching frequency FSW improves efficiency by reducing the switching loses. When load decreases, VFB decreases as well. FSW is dependent on the VFB as shown in Figure 8. Therefore, FSW decreases as the load decreases. Typically, FSW at high load is 100 kHz/ 125 kHz and starts to decrease at VFB = 1.7V. There is no further frequency reduction once it reached the fOSCx_MIN even the load is further reduced. fSW(VFB) VCS (VFB) Vcs VCS_N 0.80 V Fsw fOSC2 / fOSC4 125 kHz / 100 kHz fOSC2_ABM / fOSC4_ABM 103 kHz / 83 kHz fOSC2_MIN / fOSC4_MIN 53 kHz / 43 kHz BM No B M BM VCS_BHP / VCS_BLP 0.27 V /0.22 V No B M 0.5 V VFB_EBxP 0.93 / 1.03 V Figure 8 Frequency reduction curve 3.3.4 Slope compensation 1.35 V 1.7 V VFB_OLP 2.73 V VFB ICE5xRxxxxAG can operate at Continuous Conduction Mode (CCM). At CCM operation, duty cycle greater than 50% may generate a sub-harmonic oscillation. To avoid the sub-harmonic oscillation, slope compensation is added to VCS pin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle period. The relationship between VFB and the VCS for CCM operation is described in below equation 4: 𝑉FB = 𝑉CS ∗ 𝐺PWM + 𝑉PWM + 𝑀COMP ∗ (𝑇ON − 40% ∗ 𝑇PERIOD ) where, TON MCOMP (4) : gate turn on time of the power MOSFET : slope compensation rate TPERIOD : switching cycle period Slope compensation circuit is disabled and no slope compensation is added into the VCS pin during active burst mode to save the power consumption. Datasheet 11 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3.3.5 Oscillator and frequency jittering The oscillator generates a frequency of 100 kHz/ 125 kHz with frequency jittering of ±4% at a jittering period of TJITTER (4 ms). The frequency jittering helps to reduce conducted EMI. A capacitor, a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a highly accurate switching frequency. Once the soft-start period is over and when the IC goes into normal operating mode, the frequency jittering is enabled. There is also frequency jittering during frequency reduction. 3.3.6 Modulated gate drive The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the CoolMOS™ turn on threshold. That is a slope control of the rising edge at the output of driver (see Figure 9). Thus the leading switch spike during turn on is minimized. Figure 9 Gate rising waveform 3.4 Peak current limitation There is a cycle by cycle peak current limitation realized by the current limit comparator to provide primary over-current protection. The primary current generates a voltage VCS across the current sense resistor RCS connected between the CS pin and the GND pin. If the voltage VCS exceeds an internal voltage limit VCS_N, the comparator immediately turns off the gate drive. The primary peak current IPEAK_PRI can be calculated as below: (5) 𝐼PEAK_PRI = 𝑉CS_N⁄𝑅CS To avoid mistriggering caused by MOSFET switch on transient voltage spikes, a leading edge blanking time (tCS_LEB) is integrated in the current sensing path. 3.4.1 Propagation delay compensation In case of overcurrent detection, there is always a propagation delay from sensing the VCS to switching the power MOSFET off. An overshoot on the peak current Ipeak caused by the delay depends on the ratio of dI/dt of the primary current (see Figure 10). Datasheet 12 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description Figure 10 Current limiting The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold VCS_N and the switching off of the power MOSFET is compensated over wide bus voltage range. Current limiting becomes more accurate which will result in a minimum difference of overload protection triggering power between low and high AC line input voltage. Under CCM operation, the same VCS do not result in the same power. In order to achieve a close overload triggering level for CCM, ICE5xRxxxxAG has implemented a 2 compensation curve as shown Figure 11. One of the curve is used for TON greater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle. Figure 11 Dynamic voltage threshold VCS_N Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced level. With this implementation, the entry and exit burst mode power can be close between low and high AC line input voltage. Datasheet 13 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3.5 Active Burst Mode (ABM) with selectable power level At light load condition, the IC enters ABM operation to minimize the power consumption. Details about ABM operation are explained in the following paragraphs. 3.5.1 Entering ABM operation The sytem will enter into ABM operation when two conditions below are met:  the FB voltage is lower than the threshold of VFB_EBLP/VFB_EBHP depending on burst configuration option setup  and a certain blanking time tFB_BEB Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This multi-condition determination for entering ABM operation prevents mis-triggering of entering ABM operation, so that the controller enters ABM operation only when the output power is really low. 3.5.2 During ABM operation After entering ABM, the PWM section will be inactive making the VOUT start todecrease. As the VOUT decreases, VFB rises. Once VFB exceeded VFB_BOn, the internal circuit is again activated by the internal bias to start with the switching. If the PWM is still operating and the output load is still low, VOUT increases and VFB signal starts to decrease. When VFB reaches the low threshold VFB_BOff, the internal bias is reset again and the PWM section is disabled with no switching until VFB increases back to exceed VFB_BOn threshold. In ABM, VFB is like a sawtooth waveform swinging between VFB_BOff and VFB_BOn shown in Figure 12. During ABM, the switching frequency fOSCx_ABM is 83 kHz for 100 kHz version and 103 kHz for 125 kHz version IC. The peak current IPEAK_ABMof the power MOSFET is defined by: (6) 𝐼PEAK_ABM = 𝑉CS_BxP⁄𝑅CS where VCS_BxP is the peak current limitation in ABM 3.5.3 Leaving ABM operation The FB voltage immediately increases if there is a sudden increase in the output load. When VFB exceeds VFB_LB, it will leave ABM and the peak current limitation trhreshold voltage will return back to VCS_N immediately. Datasheet 14 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description VFB Entering Active Burst Mode VFB_LB Leaving Active Burst Mode VFB_BOn VFB_BOff VFB_EBHP/VFB_EBLP Blanking Window (tFB_BEB) t VCS VCS_N Current limit level during Active Burst Mode VCS_BHP/VCS_BLP t VVCC VVCC_off t VO Max. Ripple < 1% t Burst Mode Operation Figure 12 Datasheet Signals in Active Burst Mode 15 of 42 V 2.3 2020-02-03 Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package Functional description 3.5.4 ABM configuration The burst mode entry level can be selected by changing the different resistance RSel at FB pin. There are 3 configuration options depending on RSel which corresponds to the options of no ABM (Option 1), low range of ABM power (Option 2) and high range of ABM power (Option 3). The table below shows the control logic for the entry and exit level with the FB voltage. Table 3 ABM configuration option setup Entry level Exit level VFB_EBxP VFB_LB - No ABM No ABM VFB_P_BIAS1