IFX54441
Wide Input Range Low Noise 300mA LDO
Data Sheet
Rev. 1.1, 2014-10-30
Standard Power
Wide Input Range Low Noise 300mA LDO
1
IFX54441
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low Noise down to 24 µVRMS (BW = 10 Hz to 100 kHz)
300mA Current Capability
Low Quiescent Current: 30 µA
Wide Input Voltage Range: 1.8 V to 20 V
2.5% Output Voltage Accuracy (over full temperature and load range)
Low Dropout Voltage: 270 mV
Very low Shutdown Current: < 1µA
No Protection Diodes Needed
Fixed Output Voltage: 3.3V
Adjustable Version with Output from 1.22V to 20V
Stable with ≥ 3.3 µF Output Capacitor
Stable with Aluminium, Tantalum or Ceramic Capacitors
Reverse Battery Protection
No Reverse Current
Overcurrent and Overtemperature Protected
DSO-8 Exposed Pad and TSON-10 Exposed Pad packages
Green Product (RoHS compliant)
PG-DSO-8 Exposed Pad
PG-TSON-10
Applications
•
•
•
•
•
Microcontroller Supply
Battery-Powered Systems
Noise Sensitive Instruments
Radar Applications
Image Sensors
The IFX54441 is not qualified and manufactured according to the requirements of Infineon Technologies with
regards to automotive and/or transportation applications. For automotive applications please refer to the Infineon
TLx (TLE, TLS, TLF.....) voltage regulator products.
Type
Package
Marking
IFX54441EJV
PG-DSO-8 Exposed Pad
54441EV
IFX54441EJV33
PG-DSO-8 Exposed Pad
54441E33
IFX54441LDV
PG-TSON-10
544LV
IFX54441LDV33
PG-TSON-10
544L33
Data Sheet
2
Rev. 1.1, 2014-10-30
IFX54441
Overview
The IFX54441 is a micropower, low noise, low dropout voltage regulator. The device is capable of supplying an
output current of 300 mA with a dropout voltage of 270 mV. Designed for use in battery-powered systems, the low
quiescent current of 30 µA makes it an ideal choice.
A key feature of the IFX54441 is its low output noise. By adding an external 0.01 µF bypass capacitor output noise
values down to 24 µVRMS over a 10 Hz to 100 kHz bandwidth can be reached. The IFX54441 voltage regulator is
stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the series
resistance required by many other regulators. Its internal protection circuitry includes reverse battery protection,
current limiting and reverse current protection. The IFX54441 comes as fixed output voltage 3.3V as well as
adjustable device with a 1.22 V reference voltage. It is available in a DSO-8 Exposed Pad and as well as in a
TSON-10 Exposed Pad package.
Data Sheet
3
Rev. 1.1, 2014-10-30
IFX54441
Block Diagram
2
Block Diagram
Note: Pin numbers in the block diagrams refer to the DSO-8 EP package type.
Saturation
Control
IFX54441
IN 8
1 OUT
EN 5
Bias
BYP 4
Voltage
reference
Over Current
Protection
Temperature
Protection
Error
Amplifier
2
SENSE
6
GND
Figure 1
Block Diagram IFX54441 fixed voltage version
Saturation
Control
IFX54441 ADJ
IN 8
1 OUT
EN 5
Bias
BYP 4
Voltage
reference
Over Current
Protection
Temperature
Protection
Error
Amplifier
2 ADJ
6
GND
Figure 2
Data Sheet
Block Diagram IFX54441 adjustable version
4
Rev. 1.1, 2014-10-30
IFX54441
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
OUT
1
8
IN
OUT
1
8
IN
SENSE
2
7
NC
ADJ
2
7
NC
NC
3
6
GND
NC
3
6
GND
BYP
4
BYP
4
5
EN
9
9
5
EN
IFX54441 EJ V33
Figure 3
IFX54441 EJ V
Pin Configuration of IFX54441 in PG-DSO-8 Exposed Pad for fixed voltage and adjustable
version
OUT
OUT
NC
SENSE
BYP
1
2
3
4
5
11
10
9
8
7
6
OUT
OUT
NC
ADJ
BYP
IN
IN
NC
EN
GND
IFX54441LD V33
Figure 4
Data Sheet
1
2
3
4
5
11
10
9
8
7
6
IN
IN
NC
EN
GND
IFX54441LD V
Pin Configuration of IFX54441 in TSON10 for fixed voltage and adjustable version
5
Rev. 1.1, 2014-10-30
IFX54441
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1 (DSO-8 EP)
1,2 (TSON-10)
OUT
Output. Supplies power to the load. For this pin a minimum output capacitor of
3.3 µF is required to prevent oscillations. Larger output capacitors may be
required for applications with large transient loads in order to limit peak voltage
transients or when the regulator is applied in conjunction with a bypass capacitor.
For more details please refer to the section “Application Information” on
Page 24.
2 (DSO-8 EP)
4 (TSON-10)
SENSE
Output Sense. For the fixed voltage version the SENSE pin is the input to the
(fix voltage error amplifier. This allows to achieve an optimized regulation performance in
version)
case of small voltage drops Rp that occur between regulator and load. In
applications where such drops are relevant they can be eliminated by connecting
the SENSE pin directly at the load. In standard configuration the SENSE pin can
be connected directly to the OUT pin. For further details please refer to the section
“Kelvin Sense Connection” on Page 25.
2 (DSO-8 EP)
4 (TSON-10)
Adjust. For the adjustable version the ADJ pin is the input to the error amplifier.
ADJ
(adjustable The ADJ pin voltage is 1.22V referenced to ground and allows a output voltage
range from 1.22V to 20V - VDR. The ADJ pin is internally clamped to ±7 V. Please
version)
note that the bias current of the ADJ pin is flowing into the pin.1)
3, 7 (DSO-8 EP) NC
3, 8 (TSON-10)
No Connect. The NC Pins have no connection to any internal circuitry. Connect
either to GND or leave open.
4 (DSO-8)
5 (TSON-10)
BYP
Bypass. The BYP pin is used to bypass the reference of the IFX54441 to achieve
low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e. one VBE).
A small capacitor from the output to the BYP pin will bypass the reference to lower
the output voltage noise2). If not used this pin must be left unconnected.
5 (DSO-8 EP)
7 (TSON-10)
EN
Enable. With the EN pin the IFX54441 can be put into a low power shutdown
state. The output will be off when the EN is pulled low. The EN pin can be driven
by 5V logic or open-collector logic with pull-up resistor. The pull-up resistor is
required to supply the pull-up current of the open-collector gate3) and the EN pin
current4). Please note that if the EN pin is not used it must be connected to VIN. It
must not be left floating.
6 (DSO-8 EP)
6,(TSON-10)
GND
Ground. For the ADJ version connect the bottom of the output voltage setting
resistor divider directly to the GND pin for optimum load regulation performance.
8 (DSO-8 EP)
IN
9, 10 (TSON-10)
Input. Via the input pin IN the power is supplied to the device. A capacitor at the
input pin is required if the device is more than 6 inches away from the main input
filter capacitor or if non-negligible inductance is present at the IN pin5). The
IFX54441 is designed to withstand reverse voltages on the Input pin with respect
to GND and Output. In the case of reverse input (e.g. due to a wrongly attached
battery) the device will act as if there is a diode in series with its input. In this way
there will be no reverse current flowing into the regulator and no reverse voltage
will appear at the load. Hence, the device will protect both - the device itself and
the load.
9 (DSO-8 EP)
11 (TSON-10)
Exposed Pad. To ensure proper thermal performance, solder Pin 11 (exposed
pad) of TSON10 to the PCB ground and tie directly to Pin 6. In the case of DSO8 EP as well solder Pin 9 (exposed pad) to the PCB ground and tie directly to Pin
6.
Data Sheet
Tab
6
Rev. 1.1, 2014-10-30
IFX54441
Pin Configuration
1) The typical value of the ADJ pin bias current is 60 nA with a very good temperature stability.See also the corresponding
Typical Performance Graph “Adjust Pin Bias current IADJ versus Junction Temperature TJ” on Page 20.
2) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.
3) Normally several microamperes.
4) Typical value is 1 µA.
5) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.
Data Sheet
7
Rev. 1.1, 2014-10-30
IFX54441
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Unit
Note /
Number
Test Condition
Min.
Typ.
Max.
-20
–
20
V
–
P_4.1.1
VOUT
-20
VIN - VOUT -20
–
20
V
–
P_4.1.2
–
20
V
–
P_4.1.3
VSENSE
-20
–
20
V
–
P_4.1.4
VADJ
-7
–
7
V
–
P_4.1.5
VBYP
-0.6
–
0.6
V
VEN
-20
–
20
V
–
P_4.1.7
Tj
Tstg
-40
–
150
°C
–
P_4.1.8
-55
–
150
°C
–
P_4.1.9
VESD
VESD
-2
–
2
kV
HBM2)
P_4.1.10
kV
3)
P_4.1.11
Input Voltage
Voltage
VIN
Output Voltage
Voltage
Input to Output Differential
Voltage
Sense Pin
Voltage
ADJ Pin
Voltage
BYP Pin
Voltage
P_4.1.6
Enable Pin
Voltage
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
All Pins
All Pins
-1
–
1
CDM
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
8
Rev. 1.1, 2014-10-30
IFX54441
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Input Voltage Range
(3.3 V voltage version)
VIN
3.8 V
–
20
V
–
P_4.2.1
Input Voltage Range
(adjustable voltage version)
VIN
2.3
–
20
V
–1)
P_4.2.2
Operating Junction Temperature
Tj
-40
–
125
°C
–
P_4.2.3
1) For the IFX54441 adjustable version the minimum limit of the functional range VIN is tested and specified with the ADJ- pin
connected to the OUT pin.
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 3
Thermal Resistance1)
Parameter
Symbol
Values
Min.
Typ.
Max.
–
7.0
–
Junction to Ambient
RthJC
RthJA
RthJA
RthJA
–
66
–
Junction to Ambient
RthJA
–
52
–
6.4
Junction to Ambient
RthJC
RthJA
RthJA
RthJA
Junction to Ambient
RthJA
Unit
Note /
Test Condition
Number
K/W
–
P_4.3.1
IFX54441 EJ (PG-DSO8 Exposed Pad)
Junction to Case
Junction to Ambient
Junction to Ambient
–
–
39
155
–
–
K/W
K/W
–
2)
P_4.3.2
Footprint only
3)
P_4.3.3
K/W
2
300 mm heatsink
area on PCB3)
P_4.3.4
–
K/W
600 mm2 heatsink
area on PCB3)
P_4.3.5
–
K/W
–
P_4.3.6
IFX54441 LD (PG-TSON10)
Junction to Case
Junction to Ambient
Junction to Ambient
–
53
–
K/W
–
2)
P_4.3.7
3)
–
183
–
K/W
Footprint only
–
69
–
K/W
300 mm2 heatsink
area on PCB3)
P_4.3.8
P_4.3.9
–
57
–
K/W
600 mm2 heatsink
area on PCB3)
P_4.3.10
1) Not subject to production test, specified by design.
Data Sheet
9
Rev. 1.1, 2014-10-30
IFX54441
General Product Characteristics
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70 µm Cu).
Data Sheet
10
Rev. 1.1, 2014-10-30
IFX54441
Electrical Characteristics
5
Electrical Characteristics
5.1
Electrical Characteristics Table
Table 4
Electrical Characteristics
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
VIN,min
–
1.8
2.3
V
IOUT = 300 mA1)2)3)
P_5.1.1
IFX54441EJ V33
IFX54441LD V33
VOUT
3.220
3.30
3.380
V
1 mA < IOUT < 300 mA,
4.3 V < VIN < 20 V
P_5.1.2
IFX54441EJV
IFX54441LDV
VOUT
1.190
1.22
1.250
V
1m A < IOUT < 300 mA;
2.3 V < VIN < 20 V3)
P_5.1.3
IFX54441EJ V33
IFX54441LD V33
∆VOUT
–
1
20
mV
P_5.1.4
IFX54441EJ V
IFX54441LD V
∆VOUT
–
1
20
mV
∆VIN = 3.8 V to 20 V;
IOUT = 1 mA
∆VIN = 2.0 V to 20 V;
IOUT = 1 mA3)
IFX54441EJV33
IFX54441LDV33
∆VOUT
–
6
15
mV
IFX54441EJV33
IFX54441LDV33
∆VOUT
–
–
28
mV
IFX54441EJV
IFX54441LDV
∆VOUT
–
3
8
mV
IFX54441EJV
IFX54441LDV
∆VOUT
–
–
12
mV
Dropout Voltage
VDR
–
100
130
mV
Dropout Voltage
VDR
–
–
190
mV
Dropout Voltage
VDR
–
150
190
mV
Dropout Voltage
VDR
–
–
250
mV
Dropout Voltage
VDR
–
190
220
mV
Dropout Voltage
VDR
–
–
300
mV
Dropout Voltage
VDR
–
270
300
mV
Minimum Operating Voltage
4)
Output Voltage
Line Regulation
P_5.1.5
Load Regulation
TJ = 25°C;VIN = 4.3 V;
∆ IOUT = 1 to 300 mA
VIN = 4.3 V;
∆ IOUT = 1 to 300 mA
TJ = 25°C; VIN = 2.3 V;
∆IOUT = 1 to 300 mA3)
VIN = 2.3 V;
∆IOUT = 1 to 300 mA3)
P_5.1.6
P_5.1.7
P_5.1.8
P_5.1.9
Dropout Voltage2)5)6)
Data Sheet
11
IOUT = 10 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 10 mA;
VIN = VOUT,nom
IOUT = 50 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 50 mA;
VIN = VOUT,nom
IOUT = 100 mA;
VIN = VOUT,nom; TJ = 25°C
IOUT = 100 mA;
VIN = VOUT,nom
IOUT = 300 mA;
VIN = VOUT,nom; TJ = 25°C
P_5.1.10
P_5.1.11
P_5.1.12
P_5.1.13
P_5.1.14
P_5.1.15
P_5.1.16
Rev. 1.1, 2014-10-30
IFX54441
Electrical Characteristics
Table 4
Electrical Characteristics (cont’d)
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
VDR
–
–
400
mV
IOUT = 300 mA;
VIN = VOUT,nom
P_5.1.17
GND Pin Current
IGND
–
30
60
µA
P_5.1.18
GND Pin Current
IGND
–
50
100
µA
GND Pin Current
IGND
–
300
850
µA
GND Pin Current
IGND
–
0.7
2.2
mA
GND Pin Current
IGND
–
4
12
mA
–
0.1
1
µA
VIN = VOUT,nom;
IOUT = 0 mA
VIN = VOUT,nom;
IOUT = 1 mA
VIN = VOUT,nom;
IOUT = 50 mA
VIN = VOUT,nom;
IOUT = 100 mA
VIN = VOUT,nom;
IOUT = 300 mA
VIN = 6 V; VEN = 0 V;
TJ = 25°C
Vth,EN
Vtl,EN
IEN
IEN
–
0.8
2.0
V
P_5.1.24
0.25
0.65
–
V
–
0.01
–
µA
–
1
–
µA
VOUT = Off to On
VOUT = On to Off
VEN = 0 V; TJ = 25°C
VEN = 20 V; TJ = 25°C
Ibias,ADJ
–
60
–
nA
TJ = 25°C
eno
–
41
–
µVRMS COUT = 10 µF ceramic;
CBYP = 10 nF;
IOUT = 300 mA;
Dropout Voltage
GND Pin Current5)7)
Quiescent Current in Off-Mode Iq
(EN-pin low)
P_5.1.19
P_5.1.20
P_5.1.21
P_5.1.22
P_5.1.23
Enable
Enable Threshold High
Enable Threshold Low
EN Pin Current
8)
EN Pin Current8)
P_5.1.25
P_5.1.26
P_5.1.27
9)11)
Adjust Pin Bias Current
ADJ Pin Bias Current
P_5.1.28
11)
Output Voltage Noise
Output Voltage Noise
IFX54441EJV10)
IFX54441LDV10)
P_5.1.29
(BW = 10Hz to100kHz)
Output Voltage Noise
IFX54441EJV10)
IFX54441LDV10)
eno
Output Voltage Noise
IFX54441EJV10)
IFX54441LDV10)
eno
–
28
–
µVRMS COUT = 10 µF ceramic
P_5.1.30
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 300 mA;
(BW = 10 Hz to100 kHz)
–
29
–
µVRMS COUT = 22 µF ceramic;
CBYP = 10 nF;
IOUT = 300 mA;
P_5.1.31
(BW = 10 Hz to100 kHz)
Output Voltage Noise
IFX54441EJV10)
IFX54441LDV10)
Data Sheet
eno
–
24
–
µVRMS COUT = 22 µF ceramic
P_5.1.32
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 300 mA;
(BW = 10 Hz to100 kHz)
12
Rev. 1.1, 2014-10-30
IFX54441
Electrical Characteristics
Table 4
Electrical Characteristics (cont’d)
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
eno
Output Voltage Noise
IFX54441EJV33
IFX54441LDV33
Values
Unit
Min.
Typ.
Max.
–
45
–
Note / Test Condition
Number
µVRMS COUT = 10 µF ceramic;
CBYP = 10 nF;
IOUT = 300 mA;
P_5.1.33
(BW = 10 Hz to100 kHz)
Output Voltage Noise
IFX54441EJV33
IFX54441LDV33
eno
Output Voltage Noise
IFX54441EJV33
IFX54441LDV33
eno
–
35
–
µVRMS COUT = 10 µF ceramic
P_5.1.34
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 300 mA;
(BW = 10 Hz to100 kHz)
–
33
–
µVRMS COUT = 22 µF ceramic;
CBYP = 10 nF;
IOUT = 300 mA;
P_5.1.35
(BW = 10 Hz to100 kHz)
eno
Output Voltage Noise
IFX54441EJV33
IFX54441LDV33
–
30
–
µVRMS COUT = 22 µF ceramic
P_5.1.36
+250mΩ resistor in series;
CBYP = 10 nF;
IOUT = 300 mA;
(BW = 10 Hz to100 kHz)
11)
Power Supply Ripple Rejection
Power Supply Ripple
Rejection
PSRR
–
65
–
dB
VIN - VOUT = 1.5 V (avg);
VRIPPLE = 0.5 Vpp;
fr = 120 Hz;
IOUT = 300 mA
P_5.1.37
IOUT,limit
IOUT,limit
320
–
–
mA
–
–
mA
VIN = 7 V; VOUT = 0 V
VIN = VOUT,nom + 1 V or
P_5.1.38
320
Output Current Limitation
Output Current Limit
Output Current Limit
P_5.1.39
12)
2.3V ;
∆VOUT = -0.1 V
Input Reverse Leakage Current
Ileak,rev
–
–
1
mA
VIN = -20 V; VOUT = 0 V
P_5.1.40
Fixed Voltage Versions
IReverse
–
10
20
µA
P_5.1.41
Adjustable Voltage Version
IReverse
–
5
10
µA
VOUT = VOUT,nom;
VIN < VOUT,nom;
TJ = 25°C
VOUT = 1.22 V;
VIN < 1.22 V; TJ = 25°C3)
Input Reverse Leakage
Reverse Output Current
Data Sheet
13)
13
P_5.1.42
Rev. 1.1, 2014-10-30
IFX54441
Electrical Characteristics
Table 4
Electrical Characteristics (cont’d)
-40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter
Symbol
Values
Unit
Note / Test Condition
Number
Min.
Typ.
Max.
3.3
–
–
µF
CBYP = 0 nF
P_5.1.43
14)
–
3
Ω
–
P_5.1.44
11)
Output Capacitor
Output Capacitance
ESR
COUT
ESR
–
1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum output
current of 300 mA. Due to the nominal output voltage of 3.3 V of the fixed voltage version or depending on the chosen
setting of the external voltage divider as well as on the applied conditions the device may either regulate its nominal output
voltage or it may be in tracking mode. For further details please also refer to the VOUT specification in Table 4.
2) For the IFX54441EJV and IFX54441LDV adjustable versions the dropout voltage for certain output voltage / load
conditions will be restricted by the minimum input voltage specification.
3) The adjustable versions of the IFX54441 are tested and specified for these conditions with the ADJ pin connected to the
OUT pin.
4) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will
only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all
possible combinations of input voltage and output current at a given output voltage. When operating at maximum input
voltage, the output current must be limited for thermal reasons. The same holds true when operating at maximum output
current where the input voltage range must be limited for thermal reasons.
5) To satisfy requirements for minimum input voltage, the adjustable version of the IFX54441 is tested and specified for these
conditions with an external resistor divider (two 250 kΩ resistors) for an output voltage of 2.44 V. The external resistors will
add a 5 µA DC load on the output.
6) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output
current. In dropout, the output voltage will be equal to VIN - VDR.
7) GND-pin current is tested with VIN = VOUT,nom or VIN = 2.3 V, whichever is greater, and a current source load. This means
that this parameter is tested while being in dropout condition and thus reflects a worst case condition. The GND-pin current
will in most cases decrease slightly at higher input voltages - please also refer to the corresponding typical performance
graphs.
8) The EN pin current flows into EN pin.
9) The ADJ pin current flows into ADJ pin.
10) ADJ pin connected to OUT pin.
11) Not subject to production test, specified by design.
12) whichever of the two values of VIN is greater in order to also satisfy the requirements for VIN,min.
13) Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current
flows into the OUT pin and out of the GND pin.
14) CBYP = 0 nF, COUT ≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used - depending on the actual
applied capacitance of COUT and CBYP - a minimum requirement for ESR may apply. For further details please also refer
to the corresponding typical performance graph.
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specified mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA = 25 °C and the given supply voltage.
Data Sheet
14
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
6
Typical Performance Characteristics
Dropout Voltage VDR versus
Output Current IOUT
Guaranteed Dropout Voltage VDR versus
Output Current IOUT
500
500
450
450
400
400
350
350
300
300
VDR [mV]
VDR [mV]
Δ = Guaranteed Limits
250
250
200
200
150
150
100
100
Tj = −40 °C
Tj = 25 °C
50
Tj ≤ 25 °C
50
Tj = 125 °C
0
0
50
100
150
IOUT [A]
200
250
Dropout Voltage VDR versus
Junction Temperature TJ
Tj ≤ 125 °C
0
300
0
50
100
150
IOUT [A]
200
250
300
Quiescent Current versus
Junction Temperature TJ
500
50
IOUT = 10 mA
450
IOUT = 100 mA
40
IOUT = 300 mA
350
35
300
30
Iq [µA]
VDR [mV]
400
45
IOUT = 50 mA
250
25
200
20
150
15
100
10
50
5
0
−50
Data Sheet
0
50
Tj [°C]
0
−50
100
15
VIN = 6 V
IOUT = 0 mA .
VEN = VIN
0
50
Tj [°C]
100
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
Output Voltage VOUT versus
Junction Temperature TJ (IFX54441EJV33)
Output / ADJ Pin Voltage VOUT versus
Junction Temperature TJ (IFX54441EJV)
3.36
1.24
1.235
3.34
1.23
ADJ Pin Voltage [V]
VOUT [V]
3.32
3.3
1.225
1.22
1.215
3.28
1.21
3.26
1.205
IOUT = 1 mA
3.24
−50
0
IOUT = 1 mA
50
Tj [°C]
1.2
−50
100
800
40
700
35
600
30
500
25
400
300
100
20
15
VOUT,nom = 3.3 V
IOUT,nom = 0 mA
VEN = VIN
Tj = 25 °C
200
100
0
50
Tj [°C]
Quiescent Current Iq versus
Input Voltage VIN (IFX54441EJV)
IGND [µA]
IGND [µA]
Quiescent Current Iq versus
Input Voltage VIN (IFX54441EJV33)
0
0
2
4
6
8
10
5
0
10
VIN [V]
Data Sheet
VOUT,nom = 1.22 V
RLoad = 250 kΩ
VEN = VIN
Tj = 25 °C
16
0
5
10
VIN [V]
15
20
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
GND Current IGND versus
Input Voltage VIN (IFX54441EJV33)
GND Current IGND versus
Input Voltage VIN (IFX54441EJV)
1200
400
RLoad = 3.3 kΩ / IOUT = 1 mA*
RLoad = 1.22 kΩ / IOUT = 1 mA*
RLoad = 330 Ω / IOUT = 10 mA*
RLoad = 122 Ω / IOUT = 10 mA*
350
RLoad = 66 Ω / IOUT = 50 mA*
1000
RLoad = 24.4 Ω / IOUT = 50 mA*
[* for VOUT = 3.3 V]
Tj = 25°C
[* for VOUT = 1.22 V]
Tj = 25°C
300
800
IGND [µA]
IGND [µA]
250
600
200
150
400
100
200
50
0
0
2
4
6
8
0
10
0
2
4
VIN [V]
GND Current IGND versus
Input Voltage VIN (IFX54441EJV33)
10
8
RLoad = 33.0 Ω / IOUT = 100 mA*
RLoad = 12.2 Ω / IOUT = 100 mA*
RLoad = 11.0 Ω / IOUT = 300 mA* .
7
RLoad = 4.07 Ω / IOUT = 300 mA* .
7
[* for VOUT = 3.3 V]
Tj = 25°C
6
[* for VOUT = 1.22 V]
Tj = 25°C
6
5
IGND [mA]
5
IGND [mA]
8
GND Current IGND versus
Input Voltage VIN (IFX54441EJV)
8
4
4
3
3
2
2
1
1
0
6
VIN [V]
0
2
4
6
8
0
10
VIN [V]
Data Sheet
0
2
4
6
8
10
VIN [V]
17
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
GND Current IGND versus
Output Current IOUT
EN Pin Threshold (On-to-Off) versus
Junction Temperature TJ
1.2
5
1 mA
300 mA
VIN = VOUT,nom + 1 V
Tj = 25 ° C
4.5
1
4
3.5
0.8
VEN,th [V]
IGND [mA]
3
2.5
0.6
2
0.4
1.5
1
0.2
0.5
0
0
50
100
150
200
IOUT [mA]
250
EN Pin Threshold (Off-to-On) versus
Junction Temperature TJ
0
−50
300
0
50
Tj [°C]
100
EN Pin Input Current versus
EN Pin Voltage VEN
1.2
1.4
Tj = 25 °C
VIN = 20 V
1 mA
300 mA
1.2
1
1
IEN [µA]
VEN,th [V]
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0
−50
Data Sheet
0.2
0
50
Tj [°C]
0
100
18
0
5
10
VEN [V]
15
20
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
Current Limit versus
Input Voltage VIN
EN Pin Input Current versus
Junction Temperature TJ
1.6
1
VEN = 20 V
VOUT = 0 V
Tj = 25 ° C
0.9
1.4
0.8
1.2
0.7
IOUT,max [A]
IEN [µA]
1
0.8
0.6
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0
−50
0.1
0
50
Tj [°C]
0
100
Current Limit versus
Junction Temperature TJ
0
1
2
3
4
VIN [V]
5
6
7
Reverse Output Current versus
Output Voltage VOUT
1.2
90
VOUT.nom = 1.22 V (ADJ)
VIN = 7 V
VOUT = 0 V
VOUT.nom = 3.3 V (V33)
80
1
70
VIN = 0 V
Tj = 25 °C
60
IOUT,rev [µA]
IOUT,max [A]
0.8
0.6
0.4
50
40
30
20
0.2
10
0
−50
Data Sheet
0
50
Tj [°C]
0
100
0
2
4
6
8
10
VOUT [V]
19
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
Minimum Input Voltage1) versus
Junction Temperature TJ
Reverse Output Current versus
Junction Temperature TJ
20
3
VOUT.nom = 1.22 V (ADJ)
18
VOUT.nom = 3.3 V (V33)
2.5
16
VIN = 0 V
2
12
VIN,min [V]
IOUT,rev [µA]
14
10
1.5
8
1
6
4
0.5
IOUT = 1 mA
2
IOUT = 300 mA
0
−50
0
50
Tj [°C]
0
−50
100
0
50
Tj [°C]
100
Adjust Pin Bias current IADJ versus
Junction Temperature TJ
Load Regulation versus
Junction Temperature TJ
5
140
V33: VIN = 4.3 V VOUT.nom = 3.3 V
ADJ: VIN = 2.3 V VOUT.nom = 1.22 V
120
0
100
IADJ [nA]
ΔVLoad [mV]
−5
−10
80
60
−15
40
−20
20
ΔILoad = 1 mA to 300 mA
−25
−50
1)
0
50
Tj [°C]
0
−50
100
0
50
Tj [°C]
100
VIN,min is referred here as the minimum input voltage for which the requested current is provided and VOUT reaches 1 V.
Data Sheet
20
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
ESR(COUT) with CBYP = 10 nF versus
Output Capacitance COUT
ESR Stability versus
Output Current IOUT (for COUT = 3.3µF)
3
1
10
CByp = 10 nF
measurement limit
2.5
ESR(COUT) [Ω]
ESR(COUT) [Ω]
2
ESRmax CByp = 0 nF
0
10
ESRmin CByp = 0 nF
ESRmax CByp = 10 nF
ESRmin CByp = 10 nF
stable region above blue line
1.5
1
COUT = 3.3 µF
(0.06 Ω is measurement limit)
0.5
−1
10
0
50
100
150
200
IOUT [mA]
250
0
300
Input Ripple Rejection PSRR versus
Frequency f
2
3
4
5
COUT [µF]
6
7
Input Ripple Rejection PSRR versus
Junction Temperature TJ
72
100
VIN = VOUTnom + 1.5 V
Vripple = 0.5 Vpp
COUT = 10 µF
90
70
80
68
70
66
PSRR [dB]
PSRR [dB]
60
50
40
64
62
30
60
20
IOUT = 300mA CBYP = 0 nF
IOUT = 300mA CBYP = 10nF
10
58
IOUT = 50mA CBYP = 0 nF
Data Sheet
100
1k
f [Hz]
IOUT = 300mA; CBYP = 0 nF
IOUT = 300mA; CBYP = 10nF
IOUT = 50mA CBYP = 10nF
0
10
VIN = VOUTnom + 1.5 V
Vripple = 0.5 Vpp
fripple = 120 Hz
COUT = 10 µF
10k
56
−50
100k
21
0
50
Tj [°C]
100
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
Output Noise Spectral Density (ADJ) versus
Frequency (COUT = 10 µF, IOUT = 50 mA1))
Output Noise Spectral Density (ADJ) versus
Frequency (COUT = 22 µF, IOUT = 50 mA1))
1
1
10
10
COUT = 22 µF
IOUT = 50 mA
√
Output Spectral Noise Density μV/ Hz
√
Output Spectral Noise Density μV/ Hz
COUT = 10 µF
IOUT = 50 mA
0
10
−1
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=250mΩ
−2
10
1
10
2
10
3
4
10
f [Hz]
10
0
10
−1
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=250mΩ
−2
10
5
10
Output Noise Spectral Density (3.3 V) versus
Frequency (COUT = 10 µF, IOUT = 50 mA1))
1
10
2
10
3
4
10
f [Hz]
10
Output Noise Spectral Density (3.3 V) versus
Frequency (COUT = 22 µF, IOUT = 50 mA1))
1
1
10
10
COUT = 22 µF
IOUT = 50 mA
√
Output Spectral Noise Density μV/ Hz
√
Output Spectral Noise Density μV/ Hz
COUT = 10 µF
IOUT = 50 mA
0
10
−1
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=250mΩ
−2
10
5
10
1
10
2
10
3
10
f [Hz]
4
10
0
10
−1
10
CByp = 0 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=0
CByp = 10 nF; ESR(COUT)=250mΩ
−2
10
5
10
1
10
2
10
3
10
f [Hz]
4
10
5
10
1) Load condition 50 mA is representing a worst case condition with regard to output voltage noise performance.
Data Sheet
22
Rev. 1.1, 2014-10-30
IFX54441
Typical Performance Characteristics
Transient Response CBYP = 0nF (IFX54441EJV33)
0,3
0,15
COUT = 10 µF
CBYP = 0 nF
VIN = 6 V
0,1
0
0,05
0
-0,05
-0,1
-0,1
-0,2
-0,15
-0,3
0
100
200
300
400
500
Time (μs)
600
700
800
900
0
1000
400
400
IOUT : 100 to 300mA
350
20
40
60
80
60
80
100
120
140
160
180
200
100
120
140
160
180
200
Time / [μs]
IOUT : 100 to 300mA
350
300
Load Step / [mA]
300
Load Step / [mA]
COUT = 10 µF
CBYP = 10 nF
VIN = 6V
0,1
VOUT Deviation / [V]
0,2
VOUT Deviation / [V]
Transient Response CBYP = 10nF (IFX54441EJV33)
250
200
150
250
200
150
100
100
50
50
0
0
0
100
Data Sheet
200
300
400
500
Time (μs)
600
700
800
900
1000
0
23
20
40
Time / [μs]
Rev. 1.1, 2014-10-30
IFX54441
Application Information
7
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
IFX54441
VIN
IN
V OUT
OUT
CIN
SENSE
1µF
EN
CBYP
COUT
10nF
10µF
R Load
BYP
GND
GND
Figure 5
Typical Application Circuit IFX54441 (fixed voltage version)
IFX54441 (ADJ)
VIN
IN
V OUT
OUT
R2
CIN
ADJ
CBYP
1µF
EN
BYP
10nF
R1
COUT
R Load
10µF
GND
GND
Calculation of V OUT:
Figure 6
VOUT = 1.22V x (1 + R2 / R1) + (IADJ x R2)
Typical Application Circuit IFX54441 (adjustable version)
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application1)2).
1) Please note that in case a non-negligible inductance at IN pin is present, e.g. due to long cables, traces, parasitics, etc, a
bigger input capacitor CIN may be required to filter its influence. As a rule of thumb if the IN pin is more than six inches away
from the main input filter capacitor an input capacitor value of CIN = 10 µF is recommended.
2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors COUT for enhanced
noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 25).
Data Sheet
24
Rev. 1.1, 2014-10-30
IFX54441
Application Information
The IFX54441 is a 300 mA low dropout regulator with very low quiescent current and Enable-functionality. The
device is capable of supplying 300 mA at a dropout voltage of 270 mV. Output voltage noise numbers down to
24 µVRMS can be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass
capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator,
lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical
30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several
protection features which makes it ideal for battery-powered systems. It is protected against both reverse input
and reverse output voltages. In battery backup applications where the output can be held up by a backup battery
when the input is pulled to ground the device behaves like it has a diode in series with its output and prevents
reverse current flow.
7.1
Adjustable Operation
The adjustable version of the IFX54441 has an output voltage range of 1.22 V to 20 V - VDR. The output voltage
is set by the ratio of two external resistors, as it can be seen in Figure 6 (for the calculation of VOUT the formula
given in the figure can be used). The device controls the output to maintain the ADJ pin at 1.22 V referenced to
ground. The current in R1 is then equal 1.22 V / R1 and the current in R2 equals the current in R1 plus the ADJ pin
bias current. The ADJ pin bias current, which is ~ 60 nA @ 25°C, flows through R2 into the ADJ pin. The value of
R1 should be not greater than 250 kΩ in order to minimize errors in the output voltage caused by the ADJ pin bias
current. Note that when the device is shutdown (i.e. low level applied to EN pin) the output is turned off and
consequently the divider current will be zero. For details of the ADJ pin bias current see also the corresponding
typical performance graph Figure “Adjust Pin Bias current IADJ versus Junction Temperature TJ” on
Page 20.
7.2
Kelvin Sense Connection
For the fixed voltage version of the IFX54441 the SENSE pin is the input to the error amplifier. An optimum
regulation will be obtained at the point where the SENSE pin is connected to the OUT pin of the regulator. In critical
applications however small voltage drops can be caused by the resistance Rp of the PC-traces and thus may lower
the resulting voltage at the load. This effect may be eliminated by connecting the SENSE pin to the output as close
as possible at the load (see Figure 7). Please note that the voltage drop across the external PC trace will add up
to the dropout voltage of the regulator.
IFX54441
IN
VIN
CIN
RP
OUT
SENSE
EN
COUT
R Load
BYP
GND
RP
Figure 7
Kelvin Sense Connection
7.3
Bypass Capacitance and Low Noise Performance
The IFX54441 regulator may be used in combination with a bypass capacitor connecting the OUT pin to the BYP
pin in order to minimize output voltage noise1).This capacitor will bypass the reference of the regulator, providing
1) a good quality low leakage capacitor is recommended.
Data Sheet
25
Rev. 1.1, 2014-10-30
IFX54441
Application Information
a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output voltage noise
in the considered bandwidth. For a given output voltage actual numbers of the output voltage noise will - next to
the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor and its ESR: In case
of the IFX54441EJV applied with unity gain (i.e. VOUT = 1.22 V) the usage of a bypass capacitor of 10 nF in
combination with a (low ESR) ceramic COUT of 10 µF will result in output voltage noise numbers of typical
41 µVRMS. This Output Noise level can be reduced to typical 28 µVRMS under the same conditions by adding a
small resistor of ~250 mΩ in series to the 10 µF ceramic output capacitor acting as additional ESR. A reduction of
the output voltage noise can also be achieved by increasing capacitance of the output capacitor. For COUT = 22 µF
(ceramic low ESR) the output voltage noise will be typically around 29 µVRMS and can again be further lowered to
24 µVRMS by adding a small resistance of ~250 mΩ in series to COUT. In case of the fix voltage version
IFX54441EJV33 the output voltage noise for the described cases vary from 45 µVRMS down to 30 µVRMS. For
further details please also see “Output Voltage Noise11)” on Page 12,, of the Electrical Characteristics. Please
note that next to reducing the output voltage noise level the usage of a bypass capacitor has the additional benefit
of improving transient response which will be also explained in the next chapter. However one needs to take into
consideration that on the other hand the regulator start-up time is proportional to the size of the bypass capacitor
and slows down to values around 15 ms when using a 10 nF bypass capacitor in combination with a 10 µF COUT
output capacitor.
7.4
Output Capacitance Requirements and Transient Response
The IFX54441 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor is
an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor of
3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Like in general for LDO’s the output
transient response of the IFX54441 will be a function of the output capacitance. Larger values of output
capacitance decrease peak deviations and thus improve transient response for larger load current changes.
Bypass capacitors, used to decouple individual components powered by the IFX54441 will increase the effective
output capacitor value. Please note that with the usage of bypass capacitors for low noise operation either larger
values of output capacitors are needed or a minimum ESR requirement of COUT may have to be considered (see
also Figure “ESR(COUT) with CBYP = 10 nF versus Output Capacitance COUT” on Page 21 as example). In
conjunction with the usage of a 10 nF bypass capacitor an output capacitor COUT ≥ 6.8 µF is recommended. The
benefit of a bypass capacitor to the transient response performance is impressive and illustrated as one example
in Figure 8 where the transient response of the IFX54441EJV33 to one and the same load step from 100 mA to
300 mA is shown with and without a 10 nF bypass capacitor: for the given configuration of COUT = 10 µF with no
bypass capacitor the load step will settle in the range of less than 100 µs while for COUT = 10 µF in conjunction
with a 10 nF bypass capacitor the same load step will settle in the range of 10 µs. Due to the shorter reaction time
of the regulator by adding the bypass capacitor not only the settling time improves but also output voltage
deviations due to load steps are sharply reduced.
0,3
VOUT Deviation / [V]
C_BYP = 0nF
C_BYP = 10nF
COUT = 10 µF
CBYP = 0 vs 10nF
VIN = 6 V
0,2
0,1
0
-0,1
-0,2
-0,3
0
Figure 8
Data Sheet
100
200
300
400
500
Time (μs)
600
700
800
900
1000
Influence of CBYP: example of transient response to one and the same load step with and
without CBYP of 10 nF (IOUT 100 mA to 300 mA, IFX54441EJV33)
26
Rev. 1.1, 2014-10-30
IFX54441
Application Information
7.5
Protection Features
The IFX54441 regulators incorporate several protection features which make them ideal for usage in batterypowered circuits. In addition to normal protection features associated with monolithic regulators like current limiting
and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse
voltages from output to input.
Current limit protection and thermal overload protection are intended to protect the device against current overload
conditions at the output of the device. For normal operation the junction temperature must not exceed 125°C.
The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to
less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will
protect both itself and the load. This provides protection against batteries being plugged backwards.
The output of the IFX54441 can be pulled below ground without damaging the device. If the input is left open-circuit
or grounded, the output can be pulled below ground by 20 V. Under such conditions the output of the device by
itself behaves like an open circuit with practically no current flowing out of the pin1). In more application relevant
cases however where the output is either connected to the SENSE pin (fix voltage variant) or tied either via an
external voltage divider or directly to the ADJ pin (adjustable variant) a small current will be present from this origin.
In the case of the fixed voltage version this current will typically be below 100 µA while for the adjustable version
it depends on the magnitude of the top resistor of the external voltage divider 2). If the input is powered by a voltage
source the output will source the short circuit current of the device and will protect itself by thermal limiting. In this
case grounding the EN pin will turn off the device and stop the output from sourcing the short-circuit current.
The ADJ pin of the adjustable device can be pulled above or below ground by as much as 7 V without damaging
the device. If the input is grounded or left open-circuit, the ADJ pin will act inside this voltage range like a large
resistor (typically 100 kΩ) when being pulled above ground and like a resistor (typically 5 kΩ) in series with a diode
when being pulled below ground. In situations where the ADJ pin is at risk of being pulled outside its absolute
maximum ratings ±7 V the ADJ pin current must be limited to 1 mA (e.g. in cases where the ADJ pin is connected
to a resistor divider that would pull the ADJ pin above its 7 V clamp voltage). Let’s consider for example the case
where a resistor divider is used to provide a 1.5 V output from the 1.22 V reference and the output is forced to
20 V. The top resistor of the resistor divider must then be chosen to limit the current into the ADJ pin to 1 mA or
less when the ADJ pin is at 7 V. The 13 V difference between output and ADJ pin divided by the 1 mA maximum
current into the ADJ pin requires a minimum resistor value of 13 kΩ.
In circuits where a backup battery is required, several different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left
open-circuit. Current flow back into the output will follow the curve as shown in Figure 9 below.
When the IN pin of the fixed voltage version is forced below the OUT pin, or the OUT pin is pulled above the IN
pin, the input current will drop to very small values – typically down to less than 2 µA, once VOUT exceeds VIN by
some 300 mV or more. This can happen if the input of the device is connected to a discharged battery and the
output is held up by either a backup battery or a second regulator circuit. The state of the EN pin will have no effect
on the reverse output current when the output is pulled above the input.
1) typically < 1 µA for the mentioned conditions, VOUT being pulled below ground with other pins either grounded or open.
2) In case there is no external voltage divider applied i.e. the ADJ pin is directly connected to the output and the output is
pulled below ground by 20 V the current flowing out of the ADJ pin will be typically ~ 4 mA. Please ensure in such cases
that the absolute maximum ratings of the ADJ pin are respected.
Data Sheet
27
Rev. 1.1, 2014-10-30
IFX54441
Application Information
90
VOUT.nom = 1.22 V (ADJ)
VOUT.nom = 3.3 V (V33)
80
70
VIN = 0 V
Tj = 25 °C
IOUT,rev [µA]
60
50
40
30
20
10
0
0
2
4
6
8
10
VOUT [V]
Figure 9
Data Sheet
Reverse Output Current
28
Rev. 1.1, 2014-10-30
IFX54441
Package Outlines
8
Package Outlines
0.35 x 45˚
1.27
0.41±0.09 2)
0.2
8˚ MAX.
0.19 +0.06
0.08 C
Seating Plane
C
M
0.1 C D 2x
1.7 MAX.
Stand Off
(1.45)
0.1+0
-0.1
3.9 ±0.11)
0.64 ±0.25
C A-B D 8x
D
0.2
6 ±0.2
M
D 8x
Bottom View
8
1
5
1
4
8
4
5
2.65 ±0.2
3 ±0.2
A
B
4.9 ±0.11)
0.1 C A-B 2x
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
3) JEDEC reference MS-012 variation BA
1.63 ±0.1
Z
0.71 ±0.1
Pin 1 Marking
0.25 ±0.1
3.3 ±0.1
0.05
0.5 ±0.1
0.53 ±0.1
1.48 ±0.1
0.36 ±0.1
0.55 ±0.1
0.1 ±0.1
3.3 ±0.1
2.58 ±0.1
0.96 ±0.1
1±0.1
0 +0.05
PG-DSO-8 Exposed Pad package outlines
0.2 ±0.1
Figure 10
PG-DSO-8-27-PO V01
Pin 1 Marking
0.25 ±0.1
PG-TSON-10-2-PO V02
Z (4:1)
0.07 MIN.
Figure 11
PG-TSON-10 Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
29
Dimensions in mm
Rev. 1.1, 2014-10-30
IFX54441
Revision History
9
Revision History
Revision
Date
Changes
1.1
2014-10-30
Updated Data Sheet including additional package type PG-TSON-10:
• PG-TSON-10 package variants added: Product Overview, Pin Configuration
Thermal Resistance, wording, etc, added / updated accordingly.
• Footnote 7) on Page 14 reworked.
• Application Information updated: Clarification and correction of wording.
Typical values updated and footnotes added.
• Editorial changes throughout the document.
1.0
2014-03-12
Data Sheet - Initial Release
Data Sheet
30
Rev. 1.1, 2014-10-30
Edition 2014-10-30
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
The Infineon Technologies component described in this Data Sheet may be used in life-support devices or systems
and/or automotive, aviation and aerospace applications or systems only with the express written approval of
Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that lifesupport automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device
or system. Life support devices or systems are intended to be implanted in the human body or to support and/or
maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
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