Control Integrated POwer System
(CIPOS™)
IGCM20F60GA
Datasheet
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 17
V 2.9
2017-09-06
Control Integrated POwer System (CIPOS™)
IGCM20F60GA
Table of contents
Table of contents ................................................................................................................................................... 2
CIPOS™ Control Integrated POwer System ............................................................................................................ 3
Features
.................................................................................................................................................................. 3
Target Applications ...................................................................................................................................................... 3
Description .................................................................................................................................................................. 3
System Configuration .................................................................................................................................................. 3
Pin Configuration ................................................................................................................................................... 4
Internal Electrical Schematic ................................................................................................................................. 4
Pin Assignment ...................................................................................................................................................... 5
Pin Description ...................................................................................................................................................... 5
HIN(U, V, W) and LIN(U, V, W) (Low side and high side control pins, Pin 7 - 12)......................................................... 5
VFO (Fault-output and NTC, Pin 14) ............................................................................................................................ 6
ITRIP (Over current detection function, Pin 15).......................................................................................................... 6
VDD, VSS (Low side control supply and reference, Pin 13, 16) ................................................................................... 6
VB(U, V, W) and VS(U, V, W) (High side supplies, Pin 1 - 6) .......................................................................................... 6
NW, NV, NU (Low side emitter, Pin 17 - 19) ................................................................................................................. 6
W, V, U (High side emitter and low side collector, Pin 20 - 22) ................................................................................... 6
P (Positive bus input voltage, Pin 23) .......................................................................................................................... 6
Absolute Maximum Ratings ................................................................................................................................... 7
Module Section ............................................................................................................................................................ 7
Inverter Section............................................................................................................................................................ 7
Control Section ............................................................................................................................................................ 7
Recommended Operation Conditions ................................................................................................................... 8
Static Parameters .................................................................................................................................................. 9
Dynamic Parameters ........................................................................................................................................... 10
Bootstrap Parameters ......................................................................................................................................... 10
Thermistor ........................................................................................................................................................... 11
Mechanical Characteristics and Ratings .............................................................................................................. 11
Circuit of a Typical Application ............................................................................................................................ 12
Switching Times Definition .................................................................................................................................. 13
Electrical characteristic ....................................................................................................................................... 14
Package Outline ................................................................................................................................................... 15
Revision history ................................................................................................................................................... 16
Datasheet
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Control Integrated POwer System (CIPOS™)
IGCM20F60GA
CIPOS™
Control Integrated POwer System
Dual In-Line Intelligent Power Module
3Φ -bridge 600V / 20A
Features
Description
Fully isolated Dual In-Line molded module
The CIPOS™ module family offers the chance for
integrating various power and control components
to increase reliability, optimize PCB size and system
costs.
Reverse conducting IGBTs with monolithic body
diode
Rugged SOI gate driver technology with stability
against transient and negative voltage
Allowable negative VS potential up to -11V for
signal transmission at VBS=15V
Integrated bootstrap functionality
Over current shutdown
Temperature monitor
Under-voltage lockout at all channels
Low side emitter pins accessible for all phase
current monitoring (open emitter)
Cross-conduction prevention
All of 6 switches turn off during protection
Lead-free terminal plating; RoHS compliant
It is designed to control three phase AC motors and
permanent magnet motors in variable speed drives
for applications like an air conditioning, a
refrigerator and a washing machine. The package
concept is specially adapted to power applications,
which need good thermal conduction and electrical
isolation, but also EMI-save control and overload
protection.
The reverse conducting IGBTs are combined with an
optimized SOI gate driver for excellent electrical
performance.
System Configuration
Target Applications
3 half bridges with reverse conducting IGBTs
Dish washers
3Φ SOI gate driver
Refrigerators
Thermistor
Washing machines
Pin-to-heatsink clearance distance typ. 1.6mm
Air-conditioners
Fans
Low power motor drives
Datasheet
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IGCM20F60GA
Pin Configuration
Bottom View
(24) NC
(1) VS(U)
(2) VB(U)
(23) P
(3) VS(V)
(4) VB(V)
(22) U
(5) VS(W)
(6) VB(W)
(21) V
(7) HIN(U)
(8) HIN(V)
(9) HIN(W)
(10) LIN(U)
(11) LIN(V)
(12) LIN(W)
(13) VDD
(14) VFO
(20) W
(19) NU
(18) NV
(15) ITRIP
(16) VSS
(17) NW
Figure 1
Pin configuration
Internal Electrical Schematic
NC (24)
P (23)
(1) VS(U)
(2) VB(U)
VB1
HO1
RBS1
VS1
U (22)
(3) VS(V)
(4) VB(V)
VB2
RBS2
HO2
VS2
V (21)
(5) VS(W)
(6) VB(W)
VB3
RBS3
(7) HIN(U)
HIN1
(8) HIN(V)
HIN2
(9) HIN(W)
(10) LIN(U)
HIN3
LIN1
(11) LIN(V)
LIN2
(12) LIN(W)
LIN3
(13) VDD
VDD
(14) VFO
VFO
(15) ITRIP
ITRIP
(16) VSS
HO3
VS3
W (20)
LO1
NU (19)
LO2
NV (18)
LO3
VSS
NW (17)
Thermistor
Figure 2
Datasheet
Internal schematic
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Control Integrated POwer System (CIPOS™)
IGCM20F60GA
Pin Assignment
Pin Number
Pin Name
Pin Description
1
VS(U)
U-phase high side floating IC supply offset voltage
2
VB(U)
U-phase high side floating IC supply voltage
3
VS(V)
V-phase high side floating IC supply offset voltage
4
VB(V)
V-phase high side floating IC supply voltage
5
VS(W)
W-phase high side floating IC supply offset voltage
6
VB(W)
W-phase high side floating IC supply voltage
7
HIN(U)
U-phase high side gate driver input
8
HIN(V)
V-phase high side gate driver input
9
HIN(W)
W-phase high side gate driver input
10
LIN(U)
U-phase low side gate driver input
11
LIN(V)
V-phase low side gate driver input
12
LIN(W)
W-phase low side gate driver input
13
VDD
Low side control supply
14
VFO
Fault output / Temperature monitor
15
ITRIP
Over current shutdown input
16
VSS
Low side control negative supply
17
NW
W-phase low side emitter
18
NV
V-phase low side emitter
19
NU
U-phase low side emitter
20
W
Motor W-phase output
21
V
Motor V-phase output
22
U
Motor U-phase output
23
P
Positive bus input voltage
24
NC
No Connection
Pin Description
HIN(U, V, W) and LIN(U, V, W) (Low side and high
side control pins, Pin 7 - 12)
These pins are positive logic and they are
responsible for the control of the integrated IGBT.
The Schmitt-trigger input thresholds of them are
such to guarantee LSTTL and CMOS compatibility
down to 3.3V controller outputs. Pull-down resistor
of about 5k is internally provided to pre-bias
inputs during supply start-up and a zener clamp is
provided for pin protection purposes. Input
Schmitt-trigger and noise filter provide beneficial
noise rejection to short input pulses.
CIPOSTM
Schmitt-Trigger
HINx
LINx
Figure 3
a)
INPUT NOISE
FILTER
UZ=10.5V
SWITCH LEVEL
VIH; VIL
VSS
Input pin structure
tFILIN
b)
tFILIN
HIN
LIN
HIN
LIN
high
The noise filter suppresses control pulses which are
below the filter time tFILIN. The filter acts according
to Figure 4.
Datasheet
5k
HO
LO
Figure 4
5 of 17
low
HO
LO
Input filter timing diagram
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Control Integrated POwer System (CIPOS™)
IGCM20F60GA
It is not recommended for proper work to provide
input pulse-width lower than 1µs.
VDD, VSS (Low side control supply and reference,
Pin 13, 16)
The integrated gate drive provides additionally a
shoot through prevention capability which avoids
the simultaneous on-state of two gate drivers of the
same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and
LO3). When two inputs of a same leg are activated,
only former activated one is activated so that the
leg is kept steadily in a safe state.
VDD is the control supply and it provides power
both to input logic and to output power stage.
Input logic is referenced to VSS ground.
The under-voltage circuit enables the device to
operate at power on when a supply voltage of at
least a typical voltage of VDDUV+ = 12.1V is present.
The IC shuts down all the gate drivers power
outputs, when the VDD supply voltage is below
VDDUV- = 10.4V. This prevents the external power
switches from critically low gate voltage levels
during on-state and therefore from excessive power
dissipation.
A minimum deadtime insertion of typically 380ns is
also provided by driver IC, in order to reduce crossconduction of the external power switches.
VFO (Fault-output and NTC, Pin 14)
The VFO pin indicates a module failure in case of
under voltage at pin VDD or in case of triggered
over current detection at ITRIP. A pull-up resistor is
externally required.
CIPOS
VDD
RON,FLT
VB(U, V, W) and VS(U, V, W) (High side supplies, Pin
1 - 6)
VB to VS is the high side supply voltage. The high
side circuit can float with respect to VSS following
the external high side power device emitter voltage.
TM
From ITRIP - Latch
VFO
Due to the low power consumption, the floating
driver stage is supplied by integrated bootstrap
circuit.
1
VSS
Thermistor
Figure 5
From UV detection
Internal circuit at pin VFO
The under-voltage detection operates with a rising
supply threshold of typical VBSUV+ = 12.1V and a
falling threshold of VBSUV- = 10.4V.
The same pin provides direct access to the NTC,
which is referenced to VSS. An external pull-up
resistor connected to +5V ensures that the resulting
voltage can be directly connected to the
microcontroller.
VS(U, V, W) provide a high robustness against
negative voltage in respect of VSS of -50V
transiently. This ensures very stable designs even
under rough conditions.
ITRIP (Over current detection function, Pin 15)
NW, NV, NU (Low side emitter, Pin 17 - 19)
CIPOS™ provides an over current detection
function by connecting the ITRIP input with the
IGBT collector current feedback. The ITRIP
comparator threshold (typ. 0.47V) is referenced to
VSS ground. An input noise filter (typ.: tITRIPMIN =
530ns) prevents the driver to detect false overcurrent events.
The low side emitters are available for current
measurements of each phase leg. It is
recommended to keep the connection to pin VSS as
short as possible in order to avoid unnecessary
inductive voltage drops.
W, V, U (High side emitter and low side collector,
Pin 20 - 22)
Over current detection generates a shutdown of all
outputs of the gate driver after the shutdown
propagation delay of typically 1000ns.
These pins are motor U, V, W input pins.
P (Positive bus input voltage, Pin 23)
The fault-clear time is set to minimum 40µs.
Datasheet
The high side IGBTs are connected to the bus
voltage. It is noted that the bus voltage does not
exceed 450V.
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IGCM20F60GA
Absolute Maximum Ratings
(VDD = 15V and TJ = 25°C, if not stated otherwise)
Module Section
Description
Condition
Storage temperature range
Isolation test voltage
RMS, f = 60Hz, t = 1min
Operating case temperature range
Refer to Figure 6
Symbol
Value
Unit
min
max
Tstg
-40
125
°C
VISOL
2000
-
V
TC
-40
125
°C
Inverter Section
Description
Condition
Symbol
Value
min
max
Unit
Max. blocking voltage
IC = 250µA
VCES
600
-
V
DC link supply voltage of P-N
Applied between P-N
VPN
-
450
V
DC link supply voltage (surge) of P-N
Applied between P-N
VPN(surge)
-
500
V
Output current
TC = 25°C, TJ < 150°C
TC = 80°C, TJ < 150°C
IC
-20
-15
20
15
A
Maximum peak output current
less than 1ms
IC(peak)
-45
45
A
Short circuit withstand time1
VDC ≤ 400V, TJ = 150°C
tSC
-
5
µs
Power dissipation per IGBT
Ptot
-
32.6
W
Operating junction temperature range
TJ
-40
150
°C
RthJC
-
3.84
K/W
Single IGBT thermal resistance,
junction-case
Control Section
Description
Condition
Value
min
max
Unit
Module supply voltage
VDD
-1
20
V
High side floating supply voltage
(VB vs. VS)
VBS
-1
20
V
VIN
VITRIP
-1
-1
10
10
V
fPWM
-
20
kHz
Input voltage
LIN, HIN, ITRIP
Switching frequency
1
Symbol
Allowed number of short circuits: 1s.
Datasheet
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IGCM20F60GA
Recommended Operation Conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified.
Description
Symbol
Value
min
typ
max
Unit
DC link supply voltage of P-N
VPN
0
-
400
V
High side floating supply voltage (VB vs. VS)
VBS
13.5
-
18.5
V
Low side supply voltage
VDD
14.0
16
18.5
V
Control supply variation
ΔVBS,
ΔVDD
-1
-1
-
1
1
V/µs
Logic input voltages LIN, HIN, ITRIP
VIN
VITRIP
0
0
-
5
5
V
Between VSS - N (including surge)
VSS
-5
-
5
V
Figure 6
TC measurement point1
Any measurement except for the specified point in figure 6 is not relevant for the temperature verification and
brings wrong or different information.
1
Datasheet
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IGCM20F60GA
Static Parameters
(VDD = 15V and TJ = 25°C, if not stated otherwise)
Description
Condition
min
Value
typ
max
VCE(sat)
-
1.6
1.8
2.0
-
V
Symbol
Unit
IC = 15A
Collector-Emitter saturation voltage
TJ = 25°C
150°C
IF = 15A
Emitter-Collector forward voltage
TJ = 25°C
150°C
VF
-
1.75
1.8
2.2
-
V
Collector-Emitter leakage current
VCE = 600V
ICES
-
-
1
mA
Logic "1" input voltage (LIN, HIN)
VIH
-
2.1
2.5
V
Logic "0" input voltage (LIN, HIN)
VIL
0.7
0.9
-
V
ITRIP positive going threshold
VIT,TH+
400
470
540
mV
ITRIP input hysteresis
VIT,HYS
40
70
-
mV
VDD and VBS supply under voltage
positive going threshold
VDDUV+
VBSUV+
10.8
12.1
13.0
V
VDD and VBS supply under voltage
negative going threshold
VDDUVVBSUV-
9.5
10.4
11.2
V
VDD and VBS supply under voltage
lockout hysteresis
VDDUVH
VBSUVH
1.0
1.7
-
V
Input clamp voltage (HIN, LIN, ITRIP)
Iin=4mA
VINCLAMP
9.0
10.1
12.5
V
Quiescent VBx supply current
(VBx only)
HIN = 0V
IQBS
-
300
500
µA
Quiescent VDD supply current
(VDD only)
LIN = 0V, HINX = 5V
IQDD
-
370
900
µA
Input bias current
VIN = 5V
IIN+
-
1
1.5
mA
Input bias current
VIN = 0V
IIN-
-
2
-
µA
ITRIP input bias current
VITRIP = 5V
IITRIP+
-
65
150
µA
VFO input bias current
VFO = 5V, VITRIP = 0V
IFO
-
60
-
µA
VFO output voltage
IFO = 10mA, VITRIP = 1V
VFO
-
0.5
-
V
Datasheet
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IGCM20F60GA
Dynamic Parameters
(VDD = 15V and TJ = 25°C, if not stated otherwise)
Description
tITRIPmin
min
-
Value
typ
650
45
150
200
970
130
200
1250
530
max
-
VLIN, HIN = 0V & 5V
tFILIN
-
290
-
ns
VITRIP = 1V
tFLTCLR
40
65
200
µs
DTPWM
1.5
-
-
µs
DTIC
-
380
-
ns
Eon
-
400
605
-
µJ
Eoff
-
430
625
-
µJ
Erec
-
95
225
-
µJ
min
600
Value
typ
-
max
-
Condition
Turn-on propagation delay time
Turn-on rise time
Turn-on switching time
Reverse recovery time
Turn-off propagation delay time
Turn-off fall time
Turn-off switching time
Short circuit propagation delay time
Input filter time ITRIP
Input filter time at LIN, HIN for turn
on and off
Fault clear time after ITRIP-fault
Deadtime between low side and high
side
Deadtime of gate drive circuit
IGBT turn-on energy (includes reverse
recovery of diode)
IGBT turn-off energy
Diode recovery energy
VLIN, HIN = 5V,
IC = 15A,
VDC = 300V
VLIN, HIN = 0V,
IC = 15A,
VDC = 300V
From VIT,TH+ to 10% ISC
VITRIP = 1V
VDC = 300V, IC = 15A
TJ = 25°C
150°C
VDC = 300V, IC = 15A
TJ = 25°C
150°C
VDC = 300V, IC = 15A
TJ = 25°C
150°C
Symbol
ton
tr
tc(on)
trr
toff
tf
tc(off)
tSCP
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bootstrap Parameters
(TJ = 25°C, if not stated otherwise)
Description
Condition
Repetitive peak reverse voltage
Bootstrap diode resistance of
U-phase1
Reverse recovery time
Forward voltage drop
1
Symbol
VRRM
VS2 or VS3 = 300V, TJ = 25°C
VS2 and VS3 = 0V, TJ = 25°C
VS2 or VS3 = 300V, TJ = 125°C
VS2 and VS3 = 0V, TJ = 125°C
IF = 0.6A, di/dt = 80A/µs
IF = 20mA, VS2 and VS3 = 0V
RBS1
-
35
40
50
65
trr_BS
VF_BS
-
50
2.6
Unit
V
-
Ω
-
ns
V
RBS2 and RBS3 have same values to RBS1.
Datasheet
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IGCM20F60GA
Thermistor
Description
Condition
Resistor
min
Value
typ
max
RNTC
-
85
-
k
B(25/100)
-
4092
-
K
Symbol
TNTC = 25°C
B-constant of NTC
(Negative Temperature Coefficient)
Unit
3500
2500
2000
1500
Min.
Typ.
Max.
30
Thermistor resistance [kΩ ]
Thermistor resistance [kΩ ]
35
3000
25
20
15
10
5
0
50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130
1000
Thermistor temperature [℃]
500
0
-40 -30 -20 -10 0
Figure 7
10 20 30 40 50 60 70 80 90 100 110 120 130
Thermistor temperature [℃]
Thermistor resistance – temperature curve and table
(For more information, please refer to the application note ‘AN2016-10 CIPOS Mini Technical description’)
Mechanical Characteristics and Ratings
Description
Mounting torque
Flatness
Weight
Condition
M3 screw and washer
Refer to Figure 8
min
0.59
-50
-
Value
typ
0.69
6.15
max
0.78
100
-
Unit
Nm
µm
g
+
-
- +
Figure 8
Datasheet
Flatness measurement position
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IGCM20F60GA
Circuit of a Typical Application
NC (24)
P (23)
(1) VS(U)
(2) VB(U)
HO1
VB1
RBS1
VS1
U (22)
(3) VS(V)
#4
(4) VB(V)
VB2
RBS2
HO2
VS2
V (21)
3-ph AC
Motor
(5) VS(W)
(6) VB(W)
VB3
RBS3
HO3
VS3
W (20)
#5
#1
(7) HIN(U)
(8) HIN(V)
(9) HIN(W)
(10) LIN(U)
(11) LIN(V)
Micro
Controller
HIN1
LO1
HIN2
NU (19)
HIN3
LIN1
LIN2
LO2
(12) LIN(W)
#7
#6
LIN3
NV (18)
(13) VDD
VDD line
(14) VFO
(15) ITRIP
(16) VSS
VFO
ITRIP
LO3
NW (17)
VSS
Thermistor
Control
GND line
5 or 3.3V line
Power
GND line
VDD
#3
Temperature monitor
Figure 9
1.
-
VFO output is an open drain output. This signal line should be pulled up to the positive side of the 5V/3.3V logic
power supply with a proper resistor RPU.
It is recommended that RC filter be placed as close to the controller as possible.
Capacitor for high side floating supply voltage should be placed as close to VB and VS pins as possible.
The wiring between CIPOS™ Mini and snubber capacitor including shunt resistor should be as short as possible.
Shunt resistor
-
7.
To prevent protection function errors, CITRIP should be placed as close to Itrip and VSS pins as possible.
Snubber capacitor
-
6.
To reduce input signal noise by high speed switching, the RIN and CIN filter circuit should be mounted. (100Ω, 1nF)
CIN should be placed as close to VSS pin as possible.
VB-VS circuit
-
5.
Typical application circuit
VFO circuit
-
4.
Itrip circuit
-
3.
U-phase current sensing
V-phase current sensing
W-phase current sensing
Input circuit
-
2.
#2
The shunt resistor of SMD type should be used for reducing its stray inductance.
Ground pattern
-
Ground pattern should be separated at only one point of shunt resistor as short as possible.
Datasheet
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IGCM20F60GA
Switching Times Definition
HINx
LINx
2.1V
0.9V
trr
toff
ton
10%
iCx
90%
90%
tf
10%
tr
10%
10%
10%
vCEx
tc(on)
tc(off)
Figure 10
Datasheet
Switching times definition
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IGCM20F60GA
Electrical characteristic
40
TJ=25℃
32
28
24
20
16
VDD=13V
VDD=15V
VDD=20V
12
8
4
0
0.0
0.5
1.0
1.5
2.0
2.5
VCE(sat), Collector - Emitter
3.0
3.5
36
32
28
24
20
16
12
TJ=25℃
TJ=150℃
8
4
0
0.0
4.0
voltage [V]
Typ. Collector – Emitter saturation voltage
0.5
1.0
1.5
2.0
2.5
VCE(sat), Collector - Emitter
28
24
20
16
12
2.5
High side @TJ=25℃
High side @TJ=150℃
Low side @TJ=25℃
2.0
Low side @TJ=150℃
1.5
1.0
0.5
8
12
16
20
24
28
32
36
0
0.0
0.5
voltage [V]
1.0
2.5
3.0
3.5
Typ. Emitter – Collector forward voltage
High side @TJ=150℃
Low side @TJ=25℃
1.2
Low side @TJ=150℃
1.0
0.8
0.6
0.4
0.2
VDC=300V
VDD=15V
VDC=300V
VDD=15V
550
500
High side @TJ=25℃
450
High side @TJ=150℃
400
Low side @TJ=25℃
350
Low side @TJ=150℃
300
250
200
150
100
50
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
Ic, Collector current [A]
12
16
20
24
28
32
36
40
Ic, Collector current [A]
Typ. Turn off switching energy loss
900
2.0
600
Ic, Collector current [A]
Typ. Turn on switching energy loss
1.5
VF, Emitter - Collector voltage [V]
High side @TJ=25℃
1.4
40
TJ=150℃
4
4.0
0.0
4
TJ=25℃
8
Erec, Reverse recovery energy loss [uJ]
Eoff, Turn off switching energy loss [mJ]
3.0
0
Typ. Reverse recovery energy loss
850
High side @TJ=25℃
High side @TJ=150℃
800
Low side @TJ=25℃
Low side @TJ=150℃
750
700
650
600
550
toff, Turn off propagation delay time [ns]
500
VDC=300V
VDD=15V
tc(on), Turn on switching time [ns]
VDC=300V
VDD=15V
450
High side @TJ=25℃
400
High side @TJ=150℃
350
Low side @TJ=25℃
Low side @TJ=150℃
300
250
200
150
100
50
500
VDC=300V
VDD=15V
2200
High side @TJ=25℃
2000
High side @TJ=150℃
Low side @TJ=25℃
1800
Low side @TJ=150℃
1600
1400
1200
1000
0
0
4
8
12
16
20
24
28
32
36
40
0
4
8
Ic, Collector current [A]
12
16
20
24
28
32
36
40
0
Ic, Collector current [A]
Typ. Turn on propagation delay time
Typ. Turn on switching time
1200
trr, Reverse recovery time [ns]
1000
900
800
High side @TJ=25℃
700
High side @TJ=150℃
600
Low side @TJ=25℃
Low side @TJ=150℃
500
400
300
200
12
16
20
24
28
32
36
40
10
VDC=300V
VDD=15V
650
VDC=300V
VDD=15V
8
Typ. Turn off propagation delay time
700
1100
4
Ic, Collector current [A]
ZthJC, transient thermal resistance [K/W]
ton, Turn on propagation delay time [ns]
3.5
32
1.6
VDC=300V
VDD=15V
0.0
tc(off), Turn off switching time [ns]
3.0
Typ. Collector – Emitter saturation voltage
3.5
Eon, Turn on switching energy loss [mJ]
40
VDD=15V
36
IF, Emitter - Collector current [A]
36
Ic, Collector - Emitter current [A]
Ic, Collector - Emitter current [A]
40
600
High side @TJ=25℃
550
High side @TJ=150℃
500
Low side @TJ=25℃
Low side @TJ=150℃
450
400
350
1
0.1
D : duty ratio
D=50%
D=20%
D=10%
D=5%
D=2%
Single pulse
0.01
300
250
200
1E-3
150
100
100
50
0
4
8
12
16
20
24
28
Ic, Collector current [A]
Typ. Turn off switching time
Datasheet
32
36
40
0
4
8
12
16
20
24
28
Ic, Collector current [A]
Typ. Reverse recovery time
14 of 17
32
36
40
1E-4
1E-7 1E-6 1E-5 1E-4 1E-3
0.01
0.1
1
10
tP, Pulse width [sec.]
IGBT transient thermal resistance at all six
IGBTs operation
V 2.9
2017-09-06
100
Control Integrated POwer System (CIPOS™)
IGCM20F60GA
Package Outline
Datasheet
15 of 17
V 2.9
2017-09-06
Control Integrated POwer System (CIPOS™)
IGCM20F60GA
Revision history
Document
version
Date of release
V 2.9
Sep. 2017
Datasheet
Description of changes
Maximum operating case temperature, Tc= 125°C
Package outline update
16 of 17
V 2.9
2017-09-06
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2017-09-06
Published by
Infineon Technologies AG
81726 München, Germany
© 2017 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
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IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
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values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
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