IP2021CPBF

PD-97414 iP2021CPbF Synchronous Buck Dual Channel Power Block Integrated Power Semiconductors, Drivers, & Passives Features          60A Multiphase building block No derating up to TPCB = 95ºC Integrated 6V LDO Operation up to 1 MHz Bi-directional current flow Under Voltage Lockout Optimized for low power loss LGA interface 11mm x 7.65mm outline Applications     Multi-phase Architectures Low Duty-Ratio, High Current Microprocessor Power Supplies High Frequency Low Profile DC-DC Converters Package Description iP2021CPbF iP2021CTRPbF Interface Connection LGA LGA Standard Quantity 10 2000 Description The iP2021C is a fully optimized solution for high current synchronous buck dual-phase or dual output applications. Board space and design time are greatly reduced because most of the components required for both power stages are integrated into a single 11mm x 7.7mm power block. The only additional components required for a complete converter are a PWM controller, the output inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. Typical Application (Dual Output) www.irf.com 8/13/2009 1 PD-97414 iP2021CPbF Absolute Maximum Ratings VIN1, VIN2 to PGND …..………….……..…... -0.3V to 16V VDD to PGND ...…..……………..……..…… -0.3V to 16V PWM1, PWM2 to PGND …….....…..…….. -0.3V to 7.5V (Note 1) EN1, EN2 to PGND ………………….……. -0.3V to 7.5V (Note 1) Storage Temperature ……………..………. -60ºC to 150ºC Operating Block Temperature (TBLK) …….. -40ºC to 135ºC (Note 2) ESD Rating ……………………………….... JEDEC, JESD22-A114 (HBM[4KV], Class 3A) ……………………………….... JEDEC, JESD22-A115 (MM[400V], Class C) MSL Rating…………………………….…… 3 Reflow Temperature …..………………….. 260ºC Peak CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Recommended Operation Conditions PARAMETER Min Typ Max Units Input Voltage (VDD, VIN1,VIN2) 8 - 14 V Output Current (IOUT) - - 30 A Output Voltage (VOUT) - - 5 V Switching Frequency (FSW) 300 - 1000 kHz Minimum VSW On Time 50 - - ns Block Temperature (TBLK) -10 - 125 ºC Conditions Current per channel Electrical Specifications These specifications apply for TBLK = 0ºC to 125ºC, VDD = VIN1 = VIN2 = 8V to 14V unless otherwise specified. PARAMETER Min Typ - 11.2 (Note 3) - 4 Max Units Conditions - W VDD = VIN1 = VIN2 = 12V, VOUT = 1.3V, IOUT = 60A (outputs combined), FSW = 1MHz, L = 325nH, TBLK = 25ºC 8 mA VDD = VIN1 = VIN2 = 12V, EN1 = EN2 = 0V PLOSS Power Block Losses VIN (VIN1, VIN2, VDD) Quiescent Current www.irf.com 8/13/2009 2 PD-97414 iP2021CPbF PARAMETER Min Typ Max Units Conditions Output Voltage - 6 - V VDD = 8V – 14.5V Output Capacitor 1 - - µF 4.15 4.5 V CVCC CVCC Power On Reset CVCC Rising CVCC Falling 3.6 CVCC Threshold 3.95 V 200 mV -40ºC to 125ºC ENABLE INPUT (EN1, EN2) Logic Level Low Threshold - - 0.8 V Logic Level High Threshold 2.0 - - V Threshold Hysteresis - 100 - mV Weak Pull Down Resistance - 100k - Ω Rising Propagation Delay - 40 - ns Falling Propagation Delay - 75 - ns Logic Level Low Threshold - - 0.8 V Logic Level High Threshold 2.0 - - V Threshold Hysteresis - 100 - mV Weak Pull Down Resistance - 100k - Ω Rising Propagation Delay (tPDH) - 60 - ns Falling Propagation Delay (tPDL) - 30 - ns -40ºC to 125ºC PWM INPUT (PWM1, PWM2) -40ºC to 125ºC See Figure 8 for timing diagram Notes: 1. Must not exceed 7.5V 2. Highest die temperature inside the package 3. Guaranteed by design, but not tested in production www.irf.com 8/13/2009 3 PD-97414 iP2021CPbF Power Loss Curve 16 VI = 12V VO = 1.3V FSW = 1MHz LO = 325nH TBLK = 125ºC 14 Power Loss (W) 12 10 8 6 4 2 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 110 120 130 60 Output Current (A) Figure 1 Power Loss Curve SOA Curve Output Current (A) Case Temperature (ºC) 64 60 56 52 48 44 40 36 32 28 24 20 16 12 8 4 0 0 10 20 30 40 50 60 70 80 90 100 Safe Operating Area Tx VI = 12V VO = 1.3V FSW = 1MHz LO = 325nH 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) Figure 2 Safe Operating Area Curve www.irf.com 8/13/2009 4 PD-97414 iP2021CPbF Typical Performance Curves 1.04 1.5 1.0 1.02 0.5 1.00 0.0 0.98 -0.5 0.96 -1.0 0.94 17 8 2 9.5 3 10.8 4 12 5 13.2 6 -1.5 14.5 7 1.20 1.16 1.12 6.0 VI = 12.0V IOUT = 60A FSW = 1MHz LO = 325nH TBLK = 125ºC 2.0 1.04 1.0 1.00 0.0 0.96 -1.0 Output Voltage (V) 0.50 0.25 1.00 0.00 0.99 -0.25 0.98 -0.50 0.97 -0.75 Power Loss (Normalized) 0.75 1.10 -1.00 0.2 2 0.3 3 0.4 4 0.5 5 0.6 6 Output Inductance (µH) www.irf.com 1.00 2.2 1.1 0.0 0.95 -1.1 0.90 -2.2 0.85 -3.3 0.80 200 0.8 7 Figure 5 Normalized Power Loss vs. Inductance 1.05 VI = 12.0V VO = 1.3V IOUT = 60A LO = 325nH TBLK = 125ºC 300 SOA Temp Adjustment (oC) 1.00 1.01 0.96 0.1 1 Figure 4 Normalized Power Loss vs. Output Voltage 1.25 VI = 12.0V VO = 1.3V IOUT = 60A FSW = 1MHz TBLK = 125ºC SOA Temp Adjustment (oC) Power Loss (Normalized) 1.05 1.02 3.0 0.92 -2.0 0.8 1 1.5 1.0 2 2.5 1.3 3 3.5 1.5 4 4.5 1.8 5 5.5 2.5 6 6.5 3.3 7 Figure 3 Normalized Power Loss vs. Input Voltage 1.03 4.0 1.08 Input Voltage (V) 1.04 5.0 SOA Temp Adjustment (oC) 1.06 1.24 2.0 Power Loss (Normalized) 2.5 VO = 1.3V IO = 60A FSW = 1MHz LO = 325nH TBLK = 125ºC 1.08 SOA Temp Adjustment (oC) Power Loss (Normalized) 1.10 -4.4 500 600 750 1000 1250 1500 Switching Frequency (kHz) Figure 6 Normalized Power Loss vs. Switching Frequency 8/13/2009 5 PD-97414 iP2021CPbF Power Loss Measurement Setup Figure 7 Power Loss Test Circuit 90% PW M 10% 90% V SW 10% t PDH t PDL Figure 8 Timing Diagram www.irf.com 8/13/2009 6 PD-97414 iP2021CPbF Applying the Safe Operating Area (SOA) Curve The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case. Please refer to International Rectifier Application Note AN1047 for further details on using this SOA curve in your thermal environment. Procedure 1. Calculate (based on estimated Power Loss) or measure the Case temperature on the device and the board temperature near the device (1mm from the edge). 2. Draw a line from Case Temperature axis to the PCB Temperature axis. 3. Draw a vertical line from the TX axis intercept to the SOA curve. 4. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. Figure 9 SOA Example, Continuous current  31A for TPCB = 100ºC & TCASE = 110ºC www.irf.com 8/13/2009 7 PD-97414 iP2021CPbF Calculating Power Loss and SOA for Different Operating Conditions To calculate Power Loss for a given set of operating conditions, the following procedure should be followed: Power Loss Procedure 1. Determine the maximum current and obtain the typical power loss from Figure 1 2. Use the normalized curves to obtain power loss values that match the operating conditions in the application 3. The typical power loss under the application conditions is then the product of the power loss from Figure 1 and the normalized values. To calculate the Safe Operating Area (SOA) for a given set of operating conditions, the following procedure should be followed: SOA Procedure 1. Determine the maximum PCB and CASE temperature at the maximum operating current for each iP2021C 2. Use the normalized curves to obtain SOA temperature adjustments that match the operating conditions in the application 3. Then, add the sum of the SOA temperature adjustments to the TX axis intercept in Figure 2 Design Example Operating Conditions: Output Current = 50A Input Voltage = 10V Switching Freq = 750 kHz Inductor = 0.2µH Output Voltage = 1.3V Calculating Typical Power Loss: (Figure 1) Typical power loss = 12W (Figure 3) Normalized power loss for input voltage  0.96 (Figure 5) Normalized power loss for output inductor  1.035 (Figure 6) Normalized power loss for switch frequency  0.93 Calculated Typical Power Loss  12W x 0.96 x 1.0 x 1.035 x 0.93  11.1W www.irf.com 8/13/2009 8 PD-97414 iP2021CPbF Calculating SOA Temperature: (Figure 3) SOA temperature adjustment for input voltage  -1.0ºC (Figure 5) SOA temperature adjustment for output inductor  0.95ºC (Figure 6) SOA temperature adjustment for switch frequency  -1.5ºC TX axis intercept adjustment  -1.0ºC + 0.95ºC – 1.5ºC  -1.55ºC Assuming TPCB = 90ºC & TCASE = 110ºC, the following example shows how the SOA current is adjusted for TX decrease of 4.5ºC. Output Current (A) Case Temperature (ºC) 64 60 56 52 48 44 40 36 32 28 24 20 16 12 8 4 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 (5) (3) Safe Operating Area (2) (4) Tx (1) VI = 12V VO = 1.3V FSW = 1MHz LO = 325nH 0 10 20 30 40 50 60 70 80 90 100 110 120 130 PCB Temperature (ºC) 1. Draw a line from Case Temperature axis to the PCB Temperature axis. 2. Draw a vertical line from the TX axis intercept to the SOA curve. 3. Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the SOA continuous current. 4. Draw a new vertical line from the TX axis by adding or subtracting the SOA adjustment temperature from the original TX intercept point. 5. Draw a horizontal line from the intersection of the new vertical line with the SOA curve to the Y-axis (Output Current). The point at which the horizontal line meets the Y-axis is the new SOA continuous current. The SOA adjustment indicates the part is still allowed to run at a continuous current of 53.5A. www.irf.com 8/13/2009 9 PD-97414 iP2021CPbF Internal Block Diagram Figure 10 Internal Block Diagram Pin Description Pin Number Pin Name Description 1, 9 VIN1,VIN2 Input Voltage Pin. Connect input capacitors close to this pin. 2, 8 VSW1, VSW2 Voltage Switching Node – pin connection to the output inductor 3, 7 PGND Power Ground 4 CVCC 5, 6 PWM1, PWM2 10, 11 EN2, EN1 12 VDD www.irf.com Output of internal regulator. Connect 1uF external bypass capacitor. Input signal to MOSFET drivers. When PWM is HIGH, the control FET is on and sync FET is off. When PWM is LOW, the sync FET is on and the control FET is off. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the control and synchronous FETs are turned off. Supply voltage for internal circuitry 8/13/2009 10 PD-97414 iP2021CPbF Recommended PCB Layout Figure 11 Top Copper and Solder-mask Layer of PCB Layout PCB Layout Guidelines The following guidelines are recommended to reduce the parasitic values and optimize overall performance: • All pads on the iP2021C footprint design need to be Solder-mask defined (see Figure 11). Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint design guidance. • Place as many vias around the Power pads (VIN1, VIN2, VSW1, VSW2 and PGND) for both electrical and optimal thermal performance (see Figure 12). • A minimum of three 10µF, X5R, 16V ceramic capacitors per phase of iP2021C are needed for 28A operation at 1MHz. This will result in the lowest loss due to input capacitor ESR. • Placement of the ceramic input capacitors is critical to optimize switching performance. Place all six ceramic capacitors (C1-C6) right underneath the iP2021C footprint (see Figure 12 Bottom Component Layer). • Dedicate at least two layer for PGND only • Duplicate the Power Nodes on multiple layers (refer to AN1029). www.irf.com 8/13/2009 11 PD-97414 iP2021CPbF Figure 12 Top & Bottom Component and Via Placement (Topside, Transparent view down) www.irf.com 8/13/2009 12 PD-97414 iP2021CPbF Mechanical Outline Drawing 5 C 1.66 [.065] 0.15 [.006] C 2X 11 [0.433] B 0.07 [.0027] C A 6 PIN 1 IDENTIFICATION 1 VIN 1 12 11 10 2 VSW 1 3 PGND VIN 2 8 VSW 2 4 5 6 7.65 [0.301] 7 PGND 2X 6 0.15 [.006] C TOP VIEW SIDE VIEW 8.38 6.74 4 5.09 4 6 X 0.81 X 1.65 3.44 6 X 2.29 X 1.65 0.34 3.05 0.45 5.56 PIN 1 IDENTIFICATION PIN 1 IDENTIFICATION BOTTOM VIEW NOTES: 3 PGND 4 5 6 2 VSW 1 1 VIN 1 12 11 10 7 PGND 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 3. CONTROLLING DIMENSION: MILLIMETER. 8 VSW 2 4 LAND PAD OPENINGS. 5 PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SOLDER RESIST OPENING. 9 VIN 2 6 BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. NOT TO SCALE. 7 PIN 1 IDENTIFICATION BOTTOM VIEW ELECTRICAL I/O Figure 13 Mechanical Outline Drawing www.irf.com 8/13/2009 13 PD-97414 iP2021CPbF Figure 14 Tape and Reel Information www.irf.com 8/13/2009 14 PD-97414 iP2021CPbF Recommended Solder Paste Stencil Design Figure 15 Solder Paste Stencil Design The recommended reflow peak temperature is 260°C. The total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. www.irf.com 8/13/2009 15 PD-97414 iP2021CPbF Part Marking Figure 16 Part Marking www.irf.com 8/13/2009 16