IPB020N08N5

IPB020N08N5 MOSFET OptiMOSª5Power-Transistor,80V D²PAK Features •Idealforhighfrequencyswitchingandsync.rec. •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •N-channel,normallevel •100%avalanchetested •Pb-freeplating;RoHScompliant •QualifiedaccordingtoJEDEC1)fortargetapplications •Halogen-freeaccordingtoIEC61249-2-21 Table1KeyPerformanceParameters Parameter Value Unit VDS 80 V RDS(on),max 2.0 mΩ ID 173 A Qoss 156 nC QG(0V..10V) 133 nC Type/OrderingCode Package IPB020N08N5 PG-TO 263-3 1) Drain Pin 2, Tab Gate Pin 1 Source Pin 3 Marking 020N08N5 RelatedLinks - J-STD20 and JESD22 Final Data Sheet 1 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 173 133 A TC=25°C TC=100°C - 692 A TC=25°C - - 674 mJ ID=100A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 300 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Pulsed drain current1) 2) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - 0.4 0.5 K/W - Thermal resistance, junction - ambient, RthJA minimal footprint - - 62 K/W - Thermal resistance, junction - ambient, RthJA 6 cm2 cooling area3) - - 40 K/W - Soldering temperature, wave and reflow soldering are allowed - - 260 °C reflow MSL1 Tsold 1) See Diagram 3 for more detailed information See Diagram 13 for more detailed information 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) Final Data Sheet 3 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA 3.0 3.8 V VDS=VGS,ID=208µA - 0.1 10 1 100 µA VDS=80V,VGS=0V,Tj=25°C VDS=80V,VGS=0V,Tj=125°C IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 1.7 2.2 2.0 2.5 mΩ VGS=10V,ID=100A VGS=6V,ID=50A Gate resistance1) RG - 1.2 1.8 Ω - Transconductance gfs 100 200 - S |VDS|>2|ID|RDS(on)max,ID=100A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 80 - Gate threshold voltage VGS(th) 2.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics1) Parameter Symbol Input capacitance Values Min. Typ. Max. Ciss - 9300 12100 pF VGS=0V,VDS=40V,f=1MHz Output capacitance Coss - 1500 1950 pF VGS=0V,VDS=40V,f=1MHz Reverse transfer capacitance Crss - 65 114 pF VGS=0V,VDS=40V,f=1MHz Turn-on delay time td(on) - 28 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Rise time tr - 16 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Turn-off delay time td(off) - 62 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Fall time tf - 20 - ns VDD=40V,VGS=10V,ID=100A, RG,ext=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics2) Parameter Symbol Values Min. Typ. Max. Qgs - 43 - nC VDD=40V,ID=100A,VGS=0to10V Gate to drain charge Qgd - 28 42 nC VDD=40V,ID=100A,VGS=0to10V Switching charge Qsw - 45 - nC VDD=40V,ID=100A,VGS=0to10V Gate charge total Qg - 133 166 nC VDD=40V,ID=100A,VGS=0to10V Gate plateau voltage Vplateau - 4.6 - V VDD=40V,ID=100A,VGS=0to10V Gate charge total, sync. FET Qg(sync) - 115 - nC VDS=0.1V,VGS=0to10V Qoss - 156 207 nC VDD=40V,VGS=0V Gate to source charge 1) 1) 1) Output charge 1) 2) Defined by design. Not subject to production test. See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 Table7Reversediode Parameter Symbol Diode continous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) Values Unit Note/TestCondition 148 A TC=25°C - 692 A TC=25°C - 0.9 1.2 V VGS=0V,IF=100A,Tj=25°C trr - 85 1.2 ns VR=40V,IF=100A,diF/dt=100A/µs Qrr - 202 404 nC VR=40V,IF=100A,diF/dt=100A/µs Min. Typ. Max. IS - - IS,pulse - VSD Defined by design. Not subject to production test. Final Data Sheet 5 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 4Electricalcharacteristicsdiagrams Diagram2:Draincurrent 350 175 300 150 250 125 200 100 ID[A] Ptot[W] Diagram1:Powerdissipation 150 75 100 50 50 25 0 0 50 100 150 0 200 0 25 50 75 TC[°C] 100 125 150 175 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 100 10 1 µs 10 µs 100 µs 102 0.5 1 ms 101 ZthJC[K/W] ID[A] 10 ms DC 100 0.2 10-1 0.1 0.05 0.02 -1 10 0.01 single pulse -2 10 10-1 100 101 102 10 -2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 480 4 10V 440 7V 6V 360 6V 3 5.5 V 320 RDS(on)[mΩ] 280 ID[A] 5.5 V 5V 400 240 200 5V 7V 2 10 V 160 120 1 80 40 0 0 1 2 3 4 0 5 0 50 100 150 VDS[V] 200 250 300 350 400 450 500 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 400 250 350 200 300 150 gfs[S] ID[A] 250 200 100 150 100 175 °C 25 °C 50 50 0 0 2 4 6 8 0 0 VGS[V] 80 120 160 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 gfs=f(ID);Tj=25°C 7 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 5 4.0 3.5 4 2080 µA 3.0 VGS(th)[V] RDS(on)[mΩ] 208 µA 2.5 3 max 2 typ 2.0 1.5 1.0 1 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 60 Tj[°C] 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=100A;VGS=10V VGS(th)=f(Tj);VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 5 103 10 25 °C 175 °C 25 °C, max 175 °C, max Ciss 104 102 IF[A] C[pF] Coss 103 101 Crss 102 101 0 20 40 60 80 100 0.0 0.5 VDS[V] 1.5 2.0 2.5 VSD[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 IF=f(VSD);parameter:Tj 8 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 3 10 10 8 40 V 102 25 °C VGS[V] IAV[A] 6 100 °C 20 V 60 V 4 1 10 150 °C 2 100 100 101 102 103 0 0 tAV[µs] 50 100 150 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=100Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Gate charge waveforms 90 VBR(DSS)[V] 85 80 75 70 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 5PackageOutlines Figure1OutlinePG-TO263-3,dimensionsinmm/inches Final Data Sheet 10 Rev.2.2,2017-12-04 OptiMOSª5Power-Transistor,80V IPB020N08N5 RevisionHistory IPB020N08N5 Revision:2017-12-04,Rev.2.2 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2014-12-17 Release of final version 2.1 2017-07-11 Update product current 2.2 2017-12-04 Update Crss max TrademarksofInfineonTechnologiesAG AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™, EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™, ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™, PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™, SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™. 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Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer’scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer’sproductsandanyuseofthe productofInfineonTechnologiesincustomer’sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer’s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.2,2017-12-04