IPD036N04LGATMA1

Type IPD036N04L G ® OptiMOS 3 Power-Transistor Product Summary Features • Fast switching MOSFET for SMPS • Optimized technology for DC/DC converters V DS 40 V R DS(on),max 3.6 mΩ ID 90 A 1) • Qualified according to JEDEC for target applications • N-channel, logic level • Excellent gate charge x R DS(on) product (FOM) • Very low on-resistance R DS(on) • 100% Avalanche tested • Pb-free plating; RoHS compliant IPD036N04L G Type • Pb-free plating; RoHS compliant Package PG-TO252-3 Marking 036N04L Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value V GS=10 V, T C=25 °C 90 V GS=10 V, T C=100 °C 87 V GS=4.5 V, T C=25 °C 90 V GS=4.5 V, T C=100 °C 75 Unit A Pulsed drain current2) I D,pulse T C=25 °C 400 Avalanche current, single pulse3) I AS T C=25 °C 90 Avalanche energy, single pulse E AS I D=90 A, R GS=25 Ω 55 mJ Gate source voltage V GS ±20 V 1) Rev. 1.0 J-STD20 and JESD22 page 1 2007-12-06 IPD036N04L G Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Power dissipation P tot Operating and storage temperature T j, T stg Value T C=25 °C IEC climatic category; DIN IEC 68-1 Parameter Unit 94 W -55 ... 175 °C 55/175/56 Values Symbol Conditions Unit min. typ. max. - - 1.6 minimal footprint - - 75 6 cm² cooling area4) - - 50 Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 40 - - Gate threshold voltage V GS(th) V DS=V GS, I D=45 µA 1.2 - 2 Zero gate voltage drain current I DSS V DS=40 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=40 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=90 A - 3.9 4.9 mΩ V GS=10 V, I D=90 A - 3.0 3.6 - 1.6 - Ω 85 170 - S Gate resistance RG Transconductance g fs 2) See figure 3 for more detailed information 3) See figure 13 for more detailed information |V DS|>2|I D|R DS(on)max, I D=90 A 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.0 page 2 2007-12-06 IPD036N04L G Parameter Values Symbol Conditions Unit min. typ. max. - 4700 6300 - 1000 1300 Dynamic characteristics Input capacitance C iss V GS=0 V, V DS=20 V, f =1 MHz Output capacitance C oss Reverse transfer capacitance Crss - 54 - Turn-on delay time t d(on) - 9.3 - Rise time tr - 5.4 - Turn-off delay time t d(off) - 37 - Fall time tf - 6.0 - Gate to source charge Q gs - 14 - Gate charge at threshold Q g(th) - 7.4 - Gate to drain charge Q gd - 6.1 - Switching charge Q sw - 13 - Gate charge total Qg - 59 78 Gate plateau voltage V plateau - 3.0 - Gate charge total Qg V DD=20 V, I D=30 A, V GS=0 to 4.5 V - 28 38 Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 10 V - 55 - Output charge Q oss V DD=20 V, V GS=0 V - 37 - - - 78 - - 400 V DD=20 V, V GS=10 V, I D=30 A, R G=1.6 Ω pF ns Gate Charge Characteristics5) V DD=20 V, I D=30 A, V GS=0 to 10 V nC V nC Reverse Diode Diode continuous forward current IS A T C=25 °C Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=90 A, T j=25 °C - 0.92 1.2 Reverse recovery charge Q rr V R=20 V, I F=I S, di F/dt =400 A/µs - 45 - 5) Rev. 1.0 V nC See figure 16 for gate charge parameter definition page 3 2007-12-06 IPD036N04L G 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); V GS≥10 V 100 80 80 60 60 I D [A] P tot [W] 100 40 40 20 20 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 103 10 1 µs limited by on-state resistance 10 µs 10 2 100 µs 1 1 ms 101 0.5 Z thJC [K/W] I D [A] DC 10 ms 0.2 0.1 0.05 0.1 10 0 0.02 0.01 single pulse 10-1 10-1 0.01 100 101 102 0 0 0 0 0 1 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.0 0 10-6 page 4 2007-12-06 IPD036N04L G 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 320 12 3V 5V 280 4.5 V 3.2 V 10 10 V 240 8 R DS(on) [mΩ ] 200 I D [A] 4V 160 120 3.5 V 6 4V 4.5 V 4 5V 80 3.5 V 40 3.2 V 10 V 2 3V 2.8 V 0 0 0 1 2 3 0 20 40 V DS [V] 60 80 100 160 200 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 200 240 200 160 160 I D [A] g fs [S] 120 120 80 80 40 40 175 °C 25 °C 0 0 0 1 2 3 4 5 Rev. 1.0 0 40 80 120 I D [A] V GS [V] page 5 2007-12-06 IPD036N04L G 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=90 A; V GS=10 V V GS(th)=f(T j); V GS=V DS; I D=250 µA 8 2.5 7 2 5 98 % V GS(th) [V] R DS(on) [mΩ ] 6 4 1 typ 3 1.5 2 0.5 1 0 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 104 1000 25 °C, 98% Ciss 175 °C, 98% Coss 100 25 °C I F [A] C [pF] 10 3 102 175 °C 10 Crss 101 1 0 10 20 30 40 Rev. 1.0 0.0 0.5 1.0 1.5 2.0 V SD [V] V DS [V] page 6 2007-12-06 IPD036N04L G 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=30 A pulsed parameter: T j(start) parameter: V DD 100 12 20 V 25 °C 10 8V 100 °C 32 V 8 V GS [V] I AV [A] 150 °C 10 z 6 4 2 1 0 10-1 100 101 102 103 0 10 t AV [µs] 20 30 40 50 60 70 Q gate [nC] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 45 V GS Qg V BR(DSS) [V] 40 35 V g s(th) 30 25 Q g(th) Q sw Q gs 20 -60 -20 20 60 100 140 Q g ate Q gd 180 T j [°C] Rev. 1.0 page 7 2007-12-06 IPD036N04L G Package Outline Footprint: Rev. 1.0 PG-TO252-3 Packaging: page 8 2007-12-06 IPD036N04L G Published by Infineon Technologies AG 81726 Munich, Germany © 2007 Infineon Technologies AG All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 9 2007-12-06