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IPD046N08N5

IPD046N08N5

  • 厂商:

    EUPEC(英飞凌)

  • 封装:

    TO-252-2(DPAK)

  • 描述:

    IPD046N08N5

  • 数据手册
  • 价格&库存
IPD046N08N5 数据手册
IPD046N08N5 MOSFET OptiMOSTM5Power-Transistor,80V D-PAK Features tab •N-channel,normallevel •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •175°Coperatingtemperature •Pb-freeleadplating;RoHScompliant •QualifiedaccordingtoJEDEC1)fortargetapplication •Idealforhigh-frequencyswitchingandsynchronousrectification •Halogen-freeaccordingtoIEC61249-2-21 1 3 Table1KeyPerformanceParameters Parameter Value Unit VDS 80 V RDS(on),max 4.6 mΩ ID 90 A Drain Pin 2, Tab Gate Pin 1 Source Pin 3 Type/OrderingCode Package Marking RelatedLinks IPD046N08N5 PG-TO252-3 046N08N - 1) J-STD20 and JESD22 Final Data Sheet 1 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 90 82 A TC=25°C1) TC=100°C - 360 A TC=25°C - - 75 mJ ID=90A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 125 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Pulsed drain current1) 2) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - 0.7 1.2 K/W - Thermal resistance, junction - ambient, RthJA minimal footprint - - 75 K/W - Thermal resistance, junction - ambient, RthJA 6 cm2 cooling area3) - - 50 K/W - Soldering temperature, wave and reflow soldering allowed - - 260 °C reflow MSL1 Tsold 1) See Diagram 3 for more detailed information See Diagram 13 for more detailed information 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) Final Data Sheet 3 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA 3.0 3.8 V VDS=VGS,ID=65µA - 0.1 10 1 100 µA VDS=80V,VGS=0V,Tj=25°C VDS=80V,VGS=0V,Tj=125°C IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 4.0 5.4 4.6 6.3 mΩ VGS=10V,ID=45A VGS=6V,ID=23A Gate resistance1) RG - 1.1 1.7 Ω - Transconductance gfs 41 82 - S |VDS|>2|ID|RDS(on)max,ID=45A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 80 - Gate threshold voltage VGS(th) 2.2 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics1) Parameter Symbol Input capacitance Values Min. Typ. Max. Ciss - 2930 3800 pF VGS=0V,VDS=40V,f=1MHz Output capacitance Coss - 488 630 pF VGS=0V,VDS=40V,f=1MHz Reverse transfer capacitance Crss - 23 40 pF VGS=0V,VDS=40V,f=1MHz Turn-on delay time td(on) - 11 - ns VDD=40V,VGS=10V,ID=45A, RG,ext=1.6Ω Rise time tr - 6 - ns VDD=40V,VGS=10V,ID=45A, RG,ext=1.6Ω Turn-off delay time td(off) - 21 - ns VDD=40V,VGS=10V,ID=45A, RG,ext=1.6Ω Fall time tf - 6 - ns VDD=40V,VGS=10V,ID=45A, RG,ext=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics2) Parameter Symbol Values Min. Typ. Max. Qgs - 14 - nC VDD=40V,ID=45A,VGS=0to10V Gate to drain charge Qgd - 9 14 nC VDD=40V,ID=45A,VGS=0to10V Switching charge Qsw - 14 - nC VDD=40V,ID=45A,VGS=0to10V Gate charge total Qg - 42 53 nC VDD=40V,ID=45A,VGS=0to10V Gate plateau voltage Vplateau - 4.8 - V VDD=40V,ID=45A,VGS=0to10V Output charge1) Qoss - 51 68 nC VDD=40V,VGS=0V Gate to source charge 1) 1) 1) 2) Defined by design. Not subject to production test See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 Table7Reversediode Parameter Symbol Diode continous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) Values Unit Note/TestCondition 90 A TC=25°C - 360 A TC=25°C - 0.9 1.2 V VGS=0V,IF=45A,Tj=25°C trr - 41 82 ns VR=40V,IF=45,diF/dt=100A/µs Qrr - 46 92 nC VR=40V,IF=45,diF/dt=100A/µs Min. Typ. Max. IS - - IS,pulse - VSD Defined by design. Not subject to production test Final Data Sheet 5 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 150 100 125 80 100 ID[A] Ptot[W] 60 75 40 50 20 25 0 0 50 100 150 0 200 0 50 100 TC[°C] 150 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 1 µs 10 µs 102 100 ZthJC[K/W] 0.5 ID[A] 100 µs 0.2 0.1 0.05 101 10-1 1 ms 0.02 0.01 10 ms single pulse DC 0 10 10-1 100 101 102 10-2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 360 10 8V 10 V 320 4.5 V 7V 5.5 V 8 6.5 V 280 6V 6.5 V 200 RDS(on)[mΩ] ID[A] 240 6V 160 8V 10 V 4 5.5 V 120 80 5V 40 4.5 V 0 7V 6 0 1 2 3 4 2 0 5 0 40 80 VDS[V] 120 160 200 240 280 320 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 150 160 120 120 ID[A] gfs[S] 90 80 60 175 °C 40 25 °C 30 0 0 2 4 6 8 0 0 VGS[V] 80 120 160 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 gfs=f(ID);Tj=25°C 7 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 10 4 8 650 µA 3 65 µA max VGS(th)[V] RDS(on)[mΩ] 6 typ 4 2 1 2 0 -60 -20 20 60 100 140 0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=45A;VGS=10V VGS(th)=f(Tj);VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 175 °C 25 °C max 175 °C max Ciss Coss 102 IF[A] C[pF] 103 102 101 Crss 101 0 20 40 60 80 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 8 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 10 40 V 8 25 °C 16 V 6 VGS[V] 100 °C IAV[A] 64 V 101 4 150 °C 2 100 10-1 100 101 102 103 tAV[µs] 0 0 10 20 30 40 50 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=45Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 90 VBR(DSS)[V] 85 80 75 70 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 5PackageOutlines Figure1OutlinePG-TO252-3,dimensionsinmm/inches Final Data Sheet 10 Rev.2.1,2020-03-10 OptiMOSTM5Power-Transistor,80V IPD046N08N5 RevisionHistory IPD046N08N5 Revision:2020-03-10,Rev.2.1 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2016-09-12 Release of final version 2.1 2020-03-10 Update "Marking" Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2020InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (“Beschaffenheitsgarantie”). Withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer’scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer’sproductsandanyuseofthe productofInfineonTechnologiesincustomer’sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer’s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.1,2020-03-10
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