IPD050N10N5
MOSFET
OptiMOSTM5Power-Transistor,100V
D-PAK
Features
•N-channel,normallevel
•ExcellentgatechargexRDS(on)product(FOM)
•Verylowon-resistanceRDS(on)
•175°Coperatingtemperature
•Pb-freeleadplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplication
•Idealforhigh-frequencyswitchingandsynchronousrectification
•Halogen-freeaccordingtoIEC61249-2-21
tab
1
2
3
Table1KeyPerformanceParameters
Parameter
Value
Unit
VDS
100
V
RDS(on),max
5.0
mΩ
ID
80
A
QOSS
67
nC
QG(0V..10V)
51
nC
Type/OrderingCode
Package
IPD050N10N5
P-TO252-3
1)
Drain
Pin 2, Tab
Gate
Pin 1
Source
Pin 3
Marking
050N10N5
RelatedLinks
-
J-STD20 and JESD22
Final Data Sheet
1
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Final Data Sheet
2
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Parameter
Symbol
Continuous drain current
Values
Unit
Note/TestCondition
80
80
A
TC=25°C1)
TC=100°C
-
320
A
TC=25°C
-
-
110
mJ
ID=80A,RGS=25Ω
VGS
-20
-
20
V
-
Power dissipation
Ptot
-
-
150
W
TC=25°C
Operating and storage temperature
Tj,Tstg
-55
-
175
°C
IEC climatic category;
DIN IEC 68-1: 55/175/56
Unit
Note/TestCondition
Min.
Typ.
Max.
ID
-
-
ID,pulse
-
Avalanche energy, single pulse
EAS
Gate source voltage
Pulsed drain current1)
2)
2Thermalcharacteristics
Table3Thermalcharacteristics
Parameter
Symbol
Thermal resistance, junction - case
Values
Min.
Typ.
Max.
RthJC
-
0.6
1
K/W
-
Thermal resistance, junction - ambient,
RthJA
minimal footprint
-
-
75
K/W
-
Thermal resistance, junction - ambient,
RthJA
6 cm2 cooling area3)
-
-
50
K/W
-
Soldering temperature, wave and
reflow soldering are allowed
-
-
260
°C
reflow MSL1
Tsold
1)
See Diagram 3 for more detailed information
See Diagram 13 for more detailed information
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
2)
Final Data Sheet
3
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
3Electricalcharacteristics
Table4Staticcharacteristics
Parameter
Symbol
Drain-source breakdown voltage
Values
Unit
Note/TestCondition
-
V
VGS=0V,ID=1mA
3.0
3.8
V
VDS=VGS,ID=84µA
-
0.1
10
1
100
µA
VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
IGSS
-
1
100
nA
VGS=20V,VDS=0V
Drain-source on-state resistance
RDS(on)
-
4.3
5.1
5
6.7
mΩ
VGS=10V,ID=40A
VGS=6V,ID=20A
Gate resistance1)
RG
-
1.2
1.8
Ω
-
Transconductance
gfs
48
95
-
S
|VDS|>2|ID|RDS(on)max,ID=40A
Unit
Note/TestCondition
Min.
Typ.
Max.
V(BR)DSS
100
-
Gate threshold voltage
VGS(th)
2.2
Zero gate voltage drain current
IDSS
Gate-source leakage current
Table5Dynamiccharacteristics1)
Parameter
Symbol
Input capacitance
Values
Min.
Typ.
Max.
Ciss
-
3600
4700
pF
VGS=0V,VDS=50V,f=1MHz
Output capacitance
Coss
-
560
730
pF
VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance
Crss
-
25
44
pF
VGS=0V,VDS=50V,f=1MHz
Turn-on delay time
td(on)
-
13
-
ns
VDD=50V,VGS=10V,ID=40A,
RG,ext=1.6Ω
Rise time
tr
-
7
-
ns
VDD=50V,VGS=10V,ID=40A,
RG,ext=1.6Ω
Turn-off delay time
td(off)
-
27
-
ns
VDD=50V,VGS=10V,ID=40A,
RG,ext=1.6Ω
Fall time
tf
-
7
-
ns
VDD=50V,VGS=10V,ID=40A,
RG,ext=1.6Ω
Unit
Note/TestCondition
Table6Gatechargecharacteristics2)
Parameter
Symbol
Values
Min.
Typ.
Max.
Qgs
-
16
-
nC
VDD=50V,ID=40A,VGS=0to10V
Gate to drain charge
Qgd
-
10
16
nC
VDD=50V,ID=40A,VGS=0to10V
Switching charge
Qsw
-
16
-
nC
VDD=50V,ID=40A,VGS=0to10V
Gate charge total
Qg
-
51
64
nC
VDD=50V,ID=40A,VGS=0to10V
Gate plateau voltage
Vplateau
-
4.5
-
V
VDD=50V,ID=40A,VGS=0to10V
Output charge1)
Qoss
-
67
89
nC
VDD=50V,VGS=0V
Gate to source charge
1)
1)
1)
2)
Defined by design. Not subject to production test
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
Table7Reversediode
Parameter
Symbol
Diode continous forward current
Diode pulse current
Diode forward voltage
1)
Reverse recovery time
1)
Reverse recovery charge
1)
Values
Unit
Note/TestCondition
80
A
TC=25°C
-
320
A
TC=25°C
-
0.9
1.2
V
VGS=0V,IF=40A,Tj=25°C
trr
-
48
96
ns
VR=50V,IF=40A,diF/dt=100A/µs
Qrr
-
62
124
nC
VR=50V,IF=40A,diF/dt=100A/µs
Min.
Typ.
Max.
IS
-
-
IS,pulse
-
VSD
Defined by design. Not subject to production test
Final Data Sheet
5
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
4Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
Diagram2:Draincurrent
175
100
150
80
60
100
ID[A]
Ptot[W]
125
75
40
50
20
25
0
0
50
100
150
0
200
0
50
100
TC[°C]
150
200
TC[°C]
Ptot=f(TC)
ID=f(TC);VGS≥10V
Diagram3:Safeoperatingarea
Diagram4:Max.transientthermalimpedance
3
101
10
1 µs
10 µs
102
100
100 µs
ID[A]
ZthJC[K/W]
0.5
1 ms
1
10
0.2
0.1
10
-1
10 ms
0.05
0.02
0.01
DC
single pulse
100
10-1
100
101
102
103
10-2
10-5
10-4
VDS[V]
10-2
10-1
100
tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp
Final Data Sheet
10-3
ZthJC=f(tp);parameter:D=tp/T
6
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
Diagram5:Typ.outputcharacteristics
Diagram6:Typ.drain-sourceonresistance
360
10
8V
320
10 V
7V
6.5 V
8
280
5V
5.5 V
6V
6V
RDS(on)[mΩ]
ID[A]
240
200
160
5.5 V
6.5 V
6
7V
8V
10 V
4
120
80
5V
40
0
2
4.5 V
0
1
2
3
4
0
5
0
40
80
VDS[V]
120
160
200
240
280
320
ID[A]
ID=f(VDS);Tj=25°C;parameter:VGS
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
Diagram8:Typ.forwardtransconductance
180
200
150
160
120
gfs[S]
ID[A]
120
90
80
60
175 °C
0
40
25 °C
30
0
2
4
6
8
0
0
VGS[V]
80
120
160
ID[A]
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj
Final Data Sheet
40
gfs=f(ID);Tj=25°C
7
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
Diagram9:Drain-sourceon-stateresistance
Diagram10:Typ.gatethresholdvoltage
12
4
10
840 µA
3
RDS(on)[mΩ]
8
84 µA
VGS(th)[V]
max
6
typ
2
4
1
2
0
-60
-20
20
60
100
140
0
-60
180
-20
20
Tj[°C]
60
100
140
180
Tj[°C]
RDS(on)=f(Tj);ID=40A;VGS=10V
VGS(th)=f(Tj);VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
Diagram12:Forwardcharacteristicsofreversediode
4
103
10
25 °C
175 °C
25 °C, 98%
175 °C, 98%
Ciss
103
102
IF[A]
C[pF]
Coss
102
101
Crss
101
0
20
40
60
80
100
100
0.0
0.5
VDS[V]
C=f(VDS);VGS=0V;f=1MHz
Final Data Sheet
1.0
1.5
2.0
VSD[V]
IF=f(VSD);parameter:Tj
8
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
Diagram13:Avalanchecharacteristics
Diagram14:Typ.gatecharge
2
10
10
50 V
8
25 °C
20 V
100 °C
6
VGS[V]
IAV[A]
150 °C
80 V
101
4
2
100
10-1
100
101
102
103
0
0
tAV[µs]
20
40
60
Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
VGS=f(Qgate);ID=40Apulsed;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Gate charge waveforms
110
VBR(DSS)[V]
105
100
95
90
-60
-20
20
60
100
140
180
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA
Final Data Sheet
9
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
5PackageOutlines
Figure1OutlineP-TO252-3,dimensionsinmm/inches
Final Data Sheet
10
Rev.2.1,2017-01-17
OptiMOSTM5Power-Transistor,100V
IPD050N10N5
RevisionHistory
IPD050N10N5
Revision:2017-01-17,Rev.2.1
Previous Revision
Revision
Date
Subjects (major changes since last revision)
2.0
2016-11-22
Release of final version
2.1
2017-01-17
Update Idss max at Tj=25°C
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Final Data Sheet
11
Rev.2.1,2017-01-17