IPD50N04S309ATMA1

IPD50N04S3-09 OptiMOS®-T Power-Transistor Product Summary V DS 40 V R DS(on),max 9 mΩ ID 50 A Features • N-channel - Enhancement mode PG-TO252-3-11 • Automotive AEC Q101 qualified • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • 100% Avalanche tested Type Package Marking IPD50N04S3-09 PG-TO252-3-11 3N0409 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current ID Conditions Value T C=25 °C, V GS=10 V1) 50 T C=100 °C, V GS=10 V2) Unit A 43 Pulsed drain current2) I D,pulse T C=25 °C 200 Avalanche energy, single pulse2) E AS I D=25 A 140 mJ Avalanche current, single pulse I AS 50 A Gate source voltage V GS ±20 V Power dissipation P tot 63 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.1 55/175/56 page 1 2009-11-03 IPD50N04S3-09 Parameter Symbol Values Conditions Unit min. typ. max. - - 2.4 minimal footprint - - 62 6 cm2 cooling area3) - - 40 Thermal characteristics2) Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 40 - - Gate threshold voltage V GS(th) V DS=V GS, I D=28 µA 2.1 3.0 4.0 Zero gate voltage drain current I DSS V DS=40 V, V GS=0 V, T j=25 °C - - 1 - - 100 V DS=40 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - - 100 nA Drain-source on-state resistance RDS(on) V GS=10 V, I D=50 A - 7.5 9.0 mΩ Rev. 1.1 page 2 2009-11-03 IPD50N04S3-09 Parameter Symbol Values Conditions Unit min. typ. max. - 1350 1750 - 720 940 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 55 85 Turn-on delay time t d(on) - 11 - Rise time tr - 7 - Turn-off delay time t d(off) - 16 - Fall time tf - 6 - Gate to source charge Q gs - 8 11 Gate to drain charge Q gd - 5 8 Gate charge total Qg - 20 26 Gate plateau voltage V plateau - 5.8 - V - - 50 A - - 200 - 0.9 1.3 V - 30 - ns - 32 - nC V GS=0 V, V DS=25 V, f =1 MHz V DD=20 V, V GS=10 V, I D=50 A, R G=3.5 Ω pF ns Gate Charge Characteristics2) V DD=32 V, I D=50 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=50 A, T j=25 °C V R=20 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 2.4K/W the chip is able to carry 61A at 25°C. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2009-11-03 IPD50N04S3-09 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 70 60 60 50 40 I D [A] P tot [W] 40 30 20 20 10 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 0.5 1 µs 0 10 10 µs 100 0.1 Z thJC [K/W] I D [A] 100 µs 1 ms 0.05 -1 10 0.01 10 10-2 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.1 single pulse page 4 2009-11-03 IPD50N04S3-09 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 200 25 7V 160 6V 5.5 V 23 6.5 V 21 10 V 120 R DS(on) [mΩ] 19 I D [A] 6.5 V 80 6V 17 15 13 7V 11 5.5 V 40 9 10 V 7 5V 5 0 0 2 4 6 0 8 20 40 60 80 100 120 140 180 I D [A] V DS [V] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6V R DS(on) = f(T j); I D = 50 A; V GS = 10 V parameter: T j 200 15 25 °C -55 °C 14 160 13 175 °C 12 I D [A] R DS(on) [mΩ] 120 80 11 10 9 8 40 7 6 0 2 3 4 5 6 7 8 V GS [V] Rev. 1.1 5 -60 -20 20 60 100 T j [°C] page 5 2009-11-03 IPD50N04S3-09 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 4 3.5 V GS(th) [V] C [pF] Ciss 3 150 µA 103 Coss 30 µA 2.5 102 2 Crss 1.5 101 1 -60 -20 20 60 100 140 0 180 5 10 15 20 25 30 V DS [V] T j [°C] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I A S= f(t AV) parameter: T j parameter: T j(start) 100 103 150 °C 100 °C 25 °C I F [A] I AV [A] 102 101 175 °C 25 °C 0.6 0.8 100 1 0 0.2 0.4 1 1.2 1.4 V SD [V] Rev. 1.1 10 1 10 100 1000 t AV [µs] page 6 2009-11-03 IPD50N04S3-09 13 Typical avalanche energy 14 Typ. drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 55 300 12.5 A 250 50 V BR(DSS) [V] E AS [mJ] 200 150 25 A 45 40 100 50 A 35 50 30 0 25 75 125 -60 175 -20 T j [°C] 20 60 100 140 180 T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 12 V GS 8V 10 Qg 32 V V GS [V] 8 6 V g s(th) 4 2 Q g (th) Q sw Q gs 0 0 10 20 Q gate Q gd 30 Q gate [nC] Rev. 1.1 page 7 2009-11-03 IPD50N04S3-09 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2008 All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non‑infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.1 page 8 2009-11-03 IPD50N04S3-09 Revision History Version Date Changes Update of SOA diagram for 1ms 03.10.2009 curve Rev. 1.1 Rev. 1.1 page 9 2009-11-03