IPD50P04P4-13
Type
OptiMOS®-P2 Power-Transistor
Product Summary
VDS
-40
V
RDS(on)
12.6
mW
ID
-50
A
Features
• P-channel - Normal Level - Enhancement mode
• AEC qualified
PG-TO252-3-313
• MSL1 up to 260°C peak reflow
Tab
• 175°C operating temperature
• Green package (RoHS compliant)
1
3
• 100% Avalanche tested
Source
pin 3
Gate
pin 1
Type
Package
Marking
IPD50P04P4-13
PG-TO252-3-313
4P0413
Drain
pin 2/Tab
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol
Continuous drain current1)
ID
Conditions
T C=25°C,
V GS=-10V
T C=100°C,
Value
-50
V GS=-10V2)
-45
Unit
A
Pulsed drain current2)
I D,pulse
T C=25°C
-200
Avalanche energy, single pulse2)
E AS
I D=-25A
18
mJ
Avalanche current, single pulse
I AS
-
-50
A
Gate source voltage
V GS
-
±20
V
Power dissipation
P tot
T C=25 °C
58
W
Operating and storage temperature
T j, T stg
-
-55 ... +175
°C
IEC climatic category; DIN IEC 68-1
-
-
55/175/56
Rev. 1.3
page 1
2019-07-16
IPD50P04P4-13
Parameter
Symbol
Values
Conditions
Unit
min.
typ.
max.
Thermal characteristics2)
Thermal resistance, junction - case
R thJC
-
-
-
2.6
SMD version, device on PCB
R thJA
minimal footprint
-
-
62
6 cm2 cooling area3)
-
-
40
K/W
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0V, I D= -1mA
-40
-
-
Gate threshold voltage
V GS(th)
V DS=V GS, I D=-85µA
-2.0
-3.0
-4.0
Zero gate voltage drain current
I DSS
V DS=-32V, V GS=0V,
T j=25°C
-
-0.05
-1
T j=125°C2)
-
-20
-200
V DS=-32V, V GS=0V,
V
µA
Gate-source leakage current
I GSS
V GS=-20V, V DS=0V
-
-
-100
nA
Drain-source on-state resistance
R DS(on)
V GS=-10V, I D=-50A
-
9.2
12.6
mW
Rev. 1.3
page 2
2019-07-16
IPD50P04P4-13
Parameter
Symbol
Values
Conditions
Unit
min.
typ.
max.
-
2820
3670
-
1000
1500
Dynamic characteristics2)
Input capacitance
C iss
Output capacitance
C oss
Reverse transfer capacitance
Crss
-
30
60
Turn-on delay time
t d(on)
-
17
-
Rise time
tr
-
10
-
Turn-off delay time
t d(off)
-
22
-
Fall time
tf
-
28
-
Gate to source charge
Q gs
-
14
19
Gate to drain charge
Q gd
-
7
14
Gate charge total
Qg
-
39
51
Gate plateau voltage
V plateau
-
5.4
-
V
-
-
-50
A
-
-
-200
-
-1
-1.3
V
-
39
-
ns
-
32
-
nC
V GS=0V, V DS=-25V,
f =1MHz
V DD=-20V,
V GS=-10V, I D=-50A,
R G=3.5W
pF
ns
Gate Charge Characteristics2)
V DD=-32V, I D=-50A,
V GS=0 to -10V
nC
Reverse Diode
Diode continous forward current2)
IS
Diode pulse current2)
I S,pulse
Diode forward voltage
V SD
Reverse recovery time2)
t rr
Reverse recovery charge2)
Q rr
T C=25°C
V GS=0V, I F=-50A,
T j=25°C
V R=-20V, I F=-50A,
di F/dt =-100A/µs
1)
Current is limited by bondwire; with an R thJC = 2.6K/W the chip is able to carry -55A at 25°C.
2)
Defined by design. Not subject to production test.
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.3
page 3
2019-07-16
IPD50P04P4-13
1 Power dissipation
2 Drain current
P tot = f(T C); V GS = -10V
I D = f(T C); V GS = -10V
80
60
60
-ID [A]
Ptot [W]
40
40
20
20
0
0
0
50
100
150
200
0
50
100
TC [°C]
150
200
TC [°C]
3 Safe operating area
4 Max. transient thermal impedance
I D = f(V DS); T C = 25 °C; D = 0
Z thJC = f(t p)
parameter: t p
parameter: D =t p/T
1000
101
1 µs
0.5 0
10
10 µs
100
ZthJC [K/W]
100 µs
-ID [A]
1 ms
0.1
0.05
10-1
0.01
10
single pulse
10-2
1
10-3
0.1
1
10
100
-VDS [V]
Rev. 1.3
10-6
10-5
10-4
10-3
10-2
10-1
100
tp [s]
page 4
2019-07-16
IPD50P04P4-13
5 Typ. output characteristics
6 Typ. drain-source on-state resistance
I D = f(V DS); T j = 25 °C
R DS(on) = (I D); T j = 25 °C
parameter: -V GS
parameter: -V GS
40
200
5V
35
8V
10V
7V
30
RDS(on) [mW]
-ID [A]
150
100
25
6V
20
6V
15
50
7V
8V
10
10V
5V
5
0
0
2
4
0
6
25
50
-ID [A]
-VDS [V]
7 Typ. transfer characteristics
8 Typ. drain-source on-state resistance
I D = f(V GS); V DS = -6V
R DS(on) = f(T j); I D = -50 A; V GS = -10 V
parameter: T j
200
16
14
RDS(on) [mW]
-ID [A]
150
100
50
12
10
175 °C
8
25 °C
-55 °C
5
6
6
0
2
3
4
7
8
-20
20
60
100
140
180
Tj [°C]
-VGS [V]
Rev. 1.3
-60
page 5
2019-07-16
IPD50P04P4-13
9 Typ. gate threshold voltage
10 Typ. capacitances
V GS(th) = f(T j); V GS = V DS
C = f(V DS); V GS = 0 V; f = 1 MHz
parameter: -I D
104
4
3.5
Ciss
850µA
103
85µA
Coss
C [pF]
-VGS(th) [V]
3
2.5
102
2
Crss
1.5
101
1
-60
-20
20
60
100
140
0
180
5
10
15
20
25
30
140
180
-VDS [V]
Tj [°C]
11 Typical forward diode characteristicis
12 Drain-source breakdown voltage
IF = f(VSD)
V BR(DSS) = f(T j); I D = -1 mA
parameter: T j
44
103
43
42
-IF [A]
-VBR(DSS) [V]
102
41
40
175 °C 25 °C
101
39
38
37
100
0
0.4
0.8
1.2
1.6
-VSD [V]
Rev. 1.3
-60
-20
20
60
100
Tj [°C]
page 6
2019-07-16
IPD50P04P4-13
13 Typ. gate charge
14 Gate charge waveforms
V GS = f(Q gate); I D = -50 A pulsed
parameter: V DD
10
9
V GS
-8V
Qg
8
-32V
7
-VGS [V]
6
5
4
3
2
Q gate
1
Q gs
Q gd
0
0
10
20
30
40
Qgate [nC]
Rev. 1.3
page 7
2019-07-16
IPD50P04P4-13
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2019
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.3
page 8
2019-07-16
IPD50P04P4-13
Revision History
Version
Rev. 1.3
Date
Changes
1.0 14.03.2011
Final Data Sheet
1.1 21.12.2012
Update of diagram 8
1.2 09.12.2013
Update of Idpuls and SOA
1.3 16.07.2019
graphs corrected
page 9
2019-07-16
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