IPF13N03LA G

OptiMOS®2 Power-Transistor IPD13N03LA G IPF13N03LA G IPS13N03LA G IPU13N03LA G Product Summary Features • Ideal for high-frequency dc/dc converters • Qualified according to JEDEC1) for target applications V DS 25 V R DS(on),max 12.8 mΩ ID 30 A • N-channel, logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature • Pb-free lead plating; RoHS compliant Type IPD13N03LA IPF13N03LA IPS13N03LA IPU13N03LA Package P-TO252-3-11 P-TO252-3-23 P-TO251-3-11 P-TO251-3-1 Marking 13N03LA 13N03LA 13N03LA 13N03LA Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current ID Value T C=25 °C2) 30 T C=100 °C 30 Unit A Pulsed drain current I D,pulse T C=25 °C3) 210 Avalanche energy, single pulse E AS I D=24 A, R GS=25 Ω 60 mJ Reverse diode dv /dt dv /dt I D=30 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 kV/µs Gate source voltage4) V GS Power dissipation P tot Operating and storage temperature T j, T stg T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 2.2 ±20 V 46 W -55 ... 175 °C 55/175/56 page 1 2008-04-14 Parameter IPD13N03LA G IPF13N03LA G IPS13N03LA G IPU13N03LA G Values Symbol Conditions Unit min. typ. max. minimal footprint - - 3.2 75 6 cm2 cooling area5) - - 50 25 - - Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA Gate threshold voltage V GS(th) V DS=V GS, I D=20 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=25 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=25 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=20 A - 17.5 21.9 mΩ V GS=10 V, I D=30 A - 10.7 12.8 - 0.9 - Ω 18 36 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=30 A 1) J-STD20 and JESD22 2) Current is limited by bondwire; with an R thJC=3.2 K/W the chip is able to carry 47 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D