IPP076N15N5

IPP076N15N5 MOSFET OptiMOSª5Power-Transistor,150V TO-220-3 tab Features •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •Verylowreverserecoverycharge(Qrr) •175°Coperatingtemperature •Pb-freeleadplating;RoHScompliant •QualifiedaccordingtoJEDEC1)fortargetapplication •Idealforhigh-frequencyswitchingandsynchronousrectification •Halogen-freeaccordingtoIEC61249-2-21 Table1KeyPerformanceParameters Parameter Value Unit VDS 150 V RDS(on),max 7.6 mΩ ID 112 A Qrr 96 nC Type/OrderingCode Package IPP076N15N5 PG-TO220-3 1) Drain Pin 2, Tab Gate Pin 1 Source Pin 3 Marking 076N15N5 RelatedLinks - J-STD20 and JESD22 Final Data Sheet 1 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Final Data Sheet 2 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 112 79 A TC=25°C TC=100°C - 448 A TC=25°C - - 130 mJ ID=100A,RGS=25Ω VGS -20 - 20 V - Power dissipation Ptot - - 214 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Pulsed drain current1) 2) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - 0.4 0.7 K/W - Thermal resistance, junction - ambient, RthJA minimal footprint - - 62 K/W - Unit Note/TestCondition 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Min. Typ. Max. V(BR)DSS 150 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 3.0 3.8 4.6 V VDS=VGS,ID=160µA Zero gate voltage drain current IDSS - 0.1 10 1 100 µA VDS=120V,VGS=0V,Tj=25°C VDS=120V,VGS=0V,Tj=125°C Gate-source leakage current IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 5.9 6.4 7.6 8.4 mΩ VGS=10V,ID=56A VGS=8V,ID=28A Gate resistance3) RG - 1.1 1.7 Ω - Transconductance gfs 45 90 - S |VDS|>2|ID|RDS(on)max,ID=56A 1) See Diagram 3 See Diagram 13 3) Defined by design. Not subject to production test. 2) Final Data Sheet 3 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 Table5Dynamiccharacteristics Parameter Symbol Values Unit Note/TestCondition 4700 pF VGS=0V,VDS=75V,f=1MHz 900 1200 pF VGS=0V,VDS=75V,f=1MHz - 21 37 pF VGS=0V,VDS=75V,f=1MHz td(on) - 14 - ns VDD=75V,VGS=10V,ID=56A, RG,ext=1.6Ω Rise time tr - 4 - ns VDD=75V,VGS=10V,ID=56A, RG,ext=1.6Ω Turn-off delay time td(off) - 20 - ns VDD=75V,VGS=10V,ID=56A, RG,ext=1.6Ω Fall time tf - 4 - ns VDD=75V,VGS=10V,ID=56A, RG,ext=1.6Ω Unit Note/TestCondition Min. Typ. Max. Ciss - 3600 Output capacitance Coss - Reverse transfer capacitance1) Crss Turn-on delay time Input capacitance1) 1) Table6Gatechargecharacteristics2) Parameter Symbol Values Min. Typ. Max. Qgs - 21 - nC VDD=75V,ID=56A,VGS=0to10V Gate to drain charge Qgd - 10 15 nC VDD=75V,ID=56A,VGS=0to10V Switching charge Qsw - 17 - nC VDD=75V,ID=56A,VGS=0to10V Gate charge total Qg - 49 61 nC VDD=75V,ID=56A,VGS=0to10V Gate plateau voltage Vplateau - 5.7 - V VDD=75V,ID=56A,VGS=0to10V Qoss - 136 181 nC VDD=75V,VGS=0V Unit Note/TestCondition Gate to source charge 1) 1) 1) Output charge Table7Reversediode Parameter Symbol Diode continous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) 2) Values Min. Typ. Max. IS - - 112 A TC=25°C IS,pulse - - 448 A TC=25°C VSD - 0.89 1.1 V VGS=0V,IF=56A,Tj=25°C trr - 69 138 ns VR=75V,IF=56A,diF/dt=100A/µs Qrr - 96 192 nC VR=75V,IF=56A,diF/dt=100A/µs Defined by design. Not subject to production test. See ″Gate charge waveforms″ for parameter definition Final Data Sheet 4 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 4Electricalcharacteristicsdiagrams Diagram2:Draincurrent 240 120 200 100 160 80 ID[A] Ptot[W] Diagram1:Powerdissipation 120 60 80 40 40 20 0 0 50 100 150 0 200 0 50 100 TC[°C] 150 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 100 10 1 µs 10 µs 100 µs 0.5 1 ms 0.2 ZthJC[K/W] ID[A] 102 101 10 ms 10-1 0.1 0.05 DC 0.02 0 10 0.01 single pulse 10-1 10-1 100 101 102 103 10-2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 5 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 400 12 5.5 V 10 V 350 8V 6V 10 7V 300 8V 8 RDS(on)[mΩ] 250 ID[A] 7V 200 150 10 V 6 4 100 6V 2 50 5.5 V 0 5V 0 1 2 3 4 0 5 0 50 100 VDS[V] 150 200 250 300 350 400 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 250 160 140 200 120 100 ID[A] gfs[S] 150 100 80 60 40 50 175 °C 0 0 2 4 20 25 °C 6 8 0 0 VGS[V] 80 120 160 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 gfs=f(ID);Tj=25°C 6 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 20 5.0 4.5 4.0 1600 µA 15 160 µA 3.0 10 VGS(th)[V] RDS(on)[mΩ] 3.5 max typ 2.5 2.0 1.5 5 1.0 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=56A;VGS=10V VGS(th)=f(Tj);VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 175 °C 25°C max 175°C max Ciss 103 102 IF[A] C[pF] Coss 102 Crss 101 101 100 0 20 40 60 80 100 120 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 7 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 3 10 10 75 V 8 30 V 120 V 2 10 6 VGS[V] IAS[A] 25 °C 100 °C 125 °C 4 1 10 2 100 100 101 102 103 0 0 tAV[µs] 20 40 60 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=56Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Gate charge waveforms 165 160 VBR(DSS)[V] 155 150 145 140 135 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 8 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 5PackageOutlines Figure1OutlinePG-TO220-3,dimensionsinmm/inches Final Data Sheet 9 Rev.2.0,2016-03-03 OptiMOSª5Power-Transistor,150V IPP076N15N5 RevisionHistory IPP076N15N5 Revision:2016-03-03,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2016-03-03 Release of final version TrademarksofInfineonTechnologiesAG AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™, EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™, ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™, PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™, SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™. TrademarksupdatedAugust2015 OtherTrademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2016InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 10 Rev.2.0,2016-03-03