IR1167(A,B)S
SMARTRECTIFIERTM CONTROL IC
Product Summary
Features
Secondary side high speed SR controller
DCM, CrCM and CCM flyback topologies
200 V proprietary IC technology
Max 500 KHz switching frequency
Anti-bounce logic and UVLO protection
7 A peak turn off drive current
Micropower start-up & ultra low quiescent current
10.7 / 14.5 V gate drive clamp
50ns turn-off propagation delay
Vcc range from 11.3 V to 20 V
Direct sensing of MOSFET drain voltage
Minimal component count
Simple design
Lead-free
Compatible with 1 W Standby, Energy Star, CECP, etc.
Topology
Flyback
VD
200 V
VOUT
IR1167A
10.7 V
IR1167B
14.5 V
Io+ & I o- (typ.)
+2 A / -7 A
Turn on Propagation
Delay (typ.)
60 ns
Turn off Propagation
Delay (typ.)
40 ns
Package Options
Typical Applications
LCD & PDP TV, Telecom SMPS,
adapters, ATX SMPS, Server SMPS
AC-DC
8-Lead SOIC
Ordering Information
Standard Pack
Base Part Number
Package Type
IR1167AS
SOIC8N
IR1167BS
1
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Complete Part Number
Form
Quantity
Tape and Reel
2500
IR1167ASTRPBF
Tape and Reel
2500
IR1167BSTRPBF
© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Typical Connection Diagram
Vin
Rs
Rdc
XFM
Cdc
U1
1
Ci
2
3
RMOT
4
VCC
VGATE
OVT
GND
MOT
VS
EN
VD
IR1167(A,B)S
IR11671
Rtn
2
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8
LOAD
Cs
7
6
Co
5
Rg
Q1
© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Table of Contents
Page
Ordering Information
1
Description
4
Absolute Maximum Ratings
5
Electrical Characteristics
6
Functional Block Diagram
8
Lead Definitions
9
Lead Assignments
9
Detailed Pin Description
10
Application Information and Additional Details
11
Package Details
22
Tape and Reel Details
23
Part Marking Information
24
Qualification Information
25
3
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Description
IR1167S is a smart secondary side driver IC designed to drive N-Channel power MOSFETs used as synchronous
rectifiers in isolated Flyback converters. The IC can control one or more paralleled N-MOSFETs to emulate the
behavior of Schottky diode rectifiers. The drain to source voltage is sensed differentially to determine the polarity of
the current and turn the power switch on and off in proximity of the zero current transition. Ruggedness and noise
immunity are accomplished using an advanced blanking scheme and double-pulse suppression which allow
reliable operation in continuous, discontinuous and critical current mode operation and both fixed and variable
frequency modes.
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Absolute Maximum Ratings
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions are not implied. All
voltages are absolute voltages referenced to GND. Thermal resistance and power dissipation are measured under
board mounted and still air conditions.
Parameters
Symbol
Supply Voltage
VCC
VEN
Enable Voltage
Cont. Drain Sense Voltage
VD
Pulse Drain Sense Voltage
VD
Source Sense Voltage
VS
Gate Voltage
VGATE
Operating Junction Temperature
TJ
Storage Temperature
TS
Thermal Resistance
RθJA
Package Power Dissipation
PD
ESD Protection
VESD
Switching Frequency
fsw
†
Per EIA/JESD22-A114-B (discharging a 100pF
5
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Min.
-0.3
-0.3
-3
-5
-3
-0.3
-40
-55
Max.
Units
20
20
200
V
200
20
20
150
°C
150
128
°C/W
970
mW
2
kV
500
kHz
capacitor through a 1.5kΩ series
© 2013 International Rectifier
Remarks
VCC=20V, Gate off
SOIC-8
SOIC-8, TAMB=25°C
Human Body Model
†
resistor).
Nov 6, 2013
IR1167(A,B)S
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range T J from – 25° C to 125°C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Supply Section
Parameters
Supply Voltage Operating
Range
VCC Turn On Threshold
VCC Turn Off Threshold
(Under Voltage Lock Out)
VCC Turn On/Off Hysteresis
Symbol
Min.
Typ.
VCC
12
VCC ON
9.8
10.5
11.3
VCC UVLO
8.4
9
9.7
VCC HYST
1.4
1.55
8.5
50
10.3
66
1.8
100
150
2.75
1.6
1.5
1.7
10
65
12
80
2.2
200
200
3.2
2
Typ.
-3.5
-10.5
-19
Max.
0
-7
-15
-50
ICC
IR1167B
Quiescent Current
Start-up Current
Sleep Current
Enable Voltage High
Enable Voltage Low
Enable Pull-up Resistance
Comparator Section
Parameters
IQCC
ICC START
ISLEEP
VENHI
VENLO
REN
Symbol
2.15
1.2
Min.
-7
-15
-23
-150
Turn-off Threshold
VTH1
Turn-on Threshold
Hysteresis
VTH2
VHYST
IIBIAS1
IIBIAS2
VOFFSET
VCM
-0.15
Symbol
tBLANK
Min.
9
Input Bias Current
Comparator Input Offset
Input CM Voltage Range
One-Shot Section
Parameters
Blanking pulse duration
Reset Threshold
Hysteresis
6
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VTH3
VHYST3
55
1
30
Typ.
15
2.5
5.4
40
© 2013 International Rectifier
Remarks
Units
18
IR1167A
Operating Current
Max.
GBD
V
mA
µA
CLOAD=1nF, fsw=400kHz
CLOAD=10nF, fsw=400kHz
CLOAD=1nF, fsw=400kHz
CLOAD=10nF, fsw=400kHz
VCC=VCC ON - 0.1V
VEN=0V, VCC =15V
V
MΩ
Units
mV
7.5
100
2
2
mV
V
Max.
25
Units
µs
µA
V
mV
GBD
Remarks
OVT = 0V, VS=0V
OVT floating, VS=0V
OVT = VCC, VS=0V
VD = -50mV
V D = 200V
GBD
Remarks
VCC=10V - GBD
VCC=20V - GBD
VCC=10V - GBD
Nov 6, 2013
IR1167(A,B)S
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and
junction temperature range T J from – 25° C to 125°C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Minimum On Time Section
Parameters
Symbol
Minimum on time
TONmin
Gate Driver Section
Parameters
Gate Low Voltage
IR1167A
Gate High Voltage
IR1167B
Fall Time
Turn on Propagation Delay
Turn off Propagation Delay
Pull up Resistance
Pull down Resistance
Output Peak Current (source)
Output Peak Current (sink)
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VGTH
tr1
tr2
tf1
tf2
Rise Time
7
Symbol
VGLO
tDon
tDoff
rup
rdown
IO source
IO sink
Min.
190
Typ.
240
Max.
290
Units
ns
Remarks
RMOT =5kVCC=12V
2.4
3
3.6
µs
RMOT =75kVCC=12V
Min.
Typ.
0.3
10.7
14.5
18
125
10
30
60
40
4
0.7
2
7
Max.
0.5
12.5
16.5
Units
9
12
© 2013 International Rectifier
V
ns
80
65
Ω
A
Remarks
IGATE = 200mA
VCC=12V-18V (internally clamped)
VCC=12V-18V (internally clamped)
CLOAD = 1nF, VCC=12V
CLOAD = 10nF, VCC=12V
CLOAD = 1nF, VCC=12V
CLOAD = 10nF, VCC=12V
VDS to VGATE -100mV overdrive
VDS to VGATE -100mV overdrive
IGATE = 1A - GBD
IGATE = -200mA
CLOAD = 10nF - GBD
Nov 6, 2013
IR1167(A,B)S
Functional Block Diagram
MOT
VCC
VCC
UVLO
&
REGULATOR
ENA
VCC
VD
Min ON Time
VTH1
RESET
VS
VGATE
DRIVER
COM
OVT
Min OFF Time
Vgate
RESET
VTH3
VTH2
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VTH1
VTH3
VDS
Nov 6, 2013
IR1167(A,B)S
Lead Definitions
PIN#
1
2
3
4
5
6
7
8
Symbol
VCC
OVT
MOT
EN
VD
VS
GND
GATE
Description
Supply Voltage
Offset Voltage Trimming
Minimum On Time
Enable
FET Drain Sensing
FET Source Sensing
Ground
Gate Drive Output
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1
VCC
2
OVT
3
MOT
4
EN
© 2013 International Rectifier
IR1167S
Lead Assignments
VGATE
8
GND
7
VS
6
VD
5
Nov 6, 2013
IR1167(A,B)S
Detailed Pin Description
VCC: Power Supply
This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to turn off the IC by
pulling this pin below the minimum turn off threshold voltage, without damage to the IC.
To prevent noise problems, a bypass ceramic capacitor connected to Vcc and GND should be placed as close as possible to
the IR1167S. This pin is internally clamped.
OVT: Offset Voltage Trimming
The OVT pin will program the amount of input offset voltage for the turn-off threshold VTH1.
The pin can be optionally tied to ground, to VCC or left floating, to select 3 ranges of input offset trimming.
This programming feature allows for accommodating different R DSon MOSFETs.
MOT: Minimum On Time
The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed for the first time, the gate signal will
become active and turn on the power FET. Spurious ringings and oscillations can trigger the input comparator off. The MOT
blanks the input comparator keeping the FET on for a minimum time.
The MOT is programmed between 200ns and 3us (typ.) by using a resistor referenced to GND.
EN: Enable
This pin is used to activate the IC “sleep” mode by pulling the voltage level below 2.5V (typ). In sleep mode the IC will
consume a minimum amount of current. However all switching functions will be disabled and the gate will be inactive. The EN
pin voltage cannot linger between the Enable low and Enable high thresholds. The pin is intended to operate as a switch with
the pin voltage either above or below the threshold range. The Enable control pin (EN) is not intended to operate at high
frequency. For proper operation, EN positive pulse width needs to be longer than 20µs, EN negative pulse width needs to be
longer than 10µs.
Please refer to Figure 22B for the definition of EN pulse width.
VD: Drain Voltage Sense
VD is the voltage sense pin for the power MOSFET Drain. This is a high voltage pin and particular care must be taken in
properly routing the connection to the power MOSFET drain.
Additional filtering and or current limiting on this pin is not recommended as it would limit switching performance of the IC.
VS: Source Voltage Sense
VS is the differential sense pin for the power MOSFET Source. This pin must not be connected directly to the power ground
pin (7) but must be used to create a Kelvin contact as close as possible to the power MOSFET source pin.
GND: Ground
This is ground potential pin of the integrated control circuit. The internal devices and gate driver are referenced to this point.
GATE: Gate Drive Output
This is the gate drive output of the IC. Drive voltage is internally limited and provides 2A peak source and 7A peak sink
capability. Although this pin can be directly connected to the power MOSFET gate, the use of minimal gate resistor is
recommended, especially when putting multiple FETs in parallel.
Care must be taken in order to keep the gate loop as short and as small as possible in order to achieve optimal switching
performance.
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Application Information and Additional Details
State Diagram
UVLO/Sleep Mode
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold voltage, V CC
ON. During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC draws a quiescent
current of ICC START. The UVLO mode is accessible from any other state of operation whenever the IC supply voltage
condition of VCC < VCC UVLO occurs.
The sleep mode is initiated by pulling the EN pin below 2.5V (typ). In this mode the IC is essentially shut down and
draws a very low quiescent supply current.
Normal Mode
The IC enters in normal operating mode once the UVLO voltage has been exceeded. At this point the gate driver is
operating and the IC will draw a maximum of I CC from the supply voltage source.
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
General Description
The IR1167 Smart Rectifier IC can emulate the operation of diode rectifier by properly driving a Synchronous Rectifier (SR)
MOSFET. The direction of the rectified current is sensed by the input comparator using the power MOSFET R DSon as a shunt
resistance and the GATE pin of the MOSFET is driven accordingly. Internal blanking logic is used to prevent spurious
transitions and guarantee operation in continuous (CCM), discountinuous (DCM) and critical (CrCM) conduction mode.
VGate
VDS
VTH2
VTH1
VTH3
Figure 1: Input comparator thresholds
Flyback Application
The modes of operation for a Flyback circuit differ mainly for the turn-off phase of the SR switch, while the turn-on phase of the
secondary switch (which corresponds to the turn off of the primary side switch) is identical.
Turn-on phase
When the conduction phase of the SR FET is initiated, current will start flowing through its body diode, generating a negative
VDS voltage across it. The body diode has generally a much higher voltage drop than the one caused by the MOSFET on
resistance and therefore will trigger the turn-on threshold VTH2.
At that point the IR1167 will drive the gate of MOSFET on which will in turn cause the conduction voltage V DS to drop down.
This drop is usually accompanied by some amount of ringing, that can trigger the input comparator to turn off; hence, a
Minimum On Time (MOT) blanking period is used that will maintain the power MOSFET on for a minimum amount of time.
The programmed MOT will limit also the minimum duty cycle of the SR MOSFET and, as a consequence, the max duty cycle
of the primary side switch.
DCM/CrCM Turn-off phase
Once the SR MOSFET has been turned on, it will remain on until the rectified current will decay to the level where V DS will
cross the turn-off threshold VTH1. This will happen differently depending on the mode of operation.
In DCM the current will cross the threshold with a relatively low dI/dt. Once the threshold is crossed, the current will start
flowing again through the body diode, causing the VDS voltage to jump negative. Depending on the amount of residual current,
VDS may trigger once again the turn on threshold: for this reason VTH2 is blanked for a certain amount of time (TBLANK) after
VTH1 has been triggered.
The blanking time is internally set. As soon as V DS crosses the positive threshold VTH3 also the blanking time is terminated and
the IC is ready for next conduction cycle.
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Nov 6, 2013
IR1167(A,B)S
IPRIM
VPRIM
T1
T3
T2
time
ISEC
VSEC
time
Figure 2: Primary and secondary currents and voltages for DCM mode
IPRIM
VPRIM
T1
T2
time
ISEC
VSEC
time
Figure 3: Primary and secondary currents and voltages for CrCM mode
CCM Turn-off phase
In CCM mode the turn off transition is much steeper and dI/dt involved is much higher. The turn on phase is identical to DCM
or CrCM and therefore won’t be repeated here.
During the SR FET conduction phase the current will decay linearly, and so will VDS on the SR FET.
Once the primary switch will start to turn back on, the SR FET current will rapidly decrease crossing V TH1 and turning the gate
off. The turn off speed is critical to avoid cross conduction on the primary side and reduce switching losses.
Also in this case a blanking period will be applied, but given the very fast nature of this transition, it will be reset as soon as
VDS crosses VTH3.
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Nov 6, 2013
IR1167(A,B)S
IPRIM
VPRIM
T1
time
T2
ISEC
VSEC
time
Figure 4: Primary and secondary currents and voltages for CCM mode
VTH3
ISEC
VDS
T1
T2
time
VTH1
VTH2
Gate Drive
time
Blanking
MOT
time
Figure 5: Secondary side CCM operation
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Nov 6, 2013
IR1167(A,B)S
VTH3
ISEC
VDS
T1
T2
time
VTH1
VTH2
Gate Drive
time
Blanking
MOT
10us blanking
Figure 6: Secondary side DCM/CrCM operation
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Nov 6, 2013
IR1167(A,B)S
Figure 7: Supply Current vs. Supply Voltage
Figure 9: VTH1 vs. Temperature
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© 2013 International Rectifier
Figure 8: Undervoltage Lockout vs. Temperature
Figure 10: VTH2 vs. Tempature
Nov 6, 2013
IR1167(A,B)S
Figure 11: Comparator Hysteresis vs. Temperature
Figure 12: VTH1 vs. Temperature and Common Mode
(OVT = GND)
Figure 13: VTH2 vs. Temperature and Common Mode
(OVT = GND)
Figure 14: Comparator Hysteresis vs. Temperature and
Common Mode (OVT = GND)
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Figure 15: MOT vs. Temperature
Figure 17: Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ = 125˚C, TIC = 85˚C, external RG =
1Ω, 1Ω HEXFET Gate Resistance Included
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© 2013 International Rectifier
Figure 16: Input Bias Current vs. VD
Figure 18: Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ = 125˚C, TIC = 85˚C, external RG =
2Ω, 1Ω HEXFET Gate Resistance Included
Nov 6, 2013
IR1167(A,B)S
Figure 19: Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ = 125˚C, TIC = 85˚C, external RG =
4Ω, 1Ω HEXFET Gate Resistance Included
Figure 20: Max. VCC Voltage vs. Synchronous Rectifier
Switching Freq, TJ = 125˚C, TIC = 85˚C, external RG =
6Ω, 1Ω HEXFET Gate Resistance Included
Figures 17 – 20 show the maximum allowable VCC voltage vs. maximum switching frequency for different loads which
are calculated using the design methodology discussed in AN1087
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Nov 6, 2013
IR1167(A,B)S
Figure 21: VCC Under Voltage Lockout
Figure 22A: Timing Diagram
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Nov 6, 2013
IR1167(A,B)S
VEN
VENHI
VENLO
EN positive pulse width
EN negative
pulse width
Figure 22B: Enable Timing Waveform
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Package Details: SOIC8N
22
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© 2013 International Rectifier
Nov 6, 2013
IR1167(A,B)S
Tape and Reel Details: SOIC8N
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
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© 2013 International Rectifier
Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
Nov 6, 2013
IR1167(A,B)S
Part Marking Information
IR1167(A,B)
Part number
YWW ?
Date code
Pin 1
Identifier
C XXXX
?
MARKING CODE
P
Lead Free Released
Non-Lead Free Released
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IR logo
© 2013 International Rectifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
Nov 6, 2013
IR1167(A,B)S
Qualification Information†
††
Industrial
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
†††
MSL2 260°C
(per IPC/JEDEC J-STD-020)
Yes
Qualification Level
Moisture Sensitivity Level
RoHS Compliant
†
††
†††
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
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Nov 6, 2013
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