IR2010PBF

IR2010(S)PBF High and Low Side Driver Features              Product Summary Floating channel designed for bootstrap operation Fully operational to 200V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground +/-5V offset CMOS Schmitt-triggered inputs with pull-down Shut down input turns off both channels Cross-conduction prevention logic Matched propagation delay for both channels Outputs in phase with inputs Description VOFFSET (max) 200V IO+/- (typ) 3.0A / 3.0A VOUT 10 – 20V ton/off (typ) 95ns & 65ns Delay Matching (max) 15ns Package Options The IR2010 is a high power, high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an Nchannel power MOSFET or IGBT in the high side configuration which operates up to 200 volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. 14-Lead PDIP 16-Lead SOIC Wide Body Applications   Converters DC motor drive Ordering Information Standard Pack Base Part Number Package Type IR2010PBF IR2010SPBF IR2010SPBF PDIP14 SO16W SO16W 1 www.irf.com © 2015 International Rectifier Form Tube Tube Tape and Reel Quantity 25 45 1000 Orderable Part Number IR2010PBF IR2010SPBF IR2010STRPBF April 14, 2015 IR2010(S)PBF Typical Connection Diagram 200V HO VDD VDD VB HIN HIN VS SD SD LIN LIN VCC VSS VSS COM To Load LO VCC (Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes and Design Tips for proper circuit board layout 2 www.irf.com © 2015 International Rectifier April 14, 2015 IR2010(S)PBF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RthJA TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN & SD) Allowable offset supply voltage transient (figure 2) 14-Lead PDIP Package power dissipation @ TA ≤ +25°C 16-Lead SOIC 14-Lead PDIP Thermal resistance, junction to ambient 16-Lead SOIC Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 — — — — — — -55 — Max. 225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 150 150 300 Units V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating is tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 24 and 25. Symbol VB VS VHO VCC VLO VDD VSS VIN TA Definition High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN, & SD) Ambient temperature Min. Max. Units VS + 10 VS VS + 20 200 VB V 10 0 VSS + 3 -5†† VSS -40 20 VCC VSS + 20 5 VDD 125 °C † † Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS. †† When VDD < 5V, the minimum VSS offset is limited to -VDD (Please refer to the Design Tip DT97-3 for more details). 3 www.irf.com © 2015 International Rectifier April 14, 2015 IR2010(S)PBF Dynamic Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, CL = 1000pF and TA = 25°C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in figure 3. Symbol ton toff tsd tr tf MT Definition Figure Min. Typ. Max. 7 8 9 10 11 6 50 30 35 — — — 95 65 70 10 15 — 135 105 105 20 25 15 Turn-on propagation delay Turn-off propagation delay Shutdown propagation delay Turn-on rise time Turn-off fall time Delay matching, HS & LS turn-on/off Units Test Conditions VS = 0V VS = 200V ns Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V and TA = 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH VIL VIH VIL VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- 4 Definition Logic “1” input voltage Logic “0” input voltage Logic “1” input voltage Logic “0” input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Quiescent VDD supply current Logic “1” input bias current Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current www.irf.com Figure 12 13 12 13 14 15 16 17 18 19 20 21 Min. 9.5 — 2 — — — — — — — — — Typ. — — — — — — — 70 100 1 20 — Max. — 6.0 — 1 1.0 0.1 50 210 230 5 40 1.0 22 7.5 8.6 9.7 23 7.0 8.2 9.4 © 2015 International Rectifier Units Test Conditions VDD = 15V V VDD = 3.3V IO = 0A VB = VS = 200V μA VIN = 0V or VDD VIN = VDD VIN = 0V V 24 7.5 8.6 9.7 25 7.0 8.2 9.4 26 2.5 3.0 — 27 2.5 3.0 — A VO = 0V, VIN = VDD PW ≤ 10 μs VO = 15V, VIN = 0V PW ≤ 10 μs April 14, 2015 IR2010(S)PBF Functional Block Diagram 5 www.irf.com © 2015 International Rectifier April 14, 2015 IR2010(S)PBF Lead Definitions Symbol Description VDD HIN SD LIN VSS VB HO VS VCC LO COM Logic Supply Logic input for high side gate driver outputs (HO), in phase Logic input for shutdown Logic input for low side gate driver outputs (LO), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 14-Lead PDIP 6 www.irf.com © 2015 International Rectifier 16-Lead SOIC (Wide Body) April 14, 2015 IR2010(S)PBF Application Information and Additional Details HV = 10 to 200V VCC = 15V 0.1µF + 100µF 200µH 10KF6 10µF HIN LIN 10KF6 0.1µF VDD VCC VB VS 10KF6 SD HIN HO LO HO dVS