IR2213STRPBF

IR2213(S)PBF High and Low Side Driver Features              Product Summary Floating channel designed for bootstrap operation Fully operational to +1200 V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 12 V to 20 V Undervoltage lockout for both channels 3.3 V logic compatible Separate logic supply range from 3.3 V to 20 V Logic and power ground ±5 V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs VOFFSET (max) 1200 V IO+/- 1.7 A / 2 A VOUT 12 V – 20 V ton/off (typical) 280 ns / 225 ns Delay Matching 30 ns Description Package Options The IR2213(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 1200 V. 16 Lead SOIC (Wide Body) 14 Lead PDIP Ordering Information Standard Pack Base Part Number Package Type Form Quantity IR2213SPBF SO16WB Tube 45 IR2213SPBF SO16WB Tape and Reel 1000 IR2213PBF PDIP14 Tube 25 1 www.irf.com © 2016 International Rectifier Orderable Part Number IR2213SPBF IR2213STRPBF IR2213PBF April 26, 2016 IR2213(S)PBF Typical Connection Diagram Refer to Lead Assignments for correct pin configuration. This/These diagram(s) show electrical connections only. Please refer to our Application Notes and Design Tips for proper circuit board layout 2 www.irf.com © 2016 International Rectifier April 26, 2016 IR2213(S)PBF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA Definition High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation (14 Lead PIDP) @ T A ≤ +25˚C (16 Lead SOIC) @ T +25°C (14 ≥ A (14Lead LeadPDIP) PDIP) Thermal Resistance, Junction to Ambient (14 (16Lead LeadPDIP) SOIC) Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) TJ TS TL Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 — — — — — — -55 — Max. 1225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.3 1.0 75 100 125 150 300 Units V V/ns W °C/W °C Recommended Operating Conditions The Input / Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential. Symbol VB VS VHO VCC VLO VDD VSS VIN † †† Definition High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Min. VS + 12 † VS 12 0 VSS + 3 †† -5 VSS Max. VS + 20 1200 VB 20 VCC VSS + 20 5 VDD Units V Logic operational for VS of -5 to +1200V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT973 for more details). When VDD