IR3447MTRPBF

DCDC Converter 25A Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES SupIRBuck IR3447 DESCRIPTION  Single 5V to 21V application  Wide Input Voltage Range from 1.5V to 21V with external Vcc  Output Voltage Range: 0.6V to 0.86*PVin  0.5% accurate Reference Voltage  Enhanced line/load regulation with Feed-Forward  Programmable Switching Frequency up to 1.5MHz  Internal Digital Soft-Start  Enable input with Voltage Monitoring Capability  Remote Sense Amplifier with True Differential Voltage Sensing  Thermally compensated current limit and Hiccup Mode Over Current Protection  Smart LDO to enhance efficiency  External synchronization with Smooth Clocking  Dedicated output voltage sensing for power good indication and overvoltage protection which remains active even when Enable is low.  Enhanced Pre-Bias Start up  Body Braking to improve transient  Integrated MOSFET drivers and Bootstrap diode  Thermal Shut Down  Post Package trimmed rising edge dead-time  Programmable Power Good Output  Small Size 5mm x 6mm PQFN  Operating Junction Temp: -40oC 1.2V EN Voltage [Time] Intl_SS Vo Figure 6: Pre-Bias startup Figure 5: Recommended startup for Normal operation Figure 5 shows the recommended startup sequence for the typical operation of IR3447 with Enable used as logic input. ... HDRv 12.5% ... LDRv 16 ... ... 25% ... ... 87.5% ... ... 16 ... End of PB ... PRE-BIAS STARTUP Pre-bias can restrict the V_boot voltage and prevent the IC from starting up properly. Knowing the Vboot requirement, Vcc voltage (Vcc) and forward diode (Vd) voltage the maximum pre-bias can be determined. The power stage driver requires a minimum of 3V Vboot during startup which translates to a maximum pre-bias voltage of (Vcc – Vd – Vboot)V. Pre-Bias voltage Limit Vcc Vd Vboot < Vcc – Vd – Vboot (1) Supply Rail (Internal LDO / External Supply) Bootstrap diode forward voltage. [0.8V] Required Vboot voltage at start up. [3V] Figure 7: Pre-Bias startup pulses SOFT-START IR3447 has an internal digital soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and VCC rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft-start (Intl_SS) signal linearly rises with the rate of 0.4mV/µs from 0V to 1.5V. Figure 8 shows the waveforms during soft start. The normal Vout startup time is fixed, and is equal to: Tstart  IR3447 implements asynchronous switching during startup to help prevent oscillation and output disturbance when starting up with a pre-biased output. The regulator starts in an asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 6 shows a typical Pre-Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 7 shows the series of 16x8 startup pulses. 19 Rev 3.10 0.75V  0.15V   1.5mS 0.4mV / S (2) During the soft start the over-current protection (OCP) and over-voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. November 14, 2018 IR3447 OVER CURRENT PROTECTION POR 3.0V 1.5V 0.75V Intl_SS 0.15V Vout t1 t2 t3 Figure 8: Theoretical operation waveforms during soft-start OPERATING FREQUENCY The switching frequency can be programmed between 300kHz – 1500kHz by connecting an external resistor from Rt pin to LGnd. Table 1 tabulates the oscillator frequency versus Rt. Table 1: Switching Frequency(Fs) vs. External Resistor(Rt) Rt (KΩ) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 21 19.1 17.4 16.2 15 Freq (KHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 SHUTDOWN The Over Current (OC) protection is performed by sensing the inductor current through the RDS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The Over Current (OC) limit can be set to one of three possible settings by floating the OCset pin, by pulling up the OCset pin to VCC, or pulling down the OCset pin to PGnd. The current limit scheme in the IR3447 uses an internal temperature compensated current source to achieve an almost constant OC limit over temperature. Over Current Protection circuit senses the inductor current flowing through the Synchronous MOSFET. To help minimize false tripping due to noise and transients, inductor current is sampled for about 30 nS on the downward inductor current slope approximately 12.5% of the switching period before the inductor current valley. However, if the Synchronous MOSFET is on for less than 12.5% of the switching period, the current is sampled approximately 40nS after the start of the downward slope of the inductor current. When the sampled current is higher than the OC Limit, an OC event is detected. When an Over Current event is detected, the converter enters hiccup mode. Hiccup mode is performed by latching the OC signal and pulling the Intl_SS signal to ground for 20.48 mS (typ.). OC signal clears after the completion of hiccup mode and the converter attempts to return to the nominal output voltage using a soft start sequence. The converter will repeat hiccup mode and attempt to recover until the overload or short circuit condition is removed. Because the IR3447 uses valley current sensing, the actual DC output current limit will be greater than OC limit. The DC output current is approximately half of peak to peak inductor ripple current above selected OC limit. OC Limit, inductor value, input voltage, output voltage and switching frequency are used to calculate the DC output current limit for the converter. Equation (2) to determine the approximate DC output current limit. IR3447 can be shutdown by pulling the Enable pin below its 1.0V threshold. During shutdown the high side and the low side drivers are turned off. I OCP  I LIMIT  IOCP 20 Rev 3.10 i 2 (3) = DC current limit hiccup point November 14, 2018 IR3447 Current Limit Hiccup Tblk_Hiccup 20.48 mS* IL 0 HDrv ... 0 LDrv ... 0 PGD *typical filter delay 0 Figure 9: Timing Diagram for Current Limit Hiccup THERMAL SHUTDOWN Temperature sensing is provided inside IR3447. The trip threshold is typically 145oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20oC hysteresis in the thermal shutdown threshold. REMOTE VOLTAGE SENSING True differential remote sensing in the feedback loop is critical to high current applications where the output voltage across the load may differ from the output voltage measured locally across an output capacitor at the output inductor, and to applications that require die voltage sensing. The RS+ and RS- pins of the IR3447 form the inputs to a remote sense differential amplifier (RSA) with high speed, low input offset and low input bias current which ensure accurate voltage sensing and fast transient response in such applications. The input range for the differential amplifier is limited to 1.5V below the VCC rail. Note that IR3447 incorporates a smart LDO which switches the VCC rail voltage depending on the loading. When determining the input range assume the part is in light load and using the lower VCC rail voltage. 21 Rev 3.10 There are two remote sense configurations that are usually implemented. Figure 10 shows a general remote sense (RS) configuration. This configuration allows the RSA to monitor output voltages above VCC. A resistor divider is placed in between the output and the RSA to provide a lower input voltage to the RSA inputs. Typically, the resistor divider is calculated to provide VREF (0.6V) across the RSA inputs which is then outputted to RSo. The input impedance of the RSA is 63 KOhms typically and should be accounted for when determining values for the resistor divider. To account for the input impedance, assume a 63 KOhm resistor in parallel to the lower resistor in the divider network. The compensation is then designed for 0.6V to match the RSo value. Low voltage applications can use the second remote sense configuration. When the output voltage range is within the RSA input specifications, no resistor divider is needed in between the converter output and RSA. The second configuration is shown in Figure 11. The RSA is used as a unity gain buffer and compensation is determined normally. Resistor Divider RS+ + Vout (< VCC-1.5V) - RSo Compensation = Current Limit Valley Point = Inductor ripple current RSA RS- + FB - Figure 10: General Remote Sense Configuration + Vout (< VCC-1.5V) - RS+ RSo Vo RSA RS- Compensation ILIMIT Δi + FB - Figure 11: Remote Sense Configuration for Vout less than VCC-1.5V EXTERNAL SYNCHRONIZATION November 14, 2018 IR3447 IR3447 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (POL) regulators are used. A multifunction pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock signal solely and no other resistor is needed. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free-running frequency, an external resistor from Rt/Sync pin to LGnd is required to set the free-running frequency. When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its free-running frequency, a transition from the free-running frequency to the external clock frequency will happen. This transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. When the external clock signal is removed from Rt/Sync pin, the switching frequency is also changed to free-running gradually. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin. Figure 12 shows the timing diagram of these transitions. An internal circuit is used to change the PWM ramp slope according to the clock frequency applied on Rt/Sync pin. Even though the frequency of the external synchronization clock can vary in a wide range, the PLL circuit keeps the ramp amplitude constant, requiring no adjustment of the loop compensation. PVin variation also affects the ramp amplitude, which will be discussed separately in FeedForward section. Synchronize to the external clock Free Running Frequency Return to freerunning freq ... SW Gradually change Gradually change ... Fs1 SYNC Fs1 Fs2 Figure 12: Timing Diagram for Synchronization to the external clock (Fs1>Fs2 or Fs1