IR3502A
DATA SHEET
XPHASE3TM CONTROL IC
DESCRIPTION
The IR3502A control IC combined with an XPHASE3TM Phase IC provides a full featured and flexible way
to implement a complete VR11.0 and VR11.1 power solution. The IR3502A provides overall system control
and interfaces with any number of Phase ICs, each driving and monitoring a single phase. The XPhase3TM
architecture results in a power supply that is smaller, less expensive, and easier to design while providing
higher efficiency than conventional approaches.
FEATURES
1 to X phase operation with matching Phase IC
0.5% overall system set point accuracy
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Programmable 250kHz to 9MHz clock oscillator frequency provides per phase switching frequency of
250kHz to 1.5MHz
Programmable Dynamic VID Slew Rate
Programmable VID Offset or No Offset
Programmable Load Line Output Impedance
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 10V/us
Programmable constant converter output current limit during soft start
Hiccup over current protection with delay during normal operation
Central over voltage detection and latch with programmable threshold and communication to phase ICs
Over voltage signal output to system with overvoltage detection during powerup and normal operation
Load current reporting
Single NTC thermistor compensation for correct current reporting, OC Threshold, and Droop
Detection and protection of open remote sense line
Open control loop protection
IC bias linear regulator controller
Programmable VRHOT function monitors temperature of power stage through a NTC thermistor
Remote sense amplifier with true converter voltage sensing
Small thermally enhanced 32L 5mm x 5mm MLPQ package
RoHS Compliant
ORDERING INFORMATION
Device
IR3502AMTRPBF
* IR3502AMPBF
Package
32 Lead MLPQ
(5 x 5 mm body)
32 Lead MLPQ
(5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Samples only
Page 1 of 38
December 17, 2009
IR3502A
APPLICATION CIRCUIT
12V
+12V
Q2
VCCL
CVCCL
RVCCLDRV
IIN
PHSIN
PGOOD
PHSOUT
RMON
CLKOUT
25
CLKOUT
26
PHSOUT
28
29
30
27
PHSIN
VCCL
IIN
IMON
IR3502A
VID3
23
VDAC_BUFF
VDRP
CSS/DEL
21
RVDAC
20
RVSETPT
19
RTCMP3
CVDAC
VDAC
18
17
RTCMP1
RTHERM
RTCMP2
16
15
VO
14
9
ENABLE
EAOUT
VN
VID0
FB
VID1
ROSC
22
VSETPT
VID2
VOSEN+
8
VID0
VDAC
13
7
VID1
SS/DEL
VID4
VOSEN-
6
VID2
VID5
HOTSET
5
VID3
24
GND
ROSC
12
4
VID4
VID6
11
VID5
VCCLDRV
32
3
VID7
VRHOT
2
VID6
ENABLE
1
VID7
PGOOD
RMON1
VOSEN-
10
CMON
31
IOUT
RDRP
VRHOT
RHOTSET1
RHOTSET3
CHOTSET
RFB1
CFB1
EAOUT
CEA1
RFB
RHOTSET2
CEA
REA
VOSEN+
VOSEN-
Figure 1: IR3502A Application Circuit
IR3502A
ERROR
AMPLIFIER
VDAC
BUFFER
AMPLIFIER
EAOUT
1k
+
FB
+
VSETPT
ISOURCE
FAST
VDAC
VDAC
ISINK
OCSET ROCSET
-
IVDAC
IOCSET
IVSETPT
IROSC
CURRENT
SOURCE
GENERATOR
CVDAC
IROSC
ROSC BUFFER
AMPLIFIER
0.6V
LGND
+
IROSC
RVDAC
ROSC
ROSC
VO
REMOTE SENSE
AMPLIFIER
VOSEN+
EAOUT
SYSTEM
SET POINT
VOSNSVOLTAGE
+
VOSEN-
Figure 2 –System-set point measurements.
Page 2 of 38
December 17, 2009
IR3502A
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications are not implied.
Operating Junction Temperature……………..0 to 150oC
Storage Temperature Range………………….-65oC to 150oC
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
Reflow Temperature…………………………….260oC
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VID7-0
ENABLE
VRHOT
HOTSET
VOSENVOSEN+
VO
FB
EAOUT
VDRP
VN
VDAC_BUFF
VSETPT
VDAC
SS/DEL
ROSC/OVP
LGND
CLKOUT
7.5V
3.5V
7.5V
7.5V
1.0V
7.5V
7.5V
7.5V
7.5V
7.5V
7.5V
3.5V
3.5V
3.5V
7.5V
7.5V
n/a
7.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
n/a
-0.3V
1mA
1mA
1mA
1mA
5mA
5mA
35mA
1mA
35mA
35mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
100mA
1mA
1mA
50mA
1mA
1mA
1mA
5mA
1mA
5mA
1mA
1mA
35mA
1mA
1mA
1mA
1mA
1mA
100mA
26
27
28
PHSOUT
PHSIN
VCCL
7.5V
7.5V
7.5V
-0.3V
-0.3V
-0.3V
10mA
1mA
1mA
10mA
1mA
20mA
29
IIN
7.5V
-0.3V
1mA
1mA
30
VCCLDRV
10V
-0.3V
1mA
50mA
31
PGOOD
VCCL + 0.3V
-0.3V
1mA
20mA
32
IMON
3.5V
-0.3V
25mA
1mA
Page 3 of 38
December 17, 2009
IR3502A
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V ≤ VOSEN- ≤
0.3V, 0 oC ≤ TJ ≤ 100 oC, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ, CSS/DEL = 0.1F +/-10%.
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
MIN
VID ≥ 1V
0.8V ≤ VID < 1V
0.5V ≤ VID < 0.8V
Include OCSET and VSETPT currents
Source & Sink Currents
VIDx Input Threshold
VIDx Input Bias Current
0V≤V(VIDx)≤2.5V.
VIDx OFF State Blanking Delay Measure time till PGOOD drives low
Oscillator
ROSC Voltage
CLKOUT High Voltage
I(CLKOUT)= -10 mA, measure V(VCCL)
– V(CLKOUT).
CLKOUT Low Voltage
I(CLKOUT)= 10 mA
PHSOUT Frequency
ROSC = 50.0 KΩ
PHSOUT Frequency
ROSC = 24.5 KΩ
PHSOUT Frequency
ROSC = 7.75 KΩ
PHSOUT High Voltage
I(PHSOUT)= -1 mA, measure V(VCCL)
– V(PHSOUT)
PHSOUT Low Voltage
I(PHSOUT)= 1 mA
PHSIN Threshold Voltage
Compare to V(VCCL)
VDAC Buffer Amplifier
Input Offset Voltage
V(VDAC_BUFF) – V(VDAC), 0.5V ≤
V(VDAC) ≤ 1.6V, < 1mA load
Source Current
0.5V ≤ V(VDAC) ≤ 1.6V
Sink Current
0.5V ≤ V(VDAC) ≤ 1.6V
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
Thermal Compensation Amplifier
Output Offset Voltage
0V ≤ V(IIN) – V(VDAC) ≤ 1.6V, 0.5V ≤
V(VDAC) ≤ 1.6V, Req/R2 = 2
Source Current
0.5V ≤ V(VDAC) ≤ 1.6V
Sink Current
0.5V ≤ V(VDAC) ≤ 1.6V
Unity Gain Bandwidth
Note 1, Req/R2 = 2
Slew Rate
Note 1
Current Report Amplifier
Output Offset Voltage
V(VDRP)–V(VDAC) = 0,225,450,900mV
Page 4 of 38
TYP
MAX
UNIT
-0.5
-5
-8
30
500
-1
0.5
44
600
0
1.3
0.5
+5
+8
58
700
1
2.1
%
mV
mV
A
mV
A
s
0.570
0.595
0.620
1
V
V
225
450
1.35
250
500
1.50
1
275
550
1.65
1
V
kHz
kHz
MHz
V
V
%
30
50
1
70
-5
0
9
mV
0.3
3.5
0.44
13
3.5
1.5
0.6
20
mA
mA
MHz
V/s
-10
0
10
mV
3
0.3
2
8
0.4
4.5
5.5
15
0.5
7
mA
mA
MHz
52
67
37
V/s
December 17, 2009
mV
IR3502A
PARAMETER
TEST CONDITION
Source Current
0.5V ≤ V(IMON) ≤ 0.9V
Sink Resistance
0.5V ≤ V(IMON) ≤ 0.9V
Unity Gain Bandwidth
Note 1
Input Filter Time Constant
Max Output Voltage
Soft Start and Delay
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
PGOOD Delay (TD4 + TD5)
OC Delay Time
V(VDRP) – V(DACBUFF) = 1.67 mV
SS/DEL to FB Input Offset
With FB = 0V, adjust V(SS/DEL) until
Voltage
EAOUT drives high
Charge Current
Discharge Current
Charge/Discharge Current Ratio
Charge Voltage
Relative to Charge Voltage, SS/DEL rising
Delay Comparator Threshold
Relative to Charge Voltage, SS/DEL falling
Delay Comparator Threshold
Delay Comparator Input Filter
Delay Comparator Hysteresis
VID Sample Delay Comparator
Threshold
Discharge Comp. Threshold
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Source Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
Slew Rate
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V
VOSEN+ Bias Current
0.5 V < V(VOSEN+) < 1.6V
VOSEN- Bias Current
-0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes
High Voltage
V(VCCL) – V(VO)
Low Voltage
V(VCCL)=7V
Error Amplifier
Input Offset Voltage
Measure V(FB) – V(VSETPT). Note 2
FB Bias Current
VSETPT Bias Current
ROSC= 24.5 KΩ
DC Gain
Note 1
Bandwidth
Note 1
Slew Rate
Note 1
Sink Current
Source Current
Maximum Voltage
Measure V(VCCL) – V(EAOUT)
Page 5 of 38
MIN
5
5
1.04
TYP
9
10
1
1
1.09
MAX
15
17
1.145
UNIT
mA
kΩ
MHz
s
V
1.0
0.8
0.3
0.5
75
0.7
2.9
2.2
1.2
1.2
125
1.4
3.5
3.25
3.0
2.3
300
1.9
ms
ms
ms
ms
us
V
35.0
2.5
10
3.6
50
85
70.0
6.5
16
4.2
125
160
10
2.8
52.5
4.5
12
4.0
80
120
5
30
3.0
60
3.2
A
A
A/A
V
mV
mV
s
mV
V
150
200
275
mV
3.0
-3
0.4
3
2
6.4
0
1
9
4
1.5
160
2
9.0
3
2
20
8
100
275
2.5
50
MHz
mV
mA
mA
V/us
uA
uA
V
mV
-1
-1
23.00
100
20
7
0.40
5
500
0
0
24.25
110
30
12
0.85
8
780
1
1
25.50
120
40
20
1.00
12
950
mV
A
A
dB
MHz
V/s
mA
mA
mV
December 17, 2009
IR3502A
PARAMETER
Minimum Voltage
Open Voltage Loop Detection
Threshold
Open Voltage Loop Detection
Delay
Enable Input
VR 11 Threshold Voltage
VR 11 Threshold Voltage
VR 11 Hysteresis
Bias Current
Blanking Time
TEST CONDITION
MIN
Measure V(VCCL) - V(EAOUT),
Relative to Error Amplifier maximum
voltage.
Measure PHSOUT pulse numbers from
V(EAOUT) = V(VCCL) to PGOOD =
low.
125
ENABLE rising
ENABLE falling
825
775
25
-5
75
850
800
50
0
250
875
825
75
5
400
mV
mV
mV
-40
-25
2
1.17
4096
2048
1024
-10
mV
S
V
Cycle
Cycle
Cycle
0V ≤ V(ENABLE) ≤ 3.3V
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
Over-Current Comparator
Input Offset Voltage
1V ≤ V(IIN) ≤ 3.3V
Input Filter Time Constant
Over-Current Threshold
VDRP-VDAC_BUFF
Over-Current Delay Counter
ROSC = 7.75 KΩ (PHSOUT=1.5MHz)
Over-Current Delay Counter
ROSC = 15.0 KΩ (PHSOUT=800kHz)
Over-Current Delay Counter
ROSC = 50.0 KΩ (PHSOUT=250kHz)
Over-Current Limit Amplifier
Input Offset Voltage
Transconductance
Note 1
Sink Current
Unity Gain Bandwidth
Note 1
Over Voltage Protection (OVP) Comparators
Threshold at Power-up
Measure at 1.5V VCCLDRV
Threshold during Normal
Compare to V(VDAC)
Operation
OVP Release Voltage during
Compare to V(VDAC)
Normal Operation
Threshold during Dynamic VID
down
Dynamic VID Detect Comparator
Threshold
Propagation Delay to IIN
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(IIN) transition to
> 0.9 * V(VCCL).
IIN Pull-up Resistance
Propagation Delay to OVP
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(ROSC/OVP)
transition to >1V.
OVP High Voltage
Measure V(VCCL)-V(ROSC/OVP)
OVP Power-up High Voltage
ROSC = 7.75 KΩ. Measure
V(VCCLDRV)-V(ROSC/OVP) @ 1.5V
OVP Power-up High Voltage
ROSC = 24.5 KΩ. Measure
V(VCCLDRV)-V(ROSC/OVP) @ 1.5V
Page 6 of 38
TYP
120
300
MAX
250
600
8
1.07
UNIT
mV
mV
Pulses
1.27
A
ns
-10
0.50
35
0.75
0
1.00
55
2.00
10
1.75
75
3.00
mV
mA/V
uA
kHz
1.1
105
1.21
125
1.30
145
V
mV
-13
3
20
mV
1.70
1.73
1.75
V
25
50
75
mV
90
180
nS
5
90
0
.100
0
.240
15
180
1.2
.375
0.2
December 17, 2009
Ω
nS
V
V
IR3502A
PARAMETER
PGOOD Output
Output Voltage
Leakage Current
Under Voltage Threshold-VO
decreasing
Under Voltage Threshold-VO
increasing
Under Voltage Threshold
Hysteresis
VCCL_DRV Activation Threshold
Open Sense Line Detection
Sense Line Detection Active
Comparator Threshold Voltage
Sense Line Detection Active
Comparator Offset Voltage
VOSEN+ Open Sense Line
Comparator Threshold
VOSEN- Open Sense Line
Comparator Threshold
Sense Line Detection Source
Currents
VRHOT Comparator
Threshold Voltage
HOTSET Bias Current
Hysteresis
Output Voltage
VRHOT Leakage Current
VCCL Regulator Amplifier
VCCL Output Voltage
VCCLDRV Sink Current
UVLO Start Threshold
UVLO Stop Threshold
Hysteresis
General
VCCL Supply Current
TEST CONDITION
MIN
I(PGOOD) = 4mA
V(PGOOD) = 5.5V
Reference to VDAC
MAX
mV
A
mV
300
10
-350
-300
-250
-290
-240
-190
25
60
95
1
2
3.6
V
150
200
250
mV
30
55
80
mV
87.5
90.0
92.5
%
0.36
0.40
0.44
V
200
500
700
uA
1.584
-1
75
1.600
0
100
150
0
1.616
1
125
400
10
I(PG)=4mA, V(PG) 1.73V
12V
VCC
VCCL+0.7V
VCCL+0.7V
VCCLDRV
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VID + 0.13V
VCCL UVLO
VCCL - 1V
ROSC/OVP
0.6V
3.92V (4V-0.08V)
SS/DEL
Figure 16 Over-voltage protection with pre-charging converter output VID + 0.13V
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