IR3522MTRPBF

IR3522 DATA SHEET XPHASE3TM DDR & VTT CONTROL IC DESCRIPTION The IR3522 Control IC combined with IR3506 xPHASE3TM Phase ICs implements a full featured DDR3 power solution. The IR3522 provides control functions for both the VTT (single phase) and VDDR (multiphase) power rails which can interfaces with any number of IR3506 ICs each driving and monitoring TM a single phase to power any number of DDR3 DIMMs. The xPHASE3 architecture delivers a power supply that is smaller, more flexible, and easier to design while providing higher efficiency than conventional approaches. FEATURES • • • • • • • • • • • • • • I2C interface programs 1.025V< VREF1 V(VREF1) (500 mV overdrive) to V(CROWBAR) transition to > 2 V with 1nF. Measure time from V(VOUT2) > V(VREF1) (250 mV overdrive) to V(CROWBAR) transition to > 2 V with 1nF. To VCCL 5 15 Ω 25 65 kΩ 20 60 Ω 1.06 90 1.13 180 V ns 150 200 250 mV 35 62.5 90 mV 86.5 89.0 91.5 % 0.36 0.40 0.44 V 200 500 700 uA 1.38 50 3.1 1.65 100 3.3 1.94 250 3.5 12 Track Fault Comparator Threshold Voltage Propagation Delay to CROWBAR Compare VOUT1 to VOUT2 Measure time from V(VOUT1) > V(VOUT1) (1.2V overdrive) to V(CROWBAR) transition to > 0.9 * V(VCCL). 0.99 Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents V(VOUTx) < [V(VOSENx+) – V(LGND)] / 2 Compare to V(VCCL) V(VOUTx) = 100mV VIDx VID0 & VID1 Input Thresholds Internal Pull-up Float Voltage Pull-up to 3.3 V typical V kΩ V ENABLE Threshold Increasing Threshold Decreasing Threshold Hysteresis Bias Current Blanking Time 0V ≤ V(x) ≤ 3.5V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 1.38 0.8 470 -5 75 1.65 0.99 620 0 250 1.94 1.2 770 5 400 V V mV uA ns 35 +5 % 23.1 29.1 mV µA Over-Current Comparators Input Offset Voltage OCSET Bias Current 1V ≤ V(OCSETx) ≤ 3.3V 2048-4096 Count Threshold 1024-2048 Count Threshold ROSC value, Note 1 ROSC value, Note 1 Page 7 -35 -5% 11.3 14.4 0 Vrosc(V)*1000/ Rosc(KΩ) 16 20 V3.01 kΩ kΩ IR3522 PARAMETER TEST CONDITION MIN TYP MAX UNIT 3.5 4.20 3.8 0.36 7 4.43 3.99 0.42 15 4.7 4.3 0.46 mA V V V VCCL Supply Current UVLO Start Threshold UVLO Stop Threshold Hysteresis Note 1: Guaranteed by design, but not tested in production Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offsets Bold Letters: Critical specs SYSTEM SET POINT TEST Converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-toanalog converters, the Error Amp input offsets, and the Remote Sense input offsets. The voltage appearing at the VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are shown in Figures 2A and 2B. IR3522 ERROR AMPLIFIER VREF1 BUFFER AMPLIFIER EAOUT1 + - FB1 + ISOURCE "FAST" VDAC VREF1 OC SET1 ISINK ROCSET1 - IOCSET1 IROSC RVREF1 CVREF1 CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER 0.6V LGND + IROSC ROSC RROSC VOUT1 EAOUT SYSTEM SET POINT VOSNSVOLTAGE REMOTE SENSE AMPLIFIER VOSEN1+ + VOSEN1- - Figure 2A - Output 1 System Set Point Test Circuit ERROR AMPLIFIER 2 IR3522 VOUT1 + EAOUT2 - VREF_TRACK FB2 VOUT2 REMOTE SENSE AMPLIFIER 2 VOSEN2+ EAOUT SYSTEM SET POINT VOSNSVOLTAGE VOSEN2- + - Figure 2B - Output 2 System Set Point Test Circuit Page 8 V3.01 IR3522 SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the xPHASE3TM architecture is shown in Figure 3. Feed-forward voltage mode control with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is performed by the phase ICs as a result of sensing the Input voltage (FET’s drain voltage). The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. . GATE DRIVE VOLTAGE VIN IR3522 CONTROL IC PHSOUT CLOCK GENERATOR CLKOUT IR3506 PHASE IC CLKIN VCCH C LK Q PWM LATCH D PHSOUT PHSIN PHSIN VOSNS1+ C BST VC CL SW RESET DOMINANT VOUT1 COUT - EAIN R VCCL + GND GATEL ENABLE + PGND + VID6 - REMOTE SENSE AMPLIFIER GATEH S PWM COMPARATOR VOSNS1- - RAMP DISCHARGE CLAMP VOUT1 VREF1 LGND - IOUT - CURRENT SENSE AMPLIFIER VID6 VID6 + - + 3K R CP1 C CS VID6 VID6 + R FB12 RF B11 + C CP11 FB1 CSIN+ + CC P12 C FB1 R CS - + SHARE ADJUST ERROR AMPLIFIER EAOUT1 - VREF1_FAST + ERROR AMPLIFIER CSIN- DACIN PHSOUT IR3506 PHASE IC CLKIN VCCH C LK Q PWM LATCH D PHSIN GATEH C BST S PWM COMPARATOR - EAIN VC CL SW RESET DOMINANT R VCCL + GATEL ENABLE + PGND VID6 - RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER + IOUT - 3K VID6 VID6 + CSIN+ + + C CS R CS - VID6 VID6 + CSIN- DACIN Figure 3 - PWM Block Diagram Frequency and Phase Timing Control The system oscillator is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an external resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by a daisy chain loop. The control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase timing for a four phase converter. Page 9 V3.01 IR3522 Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 4 Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. Upon receiving a clock falling edge and PHSIN high, the PWM latch is set and the PWM ramp voltage begins to increase and turning off the low side driver The high side driver is then turned on once GATEL falls below 1.0V (non-overlap time). When the PWM ramp voltage exceeds the error amplifier’s output voltage, the PWM latch is reset and the internal ramp capacitor is quickly discharged to the output voltage of share adjust amplifier. And, the ramp will remains discharged until the next clock pulse. This reset turns off the high side driver and enables the low side driver after the non-overlap time ((GATEH-SW) < 1.0V). The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of this architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 5 depicts PWM operating waveforms under various conditions. Page 10 V3.01 IR3522 PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID FAULT) STEADY-STATE OPERATION Figure 5 PWM Operating Waveforms Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series RC network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 6. The equation of this sensing network is, v C ( s ) = v L ( s) 1 + s (L R L ) 1 = i L (s) RL . 1 + sRCS C CS 1 + sRCS C CS Usually, the resistor Rcs and capacitor Ccs are chosen so that the RC time constant equals the time constant of the inductor which is the inductance L divided by the inductor’s DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. vL iL Current Sense Amp L RL RCS CCS VO CO c vCS CSOUT Figure 6 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). Page 11 V3.01 IR3522 An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the IR3506 phase IC, as shown in Figure 7. Its gain is nominally 32.5 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be considered when setting the controller’s current limit. The current sense amplifier can accept positive differential input up to 50 mV and negative up to -10 mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If a single phase current is smaller than the average current, the phase IC share adjust amplifier will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current. Conversely, a phase current larger than the average current will pull up the PWM starting point decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency, of the current share loop, is much slower than that of the voltage loop and the two loops do not interact. Page 12 V3.01 IR3522 IR3522 THEORY OF OPERATION Block Diagram The Block diagram of the IR3522 is shown in Figure 7. The following discussions are applicable to either output plane unless otherwise specified. ENABLE COMPARATOR ENABLE OPEN DAISY - 250nS BLANKING + OPEN SENSE OPEN CONTROL 2 1.65V 1V VCCL OPEN CONTROL 1 DIS VCCL + VCCL VCCL UVLO - LGND TRACK_FLT DISCHARGE DETECT INTERNAL VCCL UVL CIRCUIT BIASCOMPARATOR 4.43V 3.99V OV1-2 CROWBAR SVI _OFF 25k ENABLE I NTERNAL_CROWBAR Fault Latch Control Logic OC TIMEOUT VCCL PGBIAS DLY _OUT SOFT STOP SS_DISCHARGED PGOOD UV2 UV1 SRD_PRESET# 3.9V OC LIMIT COMPARATOR 1 OC DELAY COUTER IOCSET OCSET1 IROSC OC2 SS/DEL1 SRD_PRESET# PHSOUT IROSC OC LIMIT COMPARATOR2 IIN2 ICHG 45uA SS Comparators OC1 DELAY + IIN1 IDCHG 55uA DLY _OUT SRD PRESET + IOCSET - VCCL OPEN CONTROL 1 OPEN CONTROL 2 Open Control Loop ERROR AMPLIFIER 2 ERROR AMPLIFIER 1 INTERNAL_CROWBAR T RACK FAULT COMPARAT OR 70mV - FB2 VOUT1 1.4V VREF1 OV1_2 - + OV2 REMOTE SENSE AMPLIFIER 1 + 25k OPEN SENSE 25k 25k 25k OPEN SENSE LINE DETECT CIRCUIT 2 D/A CONVERT ER VOUT1 SVI (Serial VID Int erface) VID7 VREF CONTROL - VREF1_FAST . VID7 VID1 OFF VALID I2C COMMAND OVERRIDE ARRIVED VID2 OFF VID3 SCL VID3 VID3 VID7 SVI ADDRESS 2X IROSC SVI_OFF VID3 SDA VID3 950mV 650mV 3.3V VID7 VID7 100k ISINK 100k TRACK CONTROL VREF_TRACK 100k VREF1 ADDR1 + IROSC - VID7 ISOURCE + VREF BUFFER AMPLIFIER SS_DISCHARGED - SS_DI SCHARGED OPEN SENSE LINE DETECT CIRCUIT 1 DETECT PULSE1 + DETECT PULSE1 VOSEN1- + IVOSEN2- IVOSEN1+ + IVOSEN2+ VOSEN1+ 25k - 25k VOSEN2- VOUT1 25k + VOSEN2+ REMOTE SENSE AMPLIFIER 2 IVOSEN1- - UV1 - VREF1 VOUT1 UV COMPARATOR 275mV 315mV 260mV - OVER VOLTAGE COMPARAT OR 2 25k EAOUT1 FB1 OVER VOLT AGE COMPARATOR 1 1.0 6V VOUT2 DIS OV1 + UV2 275mV 315mV SS/DEL + VOUT2 UV COMPARATOR TRACK_FLT + - + EAOUT2 I NTERNAL_CROWBAR SOFT ST ART CLAMP VREF_TRACK + DIS 100k IROSC + + OCSET2 VID7 OPEN DAISY FAULT VCCL UVLO POWER-UP VREF1 CONTROL UVLO + - CLKOUT PHSOUT ROSC R Q D CLK CLKOUT PHSIN VID1 0 0 1 1 VID0 0 1 0 1 VREF1 1.05V 1.2V 1.35V VID7 1.5V ENABLE VID7 VID7 VID1 VID0 - PHSIN + IROSC ADDR2 - VREF1 CODE STORAGE LATCH + VID0 - 0.6V CURRENT SOURCE GENERATOR + ROSC BUFFER AMPLIFIER 1.65V PHSOUT Figure 7 Block Diagram Page 13 V3.01 IR3522 Serial VID Control The IR3522 outputs can be controlled via a serial VID Interface (SVID) which employs a Fast Mode I2C protocol. VREF1, which is the reference for VOUT1, can also be programmed to boot-up to one of four codes through pins VID0 and VID1 prior to ENABLE rising if SVID communication is not available prior to power-up. Refer to Table 4. Pins VID0 and VID1 have internal 100K pull-up resistors to an internal 3.3V. The SVID controls both the VOUT1 and VOUT2 margining (see Table 2 or 3) depending on which serial address precedes the data string. See Table 1 for proper address codes. If the top address is used, then both outputs will coincide with the values in Table 2 depending on data code used, where VOUT2 is always half the value of VOUT1. The second address will only have an effect on VOUT2’s amplitude (margining +26.67 % and -25 %) as defined in Table 3. Since there is no internal compensation for Vref_track (VOUT2 reference), It is recommended that VOUT2 be incremented to its final value to prevent possible output overshoot. If no serial command is received before an enable event (ENABLE pin going high), the controller’s VOUT1 will startup in a default state as indicated in Table 4 and VOUT2 to 0.75 V (half of VDAC). Addresses and data are serially transmitted in 8-bit words. The first data bit of the SVID data word represents the PSI_L bit and will be ignored by the IR3522 therefore this system will never enter a power-saving mode. The remaining data bits SVID[6:0] select the desired VOUTx regulation voltage as defined in Table 2 or Table 3 depending address chosen. VOUT1 is divided in half by an internal resistor divider to provide a reference voltage (Vref_track) for VOUT2. This allows VOUT2 to track VOUT1 maintaining a desired differential voltage. SVID [6:0] are the inputs to the Digital-to-Analog Converter (VREF) which then provides an analog reference voltage to the transconductance type buffer amplifier. This VREF buffer provides a system reference on the VREF1 pin. The VREF1 voltage along with error amplifier and remote sense differential amplifier input offsets are post-package trimmed to provide a 0.5% system set-point accuracy, as measured in Figures 2A and 2B. VREF1 slew rates are programmable by properly selecting external series RC compensation networks located between the VREF1 and the LGND pins. The VREF1 source and sink currents are derived off the external oscillator frequency setting resistor, RROSC. The programmable slew rate enables the IR3522 to smoothly transition the regulated output voltage throughout VID transitions resulting in a power supply input and output capacitor inrush currents, along with output voltage overshoot, to be well controlled. The ADDR1 and ADDR2 pins (5, 6) are reserved for controller addressing. These pins have internal 100K pull-up resistors to an internal 3.3V. By floating or shorting to ground these two pins, four different controller identification address states can be made. By setting bit 2 and 3 of the SVI address codes (see Figure 8) to the desired controller address, a CPU can communicate with one controller while ignoring other controllers sharing the same SVID bus. SVI Address [6:0] + Wr 6 5 4 ADDR1 ADDR2 1 0 WR Figure 8 Bit 2 and 3 are use for Controller addressing The SCL and SDA pins require external pull-up biasing and should not be floated. Biasing of pins SDA, SCL, VID0, VID1, ADDR1 and ADDR2 prior to applying VCCL is acceptable. For Write, WR=0. SVI Address SVI Address [6:0] + Wr [bit6 :bit5 : bit4 : ADDR1 _ ADDR2 : bit1 : bit0 : WR] 1101_1100 in binary or D_C in hex if ADDR1 and ADDR2 pins are high 1101_1010 in binary or D_A in hex if ADDR1 and ADDR2 pins are high Description Set VID only Output 1 Set VID only Output 2 BOLD indicates the pin states of ADDR1 and ADDR2, in this case high or floating. Table 1 – SVI Address Page 14 V3.01 IR3522 VDDR (VREF1) SVID Codes and Resulting VTT Default (50%) Voltage Hex VDDR SVID Codes 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F X000_0000 X000_0001 X000_0010 X000_0011 X000_0100 X000_0101 X000_0110 X000_0111 X000_1000 X000_1001 X000_1010 X000_1011 X000_1100 X000_1101 X000_1110 X000_1111 X001_0000 X001_0001 X001_0010 X001_0011 X001_0100 X001_0101 X001_0110 X001_0111 X001_1000 X001_1001 X001_1010 X001_1011 X001_1100 X001_1101 X001_1110 X001_1111 X010_0000 X010_0001 X010_0010 X010_0011 X010_0100 X010_0101 X010_0110 X010_0111 X010_1000 X010_1001 X010_1010 X010_1011 X010_1100 X010_1101 X010_1110 X010_1111 x1xx_xxxx VDDR, VREF1, VOUT1 VOUT2 Typical Target 1.6125 0.80625 1.6 0.8 1.5875 0.79375 1.575 0.7875 1.5625 0.78125 1.55 0.775 1.5375 0.76875 1.525 0.7625 1.5125 0.75625 1.5 0.75 1.4875 0.74375 1.475 0.7375 1.4625 0.73125 1.45 0.725 1.4375 0.71875 1.425 0.7125 1.4125 0.70625 1.4 0.7 1.3875 0.69375 1.375 0.6875 1.3625 0.68125 1.35 0.675 1.3375 0.66875 1.325 0.6625 1.3125 0.65625 1.3 0.65 1.2875 0.64375 1.275 0.6375 1.2625 0.63125 1.25 0.625 1.2375 0.61875 1.225 0.6125 1.2125 0.60625 1.2 0.6 1.1875 0.59375 1.175 0.5875 1.1625 0.58125 1.15 0.575 1.1375 0.56875 1.125 0.5625 1.1125 0.55625 1.1 0.55 1.0875 0.54375 1.075 0.5375 1.0625 0.53125 1.05 0.525 1.0375 0.51875 1.025 0.5125 VID OFF, no change in VREF or VTT Table 2: VDDR Margin Codes and resulting 50% Vtt Tracking (VIDX pin controlled codes are in Gray) Page 15 V3.01 IR3522 VTT Margining Range Codes Hex VTT SVID Codes % Change from Default % Change from VOUT1 0 1 2 3 4 5 6 7 8 9 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F x000_0000 x000_0001 x000_0010 x000_0011 x000_0100 x000_0101 x000_0110 x000_0111 x000_1000 x000_1001 x000_1010 x000_1011 x000_1100 x000_1101 x000_1110 x000_1111 x001_0000 x001_0001 x001_0010 x001_0011 x001_0100 x001_0101 x001_0110 x001_0111 x001_1000 x001_1001 x001_1010 x001_1011 x001_1100 x001_1101 x001_1110 x001_1111 x1xx_xxxx 26.67 25 23.33 21.67 20 18.33 16.67 15 13.33 11.67 10 8.33 6.67 5 3.33 1.67 0 -1.67 -3.33 -5 -6.67 -8.33 -10 -11.67 -13.33 -15 -16.67 -18.33 -20 -21.67 -23.33 -25 VID OFF 63.16 62.35 61.52 60.70 59.87 59.06 58.23 57.40 56.59 55.78 54.94 54.12 53.28 52.46 51.64 50.82 50 49.16 48.31 47.46 46.61 45.78 44.93 44.08 43.25 42.42 41.58 40.74 39.90 39.08 38.21 37.44 VID OFF Table 3 – Vtt Margining (Default in Gray) Pre-ENABLE VREF1 Codes VID1 VID0 VDDR 0 0 1.05 0 1 1.2 1 0 1.35 1 1 1.5 Table 4 – Pre-Enable VDDR program Codes Page 16 V3.01 IR3522 Response Latch Reset Open Daisy Open Sense Open Control UVLO CLEARED Latch Recycle VCCL Tracking Fault OC Over Voltage ENABLE CLEARED Latch Recycle EN or Cycle VID_OFF through SVID Disable VID_OFF SVID SS Latch SS discharge below 0.22V Both Outputs Affected Disables EA Soft Stop CROWBAR UVLO (Vout) No No none Yes No No No Yes Yes No No Yes Flags PGood Delays UVLO (VCCL) 32 Clock Pulses No 8 PHSOUT No No Delay Counter No Pulses 250ns No Blanking Time Additional Yes, Flagged Response IIN1 pin is pulled-up to VCCL when SS discharge below 0.35V. This action latches on the Phase IC(s) Diode Emulation Mode which insure proper current sharing during soft start**. No *Pulse number range depends on Rosc value selected (See Specifications Table) ** IIN1 is pulled low when SS charges above 0.4V. Table 5 – IR3522 Fault protocol . Page 17 No V3.01 IR3522 Serial VID Interface Protocol and VID-on-the-fly Transition 2 The IR3522 supports the SVI bus protocol which is based on Fast-mode I C. SVID commands from a processor are communicated through SVID bus pins SCL and SDA. The SMBus send byte protocol is used by the IR3522 VID-on-the-fly transactions. The IR3522 will wait until it detects a start bit which is defined as an SDA falling edge while SCL is high. A 7bit address code plus one write bit (low) should then follow the start bit. This address code will be compared against an internal address table and the IR3522 will reply with an acknowledge ACK bit if the address is one of the two stored addresses otherwise the ACK bit will not be sent out. The SDA pin is pulled low by the IR3522 to generate the ACK bit. Table 1 has the list of addresses recognized by the IR3522. The processor should then transmit the 8-bit data word immediately following the ACK bit. The first bit is ignored (bit 7). The IR3522 replies again with an ACK bit once the data is received. If the received data is not a VID-OFF command, the IR3522 immediately changes the VREF1 analog outputs to the new target. VOUT1 and VOUT2 then slew to the new VID voltages. See Figure 9 for a send byte example. Figure 9 Send Byte Example Page 18 V3.01 IR3522 Remote Voltage Sensing VOSENX+ and VOSENX- are used for remote sensing and are connected directly to the load. The remote sense differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage sensing and fast transient response. Start-up Sequence The IR3522 is designed as a chipset with the IR3506 Phase IC to achieve output voltage tracking. VOUT2’s internal reference (VREF_TRACK) is generated by a divided-by-half internal resistor divider. This will ensure VOUT2 remains half the value of VOUT1 preventing possible damage to some DDR system’s microprocessors. In addition, a track-fault comparator is implemented to monitor both outputs which will further guarantee the outputs remain at least 1.0 V apart and will generate a fault if this limit is surpassed, further protecting the DDR system. When VCCL is applied to the IC and the SS/DEL is below 0.3V, IIN1 (only) is pulled up to VCCL through an internal PFET enabling a diode emulation preset latch on the IR3506 phase IC. Diode emulation mode ensures proper current sharing during system soft-start by turning off the bottom sync FET when negative inductor current is sensed via the CSIN- and CSIN+ pins. The IIN1 pin is release once SS/DEL charges above 0.3 V. Once VOUT1 reaches 75% of its final operating value, the diode emulation mode is reset allowing the phase ICs to sink current. The IR3522 has a programmable soft-start and soft-stop function. The soft-start helps limit the surge current during the converter start-up, whereas the soft-stop is needed to maintain output tracking during system turn-off. A capacitor connected between the SS/DEL and LGND pins controls timing. A constant source and sink current control the charge and discharge rates of the SS/DEL. Figure 10 depicts the SVID start-up sequence. When the ENABLE input is asserted and there are no faults, the SS/DEL pin will begin charging. If the IC receives a SVID communication prior to the ENABLE pin going high, the output ramps up to the program value listed in Table 2, otherwise the VOUT1 and VOUT2 default to 1.5 V and 0.75 V, respectively. The error amplifier output, EAOUTx, is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output voltage to match the V(SS/DEL)-1.4V offset until the converter output reaches the SVID code or default state. The SS/DEL voltage continues to increase until it rises above the threshold of Delay Comparator where the PGOOD output is allowed to go high. A low signal on the ENABLE or VID_OFF input immediately sets the fault latch, which causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and SS/DEL discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DEL discharge comparator allowing another soft start charge cycle to occur. All other faults (See Table 5) will set a different fault latch that can only be reset by cycling ENABLE or the VID_OFF SVID command. These faults discharge SS/DEL, pull down EAOUTX, pull up CROWBAR to VCCLDRV and drive PGOOD low. The CROWBAR circuit is design to drive an external NMOS device to pull the output voltage to ground. This feature minimizes negative voltage undershoots at the output by reducing sync FET current during fault events. The converter can be disabled by pulling the SS/DEL pins below 0.6V Page 19 V3.01 IR3522 VCCL (6.8V) ENABLE Vtt Margining VDDR Margining CLOCK SVC SVID OFF COMMAND SVID ON COMMAND SVID OFF COMMAND SVID ON COMMAND SVID TRANSITION SVD READ & STORE SVID programmed voltage VREF1 VREF_TRACK 0.8V VREF1/Track Tracks 4.0V 3.92V 1.4V 1.4V SS/DEL EAOUT1 EAOUT2 EAOUTx Soft Stop VOUT1 VOUT2 PGOOD NORMAL START OPERATION DELAY TIME STARTUP VOUT1 ON VOUT2 ON THE FLY THE FLY MARGINING MARGINING SVID OFF TRANSITION SVID ON TRANSITION Figure 10 SVID Start-up Sequence Transitions Page 20 V3.01 IR3522 Over-Current Protection The over current limit threshold is set by a resistor connected between OCSETX and VREF1 pin. An over current fault is flagged after a delay programmed by Rocs (see Electrical Specification). The delay is required since overcurrent conditions can occur as part of normal operation due to load transients or VID transitions. If the IINX pin voltage, which is proportional to the average current plus VREF1 voltage, exceeds the OCSETx voltage, the OCDELAY counter starts counting the PHSOUT pulses. If the over-current condition persists long enough for the counter to reach the program number, the fault latch will be set which will then pull the error amplifier’s output low to stop phase IC switching and will also de-assert the PGOOD signal. The SS/DEL capacitor will then discharge by a 55 uA current. The output current is not controlled during the delay time. This latch can only reset by either recycling the ENABLE pin or VID_OFF command. VCCL Under Voltage Lockout (UVLO) The IR3522 monitors the VCCL supply voltage to determine if the amplitude is proper to adequately drive the top and bottom gates. As VCCL begins to rise during power up, the IC is allowed to power up when VCCL reaches 4.43 V (Typical). The ENABLE CLEARED fault latches will be released. If VCCL voltage drops below 3.99V (Typical) of the set value, the ENABLE CLEARED fault latch will be set. VID OFF Codes SVID OFF codes will turn off the converter keeping the error amplifiers active and discharging SS/DEL through the 50uA discharge current allowing the outputs to discharge in a control manner (soft-stop). Upon receipt of a non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in Figure 10. Power Good (PGOOD) The PGOOD pin is an open-drain output and should have an external pull-up resistor. During soft start, PGOOD remains low until the output voltage is in regulation and SS/DEL is above 3.9V. The PGOOD pin becomes low if any fault is registered (see TABLE 5 for details). A high level at the PGOOD pin indicates that the converter is in operation with no fault and ensures the output voltage is within regulation. PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but the VR continues to regulate its output voltages. Output voltage out-of-spec is defined as 315mV to 275mV below nominal voltage. VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code and a voltage associated with another VID code is not considered to be out of specification. Open Voltage Loop Detection The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault latch is set. The fault latch can only be cleared by cycling the ENABLE or the VID_OFF command. Enable Input Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.65V allows the SS/DEL pin to begin a power-up cycle. Over Voltage Protection (OVP) Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is compromised. If the over-voltage protection comparators sense that either VOUT1 pin voltage exceeds VREF1 by 260mV or VOUT2 exceeds VREF1, the over voltage fault latch is set which pulls the error amplifier output low to turn off the converter power stage. The IR3522 communicates an OVP condition to the system by raising the CROWBAR pin voltage to within V(VCCL) – 0.2 V. With the error amplifiers outputs low, the low-side MOSFET Page 21 V3.01 IR3522 turn-on within approximately 150ns. The low side MOSFET will remain low until the over voltage fault condition latch cleared. This latch is cleared by cycling the ENABLE pin or the VID_OFF command. The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible, a fuse can be added in the input supply to the multiphase converter. Open Remote Sense Line Protection If either remote sense line VOSENX+ or VOSENX- is open, the output of Remote Sense Amplifier (VOUTX) drops. The IR3522 continuously monitors the VOUTX pin and if VOUTX is lower than 200 mV, two separate pulse currents are applied to the VOSENX+ and VOSENX- pins to check if the sense lines are open. If VOSENX+ is open, a voltage higher than 90% of V(VCCL) will be present at VOSENX+ pin and the output of Open Line Detect Comparator will be high. If VOSENX- is open, a voltage higher than 400mV will be present at VOSENX- pin and the Open Line Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to force the error amplifier output low and immediately shut down the converter. SS/DEL will be discharged and the Open Sense Fault Latch can only be reset by cycling the ENABLE pin or the VID_OFF command. Open Daisy Chain Protection The IR3522 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects the feedback at PHSIN pin. If no pulse comes back after 30 CLKOUT pulses, the pulse is restarted again. If the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DELX is not allowed to charge. The fault latch can only be reset by cycling the ENABLE pin or the VID_OFF command. After powering up, the IR3522 monitors PHSIN pin for a phase input pulse equal or less than the number of phases detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an Open Daisy Chain fault is registered. Phase Number Determination After a daisy chain pulse is started, the IR3522 checks the timing of the input pulse at PHSIN pin to determine the phase number. Page 22 V3.01 IR3522 DESIGN PROCEDURES - IR3522 AND IR3506 CHIPSET IR3522 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor RRosc The only one oscillator of IR3522 generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor RROSC, use Figure 11 to determine the RROSC value. The CLKOUT frequency equals the switching frequency multiplied by the phase number. PHSOUT FREQUENCY vs. RROSC 1600 1500 1400 1300 Frequency (KHz) 1200 1100 1000 900 800 700 600 500 400 300 200 5 10 15 20 25 30 35 40 45 50 55 RROSC (KOhm) Figure 11 - PHSOUT Frequency vs. RROSC chart Soft Start Capacitor CSS/DEL The Soft Start capacitor CSS/DEL programs three different time parameters, soft start delay time, soft start time, and soft stop time. SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. Once the ENABLE pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V. Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft start time TD2 represents the time during which converter voltage rises from zero to SVID voltage (or default voltage) and the SS/DEL pin voltage rises from 1.4V to SVID voltage plus 1.4V. Power good time, TD3, is the time period from VR reaching the SVID voltage to the PGOOD signal being issued. Calculate CSS/DEL based on the required soft start time TD2. Page 23 V3.01 IR3522 C SS / DEL = TD 2 * I CHG TD 2 * 45 * 10 −6 = SVID SVID (1) The soft start delay time TD1, power good time TD3, and soft stop time are determined by equation (2), (3) and (4) respectively. TD1 = C SS / DEL *1.4 C SS / DEL * 1.4 = I CHG 45 * 10 −6 TD3 = C SS / DEL * (3.92 − SVIC − 1.4) C SS / DEL * (3.92 − SVID − 1.4) = I CHG 45 * 10 −6 TD 4 = C SS / DEL * SVIS C SS / DEL * SVID = I CHG 55 *10 −6 (2) (3) (4) VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC The slew rate of VREF1 down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in (5), where ISINK is the sink current of VREF1 pin. The resistor RVDAC is used to compensate VDAC circuit and is determined by (6) CVDAC = I SINK SR DOWN RVDAC = 0.5 + 3.2 ∗ 10 −15 CVDAC 2 (5) (6) Over Current Setting Resistor ROCSET The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset (VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current sense resistor RCS. VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS (7) The inductor DC resistance is utilized to sense the inductor current. RL is the inductor DCR. The over-current limit is set by the external resistor, ROCSET, as defined in (9). ILIMIT is the required over current limit. IOCSET is the bias current of OCSET pin and can be calculated with the equation in the ELECTRICAL CHARACTERISTICS Table. GCS is the gain of the current sense amplifier of the IR3506 phase IC. KP is the ratio of inductor peak current over average current in each phase and can be calculated from (10). ROCSET = [ KP = Page 24 I LIMIT ∗ RL ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET (9) n (VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2) IO / n (10) V3.01 IR3522 IR3506 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor CCS and Resistor RCS The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows. L RL RCS = (11) C CS Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC 0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs. Type III Compensation Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase, the desired phase margin θc and Rfb1 (see Figure 12). Determine the component values based on the equations below. wc is 2*π*fc (the crossover angular frequency), Le is the equivalent inductance of the converter, C is the output capacitance, Rst is the total equivalent resistance in series with the inductor, Rc is the output capacitance ESR and R is the load resistance. 1 K ⋅ Rfb1 1 Rcp = Ccp ⋅ wz1 1 Cfb = wz 2 ⋅ Rfb1 1 Ccp1 = wp 2 ⋅ Rcp Ccp = Rfb 2 = Page 25 1 wp1 ⋅ Cfb (12) (13) (14) (15) (16) V3.01 IR3522 where, wz1 = wc 10 wz 2 = wc ⋅ (17) 1 − sin(θc) 1 + sin(θc) (18) 1 + sin(θc) 1 − sin(θc) wp 2 = 1.4 ⋅ wp1 wp1 = wc ⋅ 4 K= 2 4 2 2 2 (19) (20) 2 2 2 2 ( wc ⋅ t + wc ⋅ t )((1 − b ⋅ wc ) + a ⋅ wc )( R + Rst ) Gpwm ⋅ H ⋅ t 5 ⋅ t 6 ⋅ R (21) where, Gpwm is the gain of the PWM generator, H is the gain of the feedback filter and Le + C ( R ⋅ Rst + R ⋅ Rc + Rst ⋅ Rc) R + Rst R + Rc b = Le ⋅ C R + Rst wc 2 t1 = 1 − wz1 ⋅ wz 2 wc 2 t2 = 1 − wp1 ⋅ wp 2 1 1 t3 = + wz1 wz 2 1 1 t4 = + wp1 wp 2 a= (22) (23) (24) (25) (26) (27) t 5 = (1 − b ⋅ wc 2 + wc 2 ⋅ Rc ⋅ C ⋅ a) 2 + wc 2 ( Rc ⋅ C (1 − b ⋅ wc 2 ) − a) 2 (28) t 6 = wc 4 (t 2 ⋅ t 3 − t1 ⋅ t 4 ) 2 + wc 2 (t1 ⋅ t 2 + wc 2 ⋅ t 3 ⋅ t 4 ) 2 (29) Figure 12 Voltage Loop Compensation Network Page 26 V3.01 IR3522 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • • • • • • • • • Dedicate at least one middle layer for a ground plane LGND. Connect the ground tab under the control IC to LGND plane through a via. Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce the noise coupling. Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins. Place the following critical components on the same layer as control IC and position them as close as possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection. Place the compensation components on the same layer as control IC and position them as close as possible to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection. Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes. Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes. Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation components. Page 27 V3.01 IR3522 PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. • Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. • Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. • No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads. Page 28 V3.01 IR3522 SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. • The minimum solder resist width is 0.13mm. • At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. • The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. • Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented or plugged from bottom boardside with solder resist. Page 29 V3.01 IR3522 STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. • The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. • The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. • The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 30 V3.01 IR3522 PACKAGE INFORMATION 32L MLPQ (5 x 5 mm Body) θJA =24.4 oC/W, θJC =0.86 oC/W Page 31 V3.01 IR3522 Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 32 V3.01