IR3523MTRPBF

IR3523 DATASHEET XPHASE3TM DUAL OUTPUT CONTROL IC DESCRIPTION The IR3523 Control IC provides a full featured and flexible way to implement a complete dual output DDR & CPU VTT multiphase power solution for Intel VR11.1 motherboards. Each output interfaces with any number of TM xPHASE3 Phase ICs each driving and monitoring a single phase. Output 1 includes a 3 bit VR11.x VID, 1.1V boot voltage and droop to implement the CPU VTT rail which is typically 1 phase. Output 2 includes a 3 bit VID for TM margining and supports any number of phases and DDR DIMM modules. The xPHASE3 architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. INDEPENDENT FEATURES FOR BOTH OUTPUT 1 & 2 • • • • • • • • • Enable Input Power Good (PG) Output 0.5% overall system set point accuracy Programmable Softstart High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us Remote sense amplifier provides differential sensing and requires less than 50uA bias current Programmable over current threshold triggers constant converter output current limit during start-up and hiccup protection during normal operation Over voltage condition communicated to phase ICs by IIN (ISHARE) and system by ROSC/OVP pins Detection and protection of open remote sense lines OUTPUT 1 ADDITIONAL FEATURES • • • • • 3 bit Intel VR11.x VID (VID4, VID3, VID2) Programmable VID offset 1.1 V Boot Voltage Programmable output impedance Programmable VID-on-the-Fly Slew Rate OUTPUT 2 ADDITIONAL FEATURES • • 3 bit VID provides 1.5 V with ±150mV margining Programmable VID-on-the-Fly Slew Rate FEATURES SHARED BY BOTH OUTPUTS 1 & 2 • • • • Programmable per phase switching frequency of 250kHz to 1.5MHz Daisy-chain digital phase timing provides accurate phase interleaving without external components Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO Over voltage signal to system with over voltage detection during powerup and normal operation ORDERING INFORMATION Device Package IR3523MTRPBF 40 Lead MLPQ (6 x 6 mm body) 3000 per reel 40 Lead MLPQ (6 x 6 mm body) 100 piece strips * IR3523MPBF * Samples only Page 1 of 37 Order Quantity June 20, 2008 IR3523 APPLICATION CIRCUIT 12V Q1 RVCCLFB1 RVCCLFB2 12V To Pow er Stage VCCL To Phase IC VCCL & GATE DRIVE BIAS CVCCL 4.7uF RVCCLDRV PG2 VID2_0 VID2_1 PHSIN VID2_2 CLKOUT CCP21 32 31 CLKOUT PHSOUT 34 35 33 PHSIN VCCL VCCLFB 37 36 OCSET1 RFB22 CFB2 NC FB1 EAOUT1 30 29 28 PG1 27 OVP FLAG 26 ROSC 25 CSS/DEL1 24 RVDAC1 CVDAC1 23 22 ISHARE1 ROCSET1 VDAC1 21 EAOUT1 CDRP1 To Output 2 Remote Sense RFB21 CFB1 RFB12 RFB11 RCP1 CCP11 CCP12 RFB13 VOUT2 SENSE + 3 Wire Analog Control Bus to Output 1 Phase ICs RDRP1 RTHERMISTOR1 CCP22 3 w ire Digital Daisy Chain Bus to Phase ICs 20 19 VOUT1 18 EAOUT2 VOSNS1+ OCSET2 11 RCP2 VCCLDRV 38 VDAC1 VOUT2 VDAC2 NC 10 IIN1 SS/DEL1 13 9 VDRP1 SS/DEL2 FB2 ROCSET2 PG2 39 IIN2 12 7 RVDAC2 8 VONSN1- 6 CSS/DEL2 CVDAC1 ROSC/OVP IR3523 CONTROL IC ENABLE1 17 5 PG1 ENABLE2 16 ENABLE 1 VID1_2 VOSNS2- 4 NC LGND 15 3 VID1_3 VOSNS2+ VID1_2 ENABLE 2 VID1_4 14 2 VID2_0 1 VID1_3 VID2_1 VID1_4 VID2_2 40 PHSOUT Load Line NTC Thermistor; Locate close to Output 1 Pow er Stage VOUT1 SENSE + VOUT2 SENSE - VOUT1 SENSE EAOUT2 VREF2 ISHARE2 To Output 2 Remote Sense 3 Wire Analog Control Bus to Output 2 Phase ICs Figure 1 – IR3523 Application Circuit PIN DESCRIPTION PIN# 1-3 4 PIN SYMBOL VID1_4, VID1_3, VID1_2 ENABLE2 5 ENABLE1 6 IIN2 7 SS/DEL2 8 VDAC2 9 OCSET2 10 11,20,30 EAOUT2 NC Page 2 of 37 PIN DESCRIPTION VID inputs for Output 1 Enable input. A logic low applied to this pin puts output 2 into fault mode. A logic high signal on this pin enables output 2. Do not float as the logic state will be undefined. Enable input. A logic low applied to this pin puts output 2 into fault mode. A logic high signal on this pin enables output 2. Do not float as the logic state will be undefined. Output 2 average current input from the output 2 phase IC(s). This pin is also used to communicate over voltage condition to the output 2 phase ICs. Programs output 2 startup and over current protection delay timing. Connect an external capacitor to LGND to program. Output 2 reference voltage. Connect an external RC network to LGND to provide compensation for the internal buffer amplifier Programs the output 2 constant converter output current limit and hiccup overcurrent threshold through an external resistor tied to VDAC2 and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC2 to program the threshold higher than the possible signal into the IIN pin from the phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Output 2 error amplifier output No Connection June 20, 2008 IR3523 PIN# 12 13 14 15 16 17 18 19 21 22 PIN SYMBOL FB2 VOUT2 VOSEN2+ VOSEN2VOSEN1VOSEN1+ VOUT1 FB1 EAOUT1 OCSET1 23 VDAC1 24 SS/DEL1 25 IIN1 26 VDRP1 27 ROSC/OVP 28 29 31 PG1 LGND CLKOUT 32 PHSOUT 33 34 PHSIN VCCL 35 VCCLFB 36 VCCLDRV 37 38, 39, 40 PG2 VID2_0, VID2_1, VID2_2 Page 3 of 37 PIN DESCRIPTION Output 2 Error Amplifier inverting input Output 2 remote sense amplifier output. Output 2 remote sense amplifier input. Connect to output at the load. Output 2 remote sense amplifier input. Connect to ground at the load. Output 1 remote sense amplifier input. Connect to ground at the load. Output 1 remote sense amplifier input. Connect to output at the load. Output 1 remote sense amplifier output. Inverting input to the output 1 Error Amplifier Output 1 error amplifier output Programs the output 1 constant converter output current limit and hiccup overcurrent threshold through an external resistor tied to VDAC1 and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC1 to program the threshold higher than the possible signal into the IIN pin from the phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Output 1 reference voltage programmed by the VID inputs and error amplifier non-inverting input. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. Programs output 1 startup and over current protection delay timing. Connect an external capacitor to LGND to program. Output 1 average current input from the output 1 phase IC(s). This pin is also used to communicate over voltage condition to phase ICs. Output 1 Buffered IIN signal. Connect an external RC network to FB1 to program converter output impedance. Connect a resistor to LGND to program oscillator frequency and OCSET, VDAC1 and VREF2 bias currents. Oscillator frequency equals switching frequency per phase. The pin voltage is 0.6V during normal operation and higher than 1.6V if over-voltage condition is detected. Open collector output. Asserted when Output 1 is regulated. Local Ground for internal circuitry and IC substrate connection. Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of phase ICs. Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first phase IC. Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC. Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. Output of the VCCL regulator error amplifier to control external transistor. The pin senses the converter input voltage through a resistor. Open collector output. Asserted when Output 2 output is regulated. VID inputs for Output 2 June 20, 2008 IR3523 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are absolute voltages referenced to the LGND pin. o Operating Junction Temperature……………..0 to 150 C o o Storage Temperature Range………………….-65 C to 150 C ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C PIN # 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 Page 4 of 37 PIN NAME VID1_4 VID1_3 VID1_2 ENABLE2 ENABLE1 IIN2 SS/DEL2 VDAC2 OCSET2 EAOUT2 FB2 VOUT2 VOSEN2+ VOSEN2VOSEN1VOSEN1+ VOUT1 FB1 EAOUT1 OCSET1 VDAC1 SS/DEL1 IIN1 VDRP1 ROSC/OVP PG1 LGND CLKOUT PHSOUT PHSIN VCCL VCCLFB VCCLDRV PG2 VID2_0 VID2_1 VID2_2 VMAX 8V 8V 8V 3.5V 3.5V 8V 8V 3.5V 8V 8V 8V 8V 8V 1.0V 1.0V 8V 8V 8V 8V 8V 3.5V 8V 8V 8V 8V 8V n/a 8V 8V 8V 8V 3.5V 10V 8V 8V 8V 8V VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.5V -0.5V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.5V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 1mA 5mA 1mA 1mA 1mA 25mA 1mA 5mA 5mA 5mA 5mA 5mA 5mA 1mA 25mA 1mA 1mA 1mA 5mA 35mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA June 20, 2008 ISINK 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 10mA 1mA 25mA 1mA 1mA 1mA 1mA 25mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 20mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA 1mA 1mA IR3523 RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN o o 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DELx = 0.1uF ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions (unless otherwise specified). Typical values represent the median values, which are related to 25°C. PARAMETER System Set Point Accuracy Deviation from Table 1 for Output 1 and deviation from Table 2 for Output 2 per test circuit in Figure 4a and 4b, respectively TEST CONDITION MIN TYP MAX UNIT Output 2 and Output 1 -0.5 0.5 % Output 2 at 1.8V (only) -1.5 1.5 % Increasing Decreasing (VID2_0 and VID2_1 Only) Hysteresis (VID2_0 and VID2_1 Only) 0.85 550 190 100 .95 650 300 175 1.05 750 410 250 V mV mV kΩ -10% See Figure 2 0.600 +10% kHz 0.625 1 V V 1 1 V V 1 70 V % 8 30 0.6 1 mV mA mA MHz V/µs µA VIDx Interface Input Thresholds Pull-Down Resistance Oscillator PHSOUT Frequency ROSC Voltage CLKOUT High Voltage CLKOUT Low Voltage PHSOUT High Voltage PHSOUT Low Voltage PHSIN Threshold Voltage 0.575 I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT)= 10 mA I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT)= 1 mA Compare to V(VCCL) 30 50 -8 2 0.2 0 VDRP1 Buffer Amplifiers Input Offset Voltage Source Current Sink Current Unity Gain Bandwidth Slew Rate IIN Bias Current V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN1) ≤ 3.3V 0.5V ≤ V(IIN1) ≤ 3.3V Note 1 Note 1 -1 0.4 8 4.7 0 3.0 -3 6.4 0 9.0 3 MHz mV 0.5 2 2 1 12 4 1.7 18 8 mA mA V/us 30 30 50 50 250 1 uA uA mV V +8% µA +11% µA Remote Sense Differential Amplifiers Unity Gain Bandwidth Input Offset Voltage Source Current Sink Current Slew Rate VOSEN+ Bias Current VOSEN- Bias Current Low Voltage High Voltage VDAC1 & VDAC2 Outputs Source Currents Sink Currents Page 5 of 37 Note 1 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V, Note 2 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V, Note 1 0.5 V < V(VOSENx+) < 1.6V -0.3V ≤ VOSENx- ≤ 0.3V, All VID Codes V(VCCL) = 7V V(VCCL) – V(VOUTx) 0.5 Includes I(OCSET) -8% Includes I(OCSET) -11% 3000*Vrosc( V)/ ROSC(kΩ) 1000*Vrosc V)/ ROSC(kΩ) June 20, 2008 IR3523 PARAMETER Soft Start and Delay Start Delay Start-up Time OC Delay Time SS/DELx to FB Input Offset Voltage Charge Current OC Delay Discharge Currents Fault Discharge Current Hiccup Duty Cycle Charge Voltage (Output 1,2) Delay Comparator Threshold Delay Comparator Threshold TEST CONDITION MIN TYP MAX UNIT Measure Enable to EAOUTx activation Measure Enable activation to PGx V(IINx) – V(OCSETx) = 500 mV 1 3 200 2.9 8 650 3.5 13 1000 ms ms us With FB = 0V, adjust V(SS/DEL) until EAOUTx drives high 0.7 1.4 1.9 V -30 -50 47 4.5 10 3.9 70 -70 µA µA µA µA/µA V mV Measure at charge voltage I(Fault) / I(Charge) 2.5 8 3.5 Relative to Charge Voltage, SS/DELx rising - Note 1 Relative to Charge Voltage, SS/DELx falling - Note 1 Delay Comparator Hysteresis VID1 Sample Delay Comparator Threshold Discharge Comp. Threshold 6.5 12 4.2 135 mV 2.8 65 3.0 3.2 mV V 150 200 300 mV -1 0 1 mV -5% Vrosc(V)*100 0 /Rosc(KΩ) +5% µA -1 100 20 5.5 0.4 5.0 500 0 110 30 12 0.85 8.5 780 120 300 1 135 40 20 1 12.0 950 250 600 µA dB MHz V/µs mA mA mV mV mV Error Amplifiers Input Offset Voltage Measure V(FBx) – V(VDACx)). Note 2 o o 25 C ≤ TJ ≤ 100 C FB1 Bias Current FB2 Bias Current DC Gain Bandwidth Slew Rate Sink Current Source Current Maximum Voltage Minimum Voltage Open Control Loop Detection Threshold Open Control Loop Detection Delay Note 1 Note 1 Note 1 Measure V(VCCL) – V(EAOUTx) Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUTx) = V(VCCL) to PGx = low. 125 8 Pulse ENABLE Inputs Threshold Increasing Threshold Decreasing Threshold Hysteresis Bias Current Blanking Time PGx Outputs Under Voltage Threshold - Voutx Decreasing Under Voltage Threshold - Voutx Increasing Under Voltage Threshold Hysteresis Output Voltage Leakage Current VCCL_DRV Activation Threshold Page 6 of 37 1.38 0.8 470 -5 75 1.65 0.99 620 0 250 1.94 1.2 800 5 400 V V mV uA ns Reference to VDAC -365 -315 -265 mV Reference to VDAC -325 -275 -225 mV 5 53 110 mV 1.0 150 0 2.0 300 10 3.6 mV µA V 0V ≤ V(x) ≤ 3.5V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 I(PGx) = 4mA V(PGx) = 5.5V I(PGx) = 4mA, V(PGx) < 400mV, V(VCCL) = 0 June 20, 2008 IR3523 PARAMETER TEST CONDITION MIN TYP MAX UNIT 1.85 1.39 100 -25 1.95 1.47 125 3 2.05 1.55 150 25 V V mV mV 1.87 1.93 1.99 V 1.24 1.33 1.37 V 25 50 75 mV 90 180 ns 1.2 0.2 V V 150 300 ns 5 15 Ω Over Voltage Protection (OVP) Comparators Threshold at Power-up (Output 2) Threshold at Power-up (Output 1) Voutx Threshold Voltage OVP Release Voltage during Normal Operation Threshold during Dynamic VID down (Output 2) Threshold during Dynamic VID down (Output 1) Dynamic VID Detect Comparator Threshold Propagation Delay to IIN OVP High Voltage OVP Power-up High Voltage Propagation Delay to OVP Compare to V(VDACx) Compare to V(VDACx) Note 1 Measure time from V(Voutx) > V(VDACx) (250mV overdrive) to V(IINx) transition to > 0.9 * V(VCCL). Measure V(VCCL)-V(ROSC/OVP) V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP) Measure time from V(Voutx) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. 0 0 IIN Pull-up Resistance Over-Current Comparators Input Offset Voltage 1V ≤ V(OCSETx) ≤ 3.3V -35 0 35 mV -5% Vrosc(V)*1000/ Rosc(KΩ) +5% µA 11.3 16 23.1 kΩ 14.4 20 29.1 kΩ 150 200 250 mV 35 60 85 mV 86.5 89.0 91.5 % 0.36 0.40 0.44 V V(Voutx) = 100mV 200 500 700 uA 1.2 0 30 93.5 85.0 8.25 1.25 1 Compare to V(VCCL) Compare to V(VCCL) Compare to V(VCCL) 1.15 -1 10 89.0 81.0 7.0 97.0 89.0 9.5 V uA mA % % % 4 10 15 mA OCSET Bias Current 2048-4096 Count Threshold 1024-2048 Count Threshold Adjust ROSC value to find threshold Note 1 Adjust ROSC value to find threshold Note 1 Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents V(Voutx) < [V(VOSEN+) – V(LGND)] / 2 Compare to V(VCCL) VCCL Regulator Amplifier Reference Feedback Voltage VCCLFB Bias Current VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis General VCCL Supply Current Note 1: Guaranteed by design, but not tested in production Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offsets Page 7 of 37 June 20, 2008 IR3523 PHSOUT FREQUENCY VS RROSC CHART PHSOUT FREQUENCY vs. RROSC 1600 1500 1400 1300 Frequency (KHz) 1200 1100 1000 900 800 700 600 500 400 300 200 5 10 15 20 25 30 35 40 45 50 55 RROSC (KOhm) Figure 2 - PHSout Frequency vs. RROSC chart Page 8 of 37 June 20, 2008 IR3523 IR3523 block diagram ENABLE2 250nS BLANKING + ENABLE COMPARATOR 1.65V 1.0V PG2 ENABLE1 - 250nS BLANKING ENABLE + COMPARATOR 1.65V 1.0V UV2 SSCLF2 DLY OUT2 VCCLDRV UV1 DLY OUT1 OVLATCH PG1 400k 400k OV1_2 VCCL REGULATOR AMPLIFIER S Q SS/DEL CLEARED FAULT LATCH1 SET DOMINANT + R - SS/DEL CLEARED FAULT LATCH2 0.94 0.86 1.2V INTERNAL DIS CIRCUIT BIAS VCCL UVLO OC1 AFTER VRRDY OC1 Bf VRRDY Q S SET DOMINANT R VCCL UVLO OC2 AFTER VRRDY OC2 Bf VRRDY + - VCCL UVL COMPARATOR S Q SET DOMINANT DIS OC DELAY COUTERDIS R 80mV 120mV DIS DELAY COMPARATOR + TBS OV OPEN SENSE1 OPEN CONTROL1 R S Q SET DOMINANT OPEN SENSE2 OPEN CONTROL2 POWER-UP OK LATCH PHSOUT DIS OC DELAY IROSC DLY OUT2 COUTER DIS DIS S Q RESET DOMINANT - DISCHARGE COMPARATOR R 80mV DELAY COMPARATOR 120mV POWER-UP OK LATCH PHSOUT IROSC DLY OUT1 Q S RESET DOMINANT Q reset 3.9V DISCHARGE COMPARATOR R - SSCLF1 + ICHG 50uA 0.2V Q reset SS/DEL1 - SSCLF2 FLT1 + ICHG 50uA 0.2V FLT2 IDCHG 4.5uA OV1 PHSOUT DCHG2 DIS 47uA - 8 Pulse Delay DIS OC LIMIT COMPARATOR IDCHG2 DIS IROSC OC LIMIT COMPARATOR IIN2 IOCSET 0.3V OV1_2 + - 1.4V SOFT START CLAMP + + VDAC2 IROSC OV2 OV1 PG2 - 275mV 315mV PG1 - OVER VOLTAGE COMPARATOR OV2 1.8V DYNAMIC VID2 DOWN DETECT COMPARATOR - VDAC2 - + + OV2 50mV + DYNAMIC VID1 DOWN DETECT COMPARATOR OV1 DETECTION PULSE1 25k VOSEN2+ 60mV + - REMOTE SENSE AMPLIFIER + IVOSEN- 25k 200mV - DETECTION PULSE2 - IVOSENVCCL DETECTION PULSE1 + 4 OPEN SENSE LINE DETECT COMPARATORS 4 OPEN SENSE LINE DETECT COMPARATORS VCCL RESET VCCL*0.9 + OPEN SENSE LINE1 + 0.4V - 200mV + VCCL RESET VCCL*0.9 VIDSEL VCCL VIDSEL VCCL VOSEN1IVOSEN1- IVOSEN1+ - VCCL 25k - IVOSEN2+ VOSEN1+ 25k REMOTE SENSE AMPLIFIER + IVOSEN2- 25k 60mV - 25k VOSEN2- VOUT1 25k 50mV 25k + VOUT2 UV1 + - - 1.2V VOUT1 UV COMPARATOR + UV2 VDAC1 OVER VOLTAGE COMPARATOR 125mV 275mV 315mV IFB 125mV + VOUT2 UV COMPARATOR FB1 DLY OUT1 OV1 SOFT START CLAMP + ERROR AMPLIFIER FB2 EAOUT1 ERROR AMPLIFIER - FLT2 DLY OUT2 VDAC1 + IROSC 1.4V EAOUT2 DISABLE1 FLT1 IOCSET DISABLE2 VCCL - + OPEN CONTROL LOOP COMPARATOR + IIN1 OCSET1 OPEN CONTROL LOOP COMPARATOR + + OCSET2 - VDRP AMPLIFIER - PHSOUT DIS 8 Pulse Delay DIS 0.3V VDRP1 + + OV2 VCCL DCHG1 47uA DIS VCCL IDCHG 4.5uA DIS IDCHG1 SS/DEL2 VCCL VCCL OPEN DAISY Q S SET DOMINANT R UV CLEARED FAULT LATCH2 OV OPEN DAISY UV CLEARED FAULT LATCH1 - VCCLFB + VCCLDRV 0.4V OPEN SENSE LINE2 - - + + + + ISOURCE ISOURCE VDAC1 IROSC VDAC2 IROSC ISINK ISINK - VID2_0 VID0 VID1_4 VID3 1.0V DIGITAL TO ANALOG CONVERTERS INTERNAL VID3 VDAC VID2 VID1 VCCL UVLO VIDSEL DYNAMIC DOWN VID2 PHSIN VID INPUT COMPARATORS (1 of 3 SHOWN) VID1 ROSC BUFFER AMPLIFIER 0.6V PHSOUT VCCL - 1.2V CLKOUT PHSIN PHSOUT VBOOT (1.1V) Q S SET DOMINANT R OV FAULT LATCH 1 SAMPLE DELAY VID1 SAMPLE AND DELAY COMPARATOR SS/DEL1 - 1.0V CLKOUT INTERNAL VID3 VDAC VID2 + - VID0 + 175k CURRENT SOURCE GENERATOR 3.0V Figure 3 – IR3523 BLOCK DIAGRAM Page 9 of 37 LGND - VID1_2 VID2 IROSC VID0 VIDSEL DYNAMIC DOWN VID1 VID1_3 OPEN DAISY FAULT CHAIN + 175k - VID2_1 VID2 + VID3 VID2_2 - VDAC BUFFER AMPLIFIER VDAC BUFFER AMPLIFIER June 20, 2008 ROSC IR3523 SYSTEM SET POINT TEST Converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digital-toanalog converters, Error Amp input offsets, and Remote Sense input offsets. The voltage appearing at the VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are shown in Figures 4A & 4B. IR3523 ERROR AMPLIFIER VDAC BUFFER AMPLIFIER EAOUT1 + - FB1 + "FAST" VDAC ISOURCE VDAC1 OCSET1 ISINK ROCSET - IFB1 IOCSET1 IROSC IROSC RVDAC CVDAC ROSC BUFFER AMPLIFIER 1.2V LGND + CURRENT SOURCE GENERATOR IROSC ROSC RROSC2 VOUT1 EAOUT SYSTEM SET POINT VOSNSVOLTAGE REMOTE SENSE AMPLIFIER VOSEN1+ + VOSEN1- - Figure 4A - Output 1 System Set Point Test Circuit IR3523 ERROR AMPLIFIER VDAC BUFFER AMPLIFIER EAOUT2 + - FB2 + ISOURCE "FAST" VDAC VDAC2 OCSET2 ISINK ROCSET3 - IOCSET1 IROSC RVDAC3 CVDAC3 CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER 1.2V LGND + IROSC ROSC RROSC3 VOUT2 REMOTE SENSE AMPLIFIER VOSEN2+ EAOUT SYSTEM SET POINT VOSNSVOLTAGE VOSEN2- + - Figure 4B - Output 2 System Set Point Test Circuit Page 10 of 37 June 20, 2008 IR3523 SYSTEM THEORY OF OPERATION PWM Control Method TM The PWM block diagram of the xPHASE3 architecture is shown in Figure 5. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp slope will change with the input voltage automatically compensating for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. GATE DRIVE VOLTAGE VIN IR3523 CONTROL IC PHASE IC PHSOUT CLOCK GENERATOR CLKOUT VCC CLKIN VCCH CLK Q PWM LATCH D PHSOUT PHSIN GATEH VOSNS1+ SW RESET DOMINANT VOUT1 COUT - EAIN R VCCL + GND GATEL ENABLE REMOTE SENSE AMPLIFIER CBST S PWM COMPARATOR PHSIN + + VID6 - - RAMP DISCHARGE CLAMP VOUT1 BODY BRAKING COMPARATOR + PGND VOSNS1- - VDAC1 SHARE ADJUST ERROR AMPLIFIER LGND ERROR AMPLIFIER + VDAC CURRENT SENSE AMPLIFIER + EAOUT1 + ISHARE - - - 3K RCP1 VID6 VID6 + CCP12 RFB12 RFB11 FB1 IROSC VDRP1 AMP CFB1 CDRP1 + CSIN- DACIN RDRP1 VDRP1 - PHASE IC PHSOUT VCC CLKIN CLK Q Output 1 Only CCS RCS - + CCP11 IFB1 CSIN+ + VID6 VID6 + IIN1 VCCH PWM LATCH D PHSIN GATEH CBST S PWM COMPARATOR - EAIN SW RESET DOMINANT R VCCL + GATEL ENABLE + VID6 - RAMP DISCHARGE CLAMP BODY BRAKING COMPARATOR + PGND - SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER + ISHARE - 3K - VID6 VID6 + CSIN+ + VID6 VID6 + + CCS RCS - CSIN- DACIN Figure 5 - PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and the system clock frequency is programmable from 500kHz to 9MHZ by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 6 shows the phase timing for a four phase converter. Page 11 of 37 June 20, 2008 IR3523 Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 6 - Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the non-overlap time. When the PWMRMP voltage exceeds the error amplifier’s output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the ramp discharge clamp, which quickly discharges the PWMRMP capacitor to the output voltage of share adjust amplifier in phase IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 7 depicts PWM operating waveforms under various conditions. Page 12 of 37 June 20, 2008 IR3523 PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID FAULT) STEADY-STATE OPERATION Figure 7 - PWM Operating Waveforms Body Braking TM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the VDAC voltage or a programmable voltage, this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 8. The equation of the sensing network is, vC ( s ) = vL ( s ) 1 RL + sL = iL ( s ) 1 + sRCS CCS 1 + sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 13 of 37 June 20, 2008 IR3523 vL iL Current Sense Amp L RL RCS CCS VO CO c vCS CSOUT Figure 8 - Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 8. Its gain is nominally 34 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning and current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. Page 14 of 37 June 20, 2008 IR3523 IR3523 THEORY OF OPERATION Block Diagram The Block diagram of the IR3523 is shown in Figure 3, and specific features are discussed in the following sections. All the features are described using one output but suitable for both unless otherwise specified. VIDx Control The IR3523 converter outputs are independently controlled by two three-bit input interfaces (see Table 1-2): VDAC1 (VOUT1) and VDAC2 (VOUT2). The VID codes are stored and then inputted to the Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. VDAC1 will initially boot to 1.1V when Vout1 is enabled then will transition to the stored VID1 value once SS/DEL1 reached 3.0 V. The VDAC voltage, input offsets of error amplifier and remote sense differential amplifier, are postpackage trimmed to provide 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system accuracy, which has a wider tolerance. The VID pins, VID2_x and VID1_x, require an external bias voltage and should not be floated. The IR3523 can accept changes in the VID code while operating and vary DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate of the voltage at the VDAC pins can be adjusted by the external capacitors between VDAC pins and LGND pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifiers. The stepped VID transition results in a smooth analog transition of the VDAC voltage and converter output voltage. This analog transition minimizes inrush currents in the input (and output) capacitors and reduces overshoot of the output voltage. VID1_4 0 0 0 0 1 1 1 1 VID1_3 0 0 1 1 0 0 1 1 VID1_2 0 1 0 1 0 1 0 1 VDAC1 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 Table 1: Output (1) 3-bit VID table VID2_2 0 0 0 0 1 1 1 1 VID2_1 0 0 1 1 0 0 1 1 VID2_0 0 1 0 1 0 1 0 1 VDAC2 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.800 Table 2: Output (2) 3-bit VID table Page 15 of 37 June 20, 2008 IR3523 Output 1 (Vtt) Adaptive Voltage Positioning Adaptive Voltage Positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load at heavy load. IR3523 only provides AVP on output1. The circuitry related to the voltage positioning is shown in Figure 9. Resistor RFB1 is connected between the error amplifier’s inverting input pin FB1 and the remote sense differential amplifier output. An internal current source whose value is programmed by the same external resistor that programs the oscillator frequency sinks current from the FB1 pin. The error amplifier forces the converter’s output voltage higher to maintain a balance at its inputs. RFB1 is selected to program the desired amount of fixed offset voltage above the DAC voltage. The VDRP1 pin voltage is a buffered reproduction of the IIN1 pin which is connected to the current share bus ISHARE. The voltage on ISHARE represents the system average inductor current information. At each phase IC, an RC network across the inductor provides current information which is gained up 32.5X and then added to the VDACX voltage. This phase current information is provided on the ISHARE bus via a 3K resistor in the phase ICs. The VDRP1 pin is connected to the FB1 pin through the resistor RDRP1. Since the error amplifier will force the loop to maintain FB1 to be equal to the VDAC1 reference voltage, an additional current will flow into the FB1 pin equal to (VDRP1-VDAC1) / RDRP1. When the load current increases, the adaptive positioning voltage increases accordingly. More current flows through the feedback resistor RFB1, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP1 so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to VDAC1 and therefore independent of the VDAC1 voltage. Control IC VDAC1 Phase IC VDAC1 Current Sense Amplifier CSIN+ - VDAC + EAOUT1 3k + ISHARE Error Amplifier CSIN- RDRP1 Phase IC VDRP1 Current Sense Amplifier + ISHARE VOUT1 VDAC + VOSEN1+ - Remote Sense Amplifier IIN1 VOSEN1- 3k CSIN+ - - + VDRP Amplifier ... ... RFB1 FB1 IFB CSIN- Figure 9 - Adaptive voltage positioning Page 16 of 37 June 20, 2008 IR3523 Output1 Inductor DCR Temperature Compensation A negative temperature coefficient (NTC) thermistor can be used for Output1 inductor DCR temperature compensation. The thermistor should be placed close to the Output1 inductors and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. Control IC VDAC1 VDAC1 Error Amplifier + EAOUT1 IFB FB1 VDRP Amplifier + RFB11 RFB12 Rt RDRP1 VDRP1 IIN1 VOUT1 + VOSEN1+ - Remote Sense Amplifier VOSEN1- Figure 10 - Temperature compensation of Output1 inductor DCR Remote Voltage Sensing VOSENX+ and VOSENX- are used for remote sensing and connected directly to the load. The remote sense differential amplifiers with high speed, low input offset, and low input bias current ensure accurate voltage sensing and fast transient response. Start-up Sequence The IR3523 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DELx and LGND pins controls soft start timing, over-current protection delay and hiccup mode timing. A charge current of 50uA and discharge currents of 47uA and 4.5uA control the up slope and down slope of the voltage at the SS/DEL pin respectively. Page 17 of 37 June 20, 2008 IR3523 Figure 11 depicts the start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DELx pins will start charging, the VID codes are read and stored. VDAC2 transitions to the stored VID code, while VDAC1 transitions to a 1.1V internal boot voltage. The error amplifier output EAOUTx is clamped low until SS/DELx reaches 1.4 V. The error amplifier will then regulate the converter’s output voltage to match the SS/DELx voltage less the 1.4 V offset until the converter VOUT2 reaches programmed VID code and VOUT1 reaches 1.1V (boot voltage). When SS/DEL1 reaches 3.0 V, VDAC1 will transition to the stored VID1 code shifting VOUT1 to the new regulation value. The SS/DELx voltage continues to increase until it rises above the threshold of Delay Comparator (3.93V). The PGx output is then de-asserted (allowed to go high). VCCL under voltage, over current, and a low signal on the ENABLE input immediately sets a fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The PGx pins also drives low and SS/DELx begin to discharge until the voltage reaches 0.2 V. If the fault has cleared, the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. Other fault conditions, such as over voltage, open sense lines, and open daisy chain, set different fault latches, which start discharging SS/DELx, pull down EAOUTx voltage and drive PG low. However, the latches can only be reset by cycling VCCL power (see Table 3). If SS/DELx pins are pulled below 0.6V, the converter can be disabled. VCC (12V) ENABLE VID1_x READ & STORE VID On-Hold VID TANSITION VID2_x READ & STORE VID On-Hold VID TRANSITION VIDx set voltage VID2 Voltage 1.1V boot (Vout1) 0.5V 0.5V VID1 Voltage VDACx 4.0V 3.92V 3.0V 1.4V SS/DELx EA2 EA1 VOUT2 (No Vboot) EAOUTx 1.1V Boot (Vout1 ONLY) VOUT1 = VID1 VOUTX PGx START DELAY STARTUP TIME VID ON THE FLY PROCESSION NORMAL OPERATION Shutdown Figure 11 - Start-up Sequence Transition Page 18 of 37 June 20, 2008 IR3523 Over-Current Hiccup Protection after Soft Start The over current limit threshold is set by a resistor connected between OCSETx and VDACx pins. Figure 12 shows the hiccup over-current protection with delay after PGx is asserted. The delay is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions. If the IINx pin voltage, which is proportional to the average current plus VDACx voltage, exceeds the OCSETx voltage after PGx is asserted, it will initiate the discharge of the capacitor at SS/DELx through the discharge current 47uA. If the over-current condition persists long enough for the SS/DELx capacitor to discharge below the 120mV offset of the delay comparator, a fault latch will be set pulling the error amplifier’s output low and inhibiting switching in the phase ICs and de-asserting the PGx signal. The SS/DEL capacitor will then continue to discharge through a 4.7uA discharge current until it reaches 200 mV, and the fault latch is reset allowing a normal soft start to occur. The output current is not controlled during the delay time. If an over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. ENABLE SS/DEL 4.0V 3.92V 3.88V 1.1V EA VOUT VRRDY OCP THRESHOLD IOUT START-UP WITH OUTPUT SHORTED HICCUP OVER-CURRENT PROTECTION (OUTPUT SHORTED) NORMAL START-UP OCP DELAY OVER-CURRENT NORMAL NORMAL PROTECTION START-UP OPERATION POWER-DOWN (OUTPUT SHORTED) (OUTPUT NORMAL OPERATION SHORTED) Figure 12 - Hiccup over-current waveforms Linear Regulator Output (VCCL) The IR3523 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by the resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a function of the number of phases used in the multiphase architecture and their switching frequency. Figure 13 shows the stability plots for the linear regulator with 5 phases switching at 750 kHz. Page 19 of 37 June 20, 2008 IR3523 Figure 13 - VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz VCCL Under Voltage Lockout (UVLO) The IR3523 has no under voltage lockout protection for the converter input voltage (VCC), but monitors the VCCL voltage instead. The VCCL is used to power both the control IC and phase ICs including the phase ICs internal gate drivers. During power up, the UVLO fault latch will be reset if VCCL is above 94% of the voltage set by resistor divider at VCCLFB pin. If VCCL voltage drops below 86% of the set value, the UVLO fault latch will be set. Power Good (PG1, 2) The PGx pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start, the PGx remains low until the output voltage is in regulation and SS/DELx is above 3.93V. The PGx pin becomes low if any of the fault latches are triggered (See Table 3). PGx monitors the output voltage. If any of the voltage planes fall out of regulation, PGx will become low, but the VR will continue to attempt to regulate the output voltages. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage. VID on-the-fly transition, which is a voltage plane transitioning between two different VID codes, is not considered to be out of specification. A high level at the PGx pins indicates that the converter is in operation with no fault and ensures the output voltage is within the regulation. The PG outputs derive power from either VCCL or VCCLDRV to ensure they can assert with input voltage as low as possible. Open Control Loop Detection The error amplifier’s output voltage is monitored to ensure the control loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08 V for 8 switching cycles, the Open Control Loop fault latch is set. This fault latch can only be cleared by cycling power to VCCL. Load Current Indicator Output The VDRP pin voltage represents the average current of the converter plus the VDAC1 voltage. The load current information can be retrieved by using a differential amplifier to subtracts the VDAC1 voltage from the VDRP1 voltage. Page 20 of 37 June 20, 2008 IR3523 Enable Input Pulling the ENABLE pin below 1.0 V sets the Fault Latch. Forcing ENABLE to a voltage above 1.65V results in the 3-bit VID codes to be read and stored. SS/DELX pins are also allowed to begin their power-up cycles as long as no fault conditions are present. Over Voltage Protection (OVP) Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is compromised. If the over-voltage protection comparators sense that either VOUTX pin voltage exceeds VDACX by 125mV, the over voltage fault latch is set which pulls the error amplifier output low turning off both converters power stage. The IR3523 communicates an OVP condition to the system by raising the ROSC pin voltage to within V(VCCL) – 1.2 V. An OVP condition is also communicated to the phase ICs by forcing the IIN pin (which is tied to the ISHARE bus and ISHARE pins of the phase ICs) to VCCL as shown in Figure 14. In each phase IC, the OVP circuit overrides the normal PWM operation to ensure the low side MOSFET turn-on within approximately 130ns. The low side MOSFET will remain on until the ISHARE pins fall below V(VCCL) - 800mV. An over voltage fault condition is latched in the IR3523 and can only be cleared by cycling the power to VCCL. During dynamic VID down at light to no load, false OVP triggering is prevented by increasing the OVP threshold to a fixed 1.2 V (VOUT1) and 1.8 V (VOUT2) whenever a dynamic VID is detected and the difference between output voltage and the fast internal VDAC is more than 50mV, as shown in Figure 15. The over-voltage threshold is changed back to VDAC+125mV if the difference between output voltage and the fast internal VDAC is less than 50mV. The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible, a fuse can be added in the input supply to the multiphase converter. OUTPUT VOLTAGE (Vout) OVP THRESHOLD VCCL-800 mV IIN (PHASE IC ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER OUTPUT (EAOUT) VDAC NORMAL OPERATION OVP CONDITION AFTER OVP Figure 14 - Over-voltage protection during normal operation Page 21 of 37 June 20, 2008 IR3523 VID VDAC 1.73V OV THRESHOLD VDAC + 130mV OUTPUT VOLTAGE (VO) VDAC 50mV 50mV NORMAL OPERATION VID DOWN LOW VID VID UP NORMAL OPERATION Figure 15 - Over-voltage protection during dynamic VID Open Remote Sense Line Protection If either remote sense line VOSENX+ or VOSENX- is open, the output of Remote Sense Amplifier (VOUTX) drops. The IR3523 continuously monitors the VOUTX pin and if VOUTX is lower than 200 mV, two separate pulse currents are applied to the VOSENX+ and VOSENX- pins to check if the sense lines are open. If VOSENX+ is open, a voltage higher than 90% of V(VCCL) will be present at VOSENX+ pin and the output of Open Line Detect Comparator will be high. If VOSENX- is open, a voltage higher than 400mV will be present at VOSENX- pin and the Open Line Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to force the error amplifier output low and immediately shut down the converter. SS/DELX will be discharged and the Open Sense Fault Latch can only be reset by cycling the power to VCCL. Open Daisy Chain Protection IR3523 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If the pulse fails to come back the second time, the open daisy chain fault is registered, and SS/DEL is not allowed to charge. The fault latch can only be reset by cycling the power to VCCL. After powering up, the IR3523 monitors PHSIN pin for a phase input pulse equal or less than the number of phases detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault is registered. Phase Number Determination After a daisy chain pulse is started, the IR3523 checks the timing of the input pulse at PHSIN pin to determine the phase number. Page 22 of 37 June 20, 2008 IR3523 The Fault Table below describes ten different faults that can occur during normal operation and how the IR3523 IC will react to protect the supply and the load from possible damage. The fault types that can occur are listed in row one. Row two and three describes the type and the method of clearing the faults, respectively. The first four faults are latched in the UV fault and require the VCCL supply to be recycled (below UVLO threshold) to regain operation. The rest of the faults, except for UVLO Vout, are latched in a SS fault which do not need VCCL supply recycled, but instead will automatically resume operation when these fault conditions are no longer impinging on the system. Most of the faults will disable the error amplifier (EA) and discharge the soft start capacitor. All of the faults flag PGood. PGood returns to high impedance state (high) when the fault clears. The Delay row shows reaction time after detecting a fault condition. Delays are provided to minimize the possibility of nuisance faults. Additional flagged responses are used to communicate externally of a fault event (Over Voltage) so additional action can be taken. System Fault Table Fault Type Latch Fault Clearing Method Outputs Affected Error Amp Disables SS/DELx Discharge Flags PGood Delays Open Daisy Open Sense Open Control UV Latch Over Voltage Disable Recycle VCCL Both Single UVLO OC (VCCL) Before SS Latch OC After SS discharge below 0.2V Both Both Both UVLO (Vout) No No Single Single Yes No Yes No Yes 32 Clock Pulses No 8 PHSOUT Pulses No 250ns Blanking Time Yes, Additional IINx and Rosc pins Flagged No pulled-up to VCCL** Response * Pulse number range depends on Rosc value selected (See Specifications Table) ** Clears when OV condition ends No PHSOUT Pulses* SS/DELx Discharge Threshold No Table 3 - IR3523 system fault responses Page 23 of 37 June 20, 2008 No IR3523 APPLICATIONS INFORMATION P12V_DDR3_FILTED Q16 VCCL C131 R55 R54 C135 C136 R56 C379 NC2 13 1 2 6 7 VCC GATEL PGND VCCL 12 Q27 VTT_SEN+ 5 VTT_SEN+ 1 2 3 6 4 7 11 10 C186 1 2 VTT+ L30 9 Q28 C187 5 C188 R100 COUT 3 4 CSIN+ 15 14 SW VCCL 8 25 24 CSIN- 16 PHSIN 26 C182 C244 IR3505 PHASE GATEH BOOST IC CLKIN R67 4 PHSOUT 27 VTT_VRRDY LGND 7 28 VTT- C138 C374 R69 23 VTT_SEN- VTT_SEN- 22 R71 VDAC_VTT 21 41 No Stuf f C142 R72 R73 R78 R77 C381 DACIN 3 6 EAIN PAD ISHARE 2 VDAC_VTT 29 20 FB1 VOUT1 VOSEN1+ EAOUT1 19 18 EAOUT2 1 30 5 CLKOUT 31 32 33 34 VCCL PHSIN PHSOUT 37 38 39 35 VCCLFB VCCLDRV PG2 OCSET1 11 C380 R75 VID2_0 VDAC1 OCSET2 17 10 IIN1 SS/DEL1 VDAC2 NC1 R70 VDRP1 SS/DEL2 VOSEN1- 9 VDAC_VDDR3 IIN2 16 8 ROSC/OVP IR3523 CONTROL IC ENABLE1 VOSEN2- 7 ENABLE2 15 R68 PG1 WOSEN2+ C378 VID1_2 14 6 C137 C139 VID2_1 40 5 ENABLE_VTT R66 NC3 LGND VOUT2 4 ENABLE_DDR3 P12V_CPU_FILTED U71 VID1_3 FB2 3 VID1_4 13 2 12 1 VID2_2 U1 VID_VTT_4 VID_VTT_3 VID_VTT_2 36 R65 VDDR3_VRRDY VID_DDR3_0 VID_DDR3_1 VID_DDR3_2 R76 P12V_DDR3_FILTED C377 C376 EA_VDDR3 R244 C192 C375 R80 R243 EA_VDDR3 1 2 6 7 VCC 16 DACIN LGND PHSIN GATEH BOOST VCCL NC2 15 Q30 14 C194 R92 VTT_SEN+ 5 13 12 VCCL VDDR3_SEN+ L24 3 4 19 17 18 CSIN- SW IR3508 PHASE IC PSI 1 2 VDDR3+ C189 11 C191 Q29 COUT 5 10 9 8 7 6 3 4 NC1 5 IOUT 1 2 6 7 4 C193 GATEL 3 PGND 2 PSI_PH5 VDAC_VDDR3 CLKIN 1 VDDR3_SEN- PHSOUT VDDR3_SEN+ CSIN+ VTT_SEN- EAIN NC3 U74 20 C197 VTT_SEN+ VDDR3VTT_SEN- VDDR3_SEN- P12V_DDR3_FILTED EA_VDDR3 LGND 1 2 6 7 BOOST VCCL NC2 15 Q32 14 12 C203 R93 5 13 L25 3 4 17 16 VCC CSIN- CSIN+ 18 19 PHSIN GATEH VCCL 1 2 1 2 6 7 DACIN C198 11 C200 Q31 5 10 9 8 7 6 3 4 NC1 5 SW IR3508 PHASE IC PSI GATEL 4 C202 IOUT PGND 3 CLKIN 2 PHSOUT 1 PSI_PH5 VDAC_VDDR3 EAIN NC3 20 C205 U79 P12V_DDR3_FILTED C210 EA_VDDR3 LGND PHSIN 1 2 6 7 VCC BOOST VCCL 12 C212 R94 5 13 L27 VCCL 1 2 C207 11 C209 Q33 5 17 10 9 8 7 6 3 4 NC2 Q34 14 3 4 CSIN- 19 18 16 GATEH 15 1 2 6 7 DACIN NC1 5 SW IR3508 PHASE IC PSI GATEL 4 C211 IOUT PGND 3 CLKIN VDAC_VDDR3 2 CSIN+ NC3 PSI_PH5 PHSOUT 1 EAIN 20 C214 U80 Figure 16 - IR3523 \ IR3508 Three Phases VDDR3 and a Single Phase (IR3505) Vtt One Phase Converter Page 24 of 37 June 20, 2008 IR3523 DESIGN PROCEDURES - IR3523 AND IR3505 CHIPSET IR3523 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor Rosc The IR3523 generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor RROSC, use Figure 2 to determine the RROSC value. The CLKOUT frequency equals the switching frequency multiplied by the phase number. Soft Start Capacitor CSS/DEL The Soft Start capacitor CSS/DEL programs four different time parameters, soft start delay time, soft start time, PGx delay time and over-current fault latch delay time after PGx. SS/DELx pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. Once the ENABLE pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V. Once SS/DEL reaches 1.4V, the error amplifier output is released to allow the soft start. The soft start time, TD2, represents the time during which converter voltage rises from zero to VID2 or VOUT1’s boot voltage (1.1V). The SS/DELx pins voltage rises from 1.4V to VID2 (or VOUT1 boot) plus 1.4V. Power good delay time, TD3, is the time period from between where VR reaches the VID voltage and PGx signal assertion. Calculate CSS/DEL based on the required soft start time TD2. C SS / DEL = TD 2 * I CHG TD 2 * 50 * 10 −6 = VID VID (1) The soft start delay time TD1 and VR ready delay time TD3 are determined by equation (2) and (3) respectively. TD1 = C SS / DEL * 1.4 C SS / DEL * 1.4 = I CHG 50 * 10 −6 TD3 = C SS / DEL * (3.93 − VID − 1.4) C SS / DEL * (3.93 − VID − 1.4) = I CHG 50 * 10 − 6 (2) (3) Once CSS/DEL is chosen, use equation (4) to calculate the maximum over-current fault latch delay time tOCDEL. t OCDEL = 2.5 ∗ C SS / DEL * 0.12 C * 0.12 = 2.5 ∗ SS / DEL −6 I DISCHG 47 * 10 (4) Due to the exponential turn-on slope of the discharge current (47uA), a correction factor (X2.5) is added to the equation (4) to accurately predict over-current delay time. Page 25 of 37 June 20, 2008 IR3523 VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC The slew rate of VDACx down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in (5), where ISINK is the sink current of VDAC pin. The slew rate of VDAC up-slope is three times greater that of down-slope. The resistor RVDAC is used to compensate VDAC circuit and is determined by (6). CVDAC = I SINK SR DOWN RVDAC = 0.5 + 3.2 ∗ 10 −15 CVDAC 2 (5) (6) Over Current Setting Resistor ROCSET The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (7), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature TL_ROOM respectively. RL _ MAX = RL _ ROOM ∗ [1 + 3850 *10−6 ∗ (TL _ MAX − TL _ ROOM )] (7) The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset (VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current sense resistor RCS. VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS (8) The over current limit is set by the external resistor ROCSET as defined in (9). ILIMIT is the required over current limit. IOCSET is the bias current of OCSET pin and can be calculated with the equation in the ELECTRICAL CHARACTERISTICS Table. GCS is the gain of the current sense amplifier. KP is the ratio of inductor peak current over average current in each phase and can be calculated from (10). ROCSET = [ KP = I LIMIT ∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET n (VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2) IO / n (9) (10) VCCL Programming Resistor RVCCLFB1 and RVCCLFB2 Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor divider. Pre-select RVCCLFB1, and calculate RVCCLFB2 from (11). RVCCLFB 2 = Page 26 of 37 RVCCLFB1 *1.23 VCCL − 1.23 (11) June 20, 2008 IR3523 No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Define RFB_R is the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the offset voltage VO_NLOFST above the DAC voltage, calculate the sink current from the FB1 pin IFB1 using the equation in the ELECTRICAL CHARACTERISTICS Table, then the effective offset resistor value RFB1 can be determined from (12). RFB _ R = VO _ NLOFST (12) I FB1 Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP, RDRP11 = RFB _ R ∗ RL _ ROOM * GCS (13) n ∗ RO Calculate the desired effective feedback resistor at the maximum temperature RFB_M using (14) RFB _ M = RDRP11 ∗ RO * n GCS ∗ RL _ MAX (14) A negative temperature constant (NTC) thermistor RTHERM1 is required to sense the temperature of the power stage for the inductor DCR thermal compensation. Pre-select the value of RTHERM. RTHERM must be bigger than RFB_R at room temperature but also bigger than RFB_M at the maximum allowed temperature. RTMAX1 is defined as the NTC thermistor resistance at maximum allowed temperature, TMAX. RTMAX1 is calculated from (15). RTMAX 1 = RTHERM 1 * EXP[ BTHERM 1 * ( 1 TL _ MAX − 1 T _ ROOM (15) )] Select the series resistor RFB13 by using equation (16). RFB13 is incorporated to linearize the NTC thermistor which has non-linear characteristics in the operational temperature range. R FB 13 = ( RTHERM 1 + RTMAX 1 ) 2 − 4 * ( RTHERM 1 * RTMAX 1 − ( RTHERM 1 − RTMAX 1 ) * R FB _ R * R FB _ M /( R FB _ R − R FB _ M )) − ( RTHERM 1 + TTMAX 1 ) 2 Use equation (17) to determine RFB11. 1 RFB11 Page 27 of 37 = 1 RFB _ R − 1 RFB13 + RTHERM 1 (17) June 20, 2008 (16) IR3523 VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. The selection of compensation types depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown in Figure (a) is usually enough. While for the applications using only ceramic capacitors and running at higher frequency, type III compensation shown in Figure 21(b) is preferred. For applications where AVP is not required, the compensation is the same as for the regular voltage mode control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type III compensation is required as shown in Figure 21(b) with RDRP and CDRP removed. CCP1 CCP1 RFB RCP CCP VO+ RCP CCP RFB1 CFB FB - RFB VO+ FB EAOUT - RDRP EAOUT RDRP VDAC VDRP + (a) Type II compensation EAOUT VDAC VDRP EAOUT + CDRP (b) Type III compensation Figure 17 - Voltage loop compensation network Type II Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine RCP and CCP from (23) and (24), where LE and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. (2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ 5 (23) RCP = VI * 1 + ( 2π * fC * C * RC ) 2 CCP = 10 ∗ LE ∗ C E RCP (24) CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Page 28 of 37 June 20, 2008 IR3523 Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (25) and (26), where RLE is the equivalent resistance of inductor DCR. f C1 = RDRP 2π * CE ∗ GCS * RFB ∗ RLE θ C1 = 90 − A tan(0.5) ∗ (25) 180 (26) π Choose the desired crossover frequency fc around fc1 estimated by (25) or choose fc between 1/10 and 1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB /Dec around the crossover frequency. Choose resistor RFB1 according to (27), and determine CFB and CDRP from (28) and (29). 1 R FB 2 R FB1 = CFB = R FB1 = to 2 R FB 3 1 (28) 4π ∗ fC ∗ RFB1 C DRP = (27) ( R FB + R FB1 ) ∗ C FB R DRP (29) RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Determine RCP and CCP from (30) and (31). RCP = CCP = (2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ 5 VI 10 ∗ LE ∗ C E (30) (31) RCP CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Type III Compensation for Non-AVP Applications Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin θc. Calculate K factor from (32), and determine the component values based on (33) to (37), π θ K = tan[ ∗ ( C + 1.5)] 4 180 RCP = RFB ∗ ( 2π ∗ LE ∗ CE ∗ fC ) 2 ∗ 5 VI ∗ K (32) (33) CCP = K 2π ∗ fC ∗ RCP (34) CCP1 = 1 2π ∗ fC ∗ K ∗ RCP (35) Page 29 of 37 June 20, 2008 IR3523 CFB = R FB1 = K 2π ∗ fC ∗ RFB 1 2π ∗ f C ∗ K ∗ C FB (36) (37) CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. DESIGN EXAMPLE – THREE PHASE (DDR) AND ONE PHASE (VTT) CONVERTER (FIGURE 16) SPECIFICATIONS: Input Voltage: VI = 12 V DAC1 Voltage: VDAC1 = 1.22 V DAC2 Voltage: VDAC2 = 1.5 V No Load Output Voltage Offset for output1: VO_NLOFST = 20 mV Output1 Current: IO1 = 28A DC Output2 Current: IO2 = 85A DC Output1 Over Current Limit: Ilimit1 =42A DC Output2 Over Current Limit: Ilimit2 = 125A DC Output1 Impedance: RO1 = 6.0 mΩ Dynamic VID Slew Rate Rise: SR = 3.25mV/uS Over Temperature Threshold: TMAX = 110 ºC POWER STAGE: Phase Number: n1 = 1, n2 = 3 Switching Frequency: fSW = 750 kHz Output Inductors: L1 = 150 nH, L2 = 90nH, RL1 = 0.47mΩ, RL2 = 0.47mΩ Output Capacitors: Ceramics, C = 22uF, RC = 1.5 mΩ, Number Cn1 = 15, Cn2 = 6 Output Capacitors: Ceramics, C = 10uF, RC = 1 mΩ, Number Cn1 = 0, Cn2 = 70 (10 per DIMM) Oscillator Resistor RROSC Once the switching frequency is chosen, RROSC can be determined from Figure 2. For switching frequency of 750 kHz per phase, choose ROSC = 15.8 kΩ. Page 30 of 37 June 20, 2008 IR3523 Soft Start Capacitor CSS/DEL Determine the soft start capacitor from the required soft start time. TD 2 * I CHG 2 * 10 −3 * 50 * 10 −6 = = 0.1uF Vboot 1.1 TD 2 * I CHG 2 * 10 −3 * 50 * 10 −6 C SS / DEL 2 = = = 0.1uF VID 2 1.5 C SS / DEL 1 = The soft start delay time is TD1 = C SS / DEL * 1.4 0.1 * 10 −6 * 1.4 = = 2.8mS I CHG 50 * 10 −6 The power good delay time is C SS / DEL1 * (3.93 − Vboot − 1.4) 0.1 * 10 −6 * (3.93 − 1.1 − 1.4) TD3(1) = = = 2.9mS I CHG 50 * 10 − 6 TD3( 2) = C SS / DEL 2 * (3.92 − VID 2 − 1.4) 0.1 * 10 −6 * (3.92 − 1.5 − 1.4) = = 2.0mS I CHG 50 * 10 − 6 The maximum over current fault latch delay time is t OCDEL = 2.5 * C SS / DEL * 0.12 0.1 * 10 −6 * 0.12 = 2.5 * = 0.638mS I DISCHG 47 * 10 −6 VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC CVDAC = I Source 113 ∗ 10 −6 = = 34.7 nF , Choose CVDAC = 33nF SR DOWN 3.25 * 10 3 RVDAC = 0.5 + 3.2 ∗ 10 −15 CVDAC 2 = 3.3Ω Over Current Setting Resistor ROCSET The output1 over current limit is 42A and the output2 over current limit is 125A. The OCSET bias current calculates out to be 38uA with ROSC = 15.8 kΩ (see Electrical Characteristics Table). The total current sense amplifier input offset voltage is typically 0mV. KP, the ratio of inductor peak current over average current in each phase, is calculated with the following equations: (V I − VO ) ∗ VO /( L ∗ V I ∗ f SW ∗ 2) (12 − 1.22) ∗ 1.22 /(150 * 10 −9 ∗ 12 ∗ 750 * 10 3 ∗ 2) K P1 = = = 0.156 I LIMIT / n 42 / 1 KP 2 = (12 − 1.5) ∗ 1.5 /(90 * 10 −9 ∗ 12 ∗ 750 * 10 3 ∗ 2) = 0.23 . 41.6 Page 31 of 37 June 20, 2008 IR3523 The over current set resistor (Rocset) can be calculated as follows: ROCSET 1 = [ =( 42 ∗ 0.52 * 10 − 3 ∗ 1.156 ) * 32.5 /(38 * 10 − 6 ) = 21.6 kΩ , 1 ROCSET 2 = [ =( I LIMIT ∗ R L ∗ (1 + K P ) + VCS _ TOFST ] ∗ G CS / I OCSET , n I LIMIT ∗ RL ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS / I OCSET , n 125 ∗ 0.47 * 10 − 3 ∗ 1.23) * 32.5 /(38 * 10 − 6 ) = 20.6 kΩ . 3 VCCL Programming Resistor RVCCLFB1 and RVCCLFB2 Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kΩ, and calculate RVCCLFB2. RVCCLFB 2 = RVCCLFB1 *1.23 20 *103 *1.23 = = 4.26kΩ VCCL − 1.23 7 − 1.23 No Load Offset Setting Resistor RFB11 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Given the desired offset voltage (VO_NLOFST) and calculating the FB1 sink current using the equation in the ELECTRICAL CHARACTERISTICS Table, the effective offset resistor value RFB11 can be determined by: R FB11 = VO _ NLOFST I FB1 = 20 * 10 −3 = 526Ω = 523Ω (Actual Value). 38 * 10 −6 Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. RDRP11 is calculated with the following equation: R DRP11 = R FB11 ∗ R L _ ROOM * GCS n ∗ RO = 523 * 0.47 * 10 −3 * 32.5 = 1.33KΩ . 1 * 6 * 10 −3 In the case of thermal compensation is required, use equation (14) to (17) to select the RFB network resistors. Page 32 of 37 June 20, 2008 IR3523 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • • • • • • • • Dedicate at least one middle layer for a ground plane LGND. Connect the ground tab under the control IC to LGND plane through a via. Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins. Place the following critical components on the same layer as control IC and position them as close as possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection. Place the compensation components on the same layer as control IC and position them as close as possible to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection. Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes. Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes. Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation components. Page 33 of 37 June 20, 2008 IR3523 PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. • Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. Page 34 of 37 June 20, 2008 IR3523 SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. • The minimum solder resist width is 0.13mm. • At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. • The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. • Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented or plugged from bottom boardside with solder resist. Page 35 of 37 June 20, 2008 IR3523 STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. • The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. • The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. • The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 36 of 37 June 20, 2008 IR3523 PACKAGE INFORMATION O O 40L MLPQ (6 X 6 MM BODY) ΘJA = 18 C/W, ΘJC = 0.5 C/W Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Page 37 of 37 June 20, 2008