IR3548MTRPBF

60A Dual Integrated PowIRstage IR3548 FEATURES DESCRIPTION • Integrated Dual, Doubler or Quad mode Driver • 2 pairs of high and low side MOSFETs • Peak efficiency up to 94% at 1.2V • Variable gate drive, VDRV, from 4.25V to 12V to optimize system efficiency • 5V VCC and VDRV capability for sleep states where only 5V is available • Input voltage (VIN) range of 4.25V to 17V • Output current capability of 30A/phase • Switching frequency up to 1.5MHz • Ultra-low Rg MOSFET technology minimizes switching losses for optimized high frequency performance • Synchronous MOSFET with monolithic integrated Schottky diode reduces dead-time and diode reverse recovery losses • Low quiescent current (1uA typical) VR12.6/VR12.6+ notebook applications. for • Independent enable control for each phase • Support both industry standard 3.3V tri-state PWM and IR Active Tri-Level (ATL) PWM logic • Small 6mm x 8 mm x 0.9mm PQFN package • Lead-free RoHS compliant package APPLICATIONS • High frequency, low profile DC-DC converters • Voltage Regulators for CPUs, GPUs, and DDR memory arrays of servers, notebook. The IR3548 is a dual integrated PowIRstage® is a with 2 pairs of co-packed control and synchronous MOSFETs and an optimized dual phase driver. The package is optimized internally for PCB layout, heat transfer and package inductance. The integrated driver is capable of operating as a Dual driver (2 PWM controlling 2 phases), a Doubler driver (1 PWM controlling 2 phases) or a Quad driver (1 PWM controlling 4 phases in two IR3548s). Up to 1.5MHz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. Integrating two phases in one package while still providing superior efficiency and thermal performance, the IR3548 enables smallest size and lower solution cost. The lower quiescent current makes it suitable for next generation VR12.6/VR12.6+ notebook applications. The IR3548 uses IR’s latest generation of low voltage MOSFET technology characterized by ultra-low gate resistance (Rg) and charge (Qg) that result in minimized switching losses. The synchronous MOSFET optimizes conduction losses and features a monolithic integrated Schottky to significantly reduce dead-time and diode conduction and reverse recovery losses. The IR3548 is optimized specifically for CPU core power delivery in 12Vin applications like servers, certain notebooks, GPU and DR memory designs. ORDERING INFORMATION Base Part Number Package Type IR3548MTRPBF PQFN 6 mm x 8 mm 1 www.irf.com Standard Pack Form Quantity Tape and Reel 3000 © 2014 International Rectifier Orderable Part Number Submit Datasheet Feedback January 08, 2014 IR3548 PINOUT DIAGRAM VIN1 VIN1 PGND PGND GATEL1 SW1 VIN1 SW1 VIN1 SW1 VINDIV SW1 EN1 SW1 PWM1 SW1 VCC SW1 BOOT1 SW1 GATEL1 SW1 LGND SW1 PGND PGND VDRV SW2 GATEL2 SW2 BOOT2 SW2 PWM2 / PWMIO1 SW2 EN2 / PWMIO2 SW2 FUNCTION SW2 MODE SW2 VIN2 SW2 VIN2 SW2 VIN2 VIN2 GATEL2 PGND PGND SW2 Figure 1: IR3548 Top View 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 FUNCTIONAL BLOCK DIAGRAM BOOT1 GATEL1 GATEL1 VIN1 VIN1 VIN1 VIN1 8 7 1 45 2 48 49 35 SW1 VDRV 11 36 SW1 VDRV EN1 Q1 4 VCC or VDRV UVLO LGND VCC 37 SW1 Driver 38 SW1 39 SW1 or T > 150°C 6 40 SW1 41 SW1 VDRV EN1 4 PWM1 Q2 Power-on Reset (POR), 5 42 SW1 Driver 43 SW1 Reference, MODE MODE (PWM or IR ATL), 17 FUNCTION 16 PWM2 / PWMIO1 44 SW1 13 BOOT2 FUNCTION (Dual, Doubler, or Quad), 14 18 VIN2 19 VIN2 20 VIN2 and Q3 Driver Dead-time EN2 / 15 PWMIO2 21 VIN2 Driver 25 SW2 Control 26 SW2 27 SW2 VIN1 VINDIV 3 LGND 9 Q4 VDRV VIN1 14 28 SW2 29 SW2 Driver 30 SW2 31 SW2 32 SW2 IR3548 33 SW2 34 SW2 10 50 12 PGND PGND 23 22 46 47 PGND PGND PGND PGND GATEL2 GATEL2 24 Figure 2: Block Diagram TABLE 1: FUNCTION AND MODE PIN CONFIGURATION TABLE PIN 16 PIN 17 “FUNCTION” “MODE” 0 1 3 PWM Pin 4 Mode “EN1” Function DUAL IR ATL Loop 1 Functionality Pin 14 Function Pin 15 Function PWM2 EN2 1 1 DOUBLER IR ATL Loops 1 & 2 NA NA Float 1 QUAD Master IR ATL Loops 1 & 2 PWMIO1 (output) PWMIO2 (output) 0 0 DUAL Tri-State Loop 1 PWM2 EN2 1 0 DOUBLER Tri-State Loops 1 & 2 NA NA Float 0 QUAD Slave NA Loops 1 & 2 PWMIO1 (input) PWMIO2 (input) www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 TYPICAL APPLICATION IR3588 DTSEN CFLT CRCS 100pF RT 10kΩ VIN1 VIN2 VCC VCC TSEN 5V 3.3V CFLT 1uF C3V3 1uF CVCC 0.1uF IR3548 CIN2 47uF x4 VDRV RCSP CVDRV 1uF SVADDR_1 RCSM SW1 SV_CLK SV_DIO VRHOT_ICRIT# SM_DIO PWM1 PWM1 PSI#1 EN1 PWM2 PWM2 PSI#2 EN2 ISEN1 SM_CLK IRTN1 EN ISEN2 VSEN VRTN IRTN2 + CS1 CBOOT2 0.22uF BOOT2 SW2 RCS2 2.49kΩ GATEL2 GATEL2 LGND L2 150nH CCS2 0.22uF + CS2 - FUNCTION + CS2 - VOUT CCS1 0.22uF GATEL1 MODE + CS1 - RCS1 2.49kΩ GATEL1 VINDIV VINSEN SV_ALERT# L1 150nH COUT 470uF x3 ADDR_PROT VRDY CBOOT1 0.22uF BOOT1 VDRV LGND From / To System VIN CIN1 0.1uF x2 PGND Figure 3: High Density Two-Phase Voltage Regulator, Standard Tri-state PWM, Dual Driver Mode VCC VIN1 VIN2 VCC CVCC 0.1uF VDRV IR3548 VDRV VIN CIN1 0.1uF x2 BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT1 SW1 Two singlephase PWM controllers GATEL1 PWM1 GATEL1 EN1 BOOT2 RCS1 2.49kΩ CBOOT2 0.22uF PWM2 EN2 + CS1 + CS2 - + VOUT1 SENSE VINDIV MODE FUNCTION LGND CCS1 0.22uF COUT1 470uF x3 + CS1 L2 150nH VOUT2 SW2 GATEL2 RCS2 2.49kΩ CCS2 0.22uF COUT2 470uF x3 GATEL2 PGND + CS2 - + VOUT2 SENSE Figure 4: IR3548 Two Single-Phase Voltage Regulators, Standard Tri-state PWM, Dual Driver Mode 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 VCC VDRV VIN VIN1 VCC CVCC 0.1uF CIN1 0.1uF x2 IR3548 VDRV BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT SW1 Single- VINDIV GATEL1 PWM1 GATEL1 CCS1 0.22uF COUT1 470uF x3 + CS1 - EN1 phase PWM RCS1 2.49kΩ BOOT2 PWM2 + CS1 - controller EN2 SW2 MODE + VOUT SENSE - FUNCTION LGND GATEL2 GATEL2 PGND Figure 5: IR3548 Single-phase Voltage Regulator, Standard Tri-state PWM, Dual Driver Mode VCC VIN1 VIN2 VCC CVCC 0.1uF VDRV IR3548 VDRV VIN CIN1 0.1uF x2 BOOT1 CVDRV 1uF CBOOT1 0.22uF CIN2 47uF x4 L1 150nH VOUT SW1 Singlephase VINDIV GATEL1 PWM1 GATEL1 EN1 PWM controller BOOT2 RCS1 4.99kΩ CBOOT2 0.22uF PWM2 + CS12 + VOUT SENSE - EN2 VCC MODE FUNCTION LGND COUT1 470uF x3 L2 150nH SW2 GATEL2 RCS2 4.99kΩ CCS 0.22uF GATEL2 PGND + CS12 - Figure 6: IR3548 Two-Phase Voltage Regulator, Standard Tri-state PWM, Doubler Driver Mode 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1, 2, 48, 49 VIN1 High current input supply pins for Phase 1. Recommended operating range is 4.25V to 17V. Connect at least a 10uF 1206 ceramic capacitor and a 0.1uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN1 pins and PGND pins (46 and 47). The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3548. 3 VINDIV Output containing divided VIN1 analog information, (VIN1-LGND) / 14 with respect to LGND. The internal resistor divider is disconnected from VIN1 when EN1 is low. EN1 Phase 1 ENABLE input in Dual mode and Phases 1 & 2 ENABLE input in Doubler or Quad mode. Grounding this pin places Phase 1 in low quiescent mode as a Dual driver and sets both phases in low quiescent mode as a Doubler or Quad driver. The pin is also used to communicate VDRV UVLO, VCC UVLO or over temperature condition; EN1 is pulsed low under the fault. The pin must be driven high with a pullup resistor or grounded and should not be floated. 5 PWM1 The PWM1 is the control input for the first driver with either an IR ATL compatible signal or an industry standard Tri-State signal. Connect this pin to the PWM output of the controller. As a Dual driver, PWM1 controls gate drivers for Phase 1 (Q1 and Q2), and as a Doubler or Quad driver, PWM1 controls both phases (Q1 and Q2 as well as Q3 and Q4). 6 VCC Bias voltage for control logic. Connect this pin to a +5V bias supply. Place a high quality low ESR 0.1uF ceramic capacitor from this pin to the LGND pin. 7 BOOT1 Floating bootstrap supply pin for the gate drive of control MOSFET Q1. Connect the bootstrap capacitor between this pin and the SW1 pin. The bootstrap capacitor provides the charge to turn on the control MOSFET Q1. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. 8, 45 GATEL1 Gate connection of the Phase 1 synchronous MOSFET Q2. Use a short, wide and direct PCB trace to connect the two pins. 9 LGND Bias and reference ground. All control signals are referenced to this node. 10, 23, 24, 46, 47, 50 PGND High current power ground. Note all pins are internally connected in the package. Provide low resistance connections to the ground plane and respective output capacitors. 11 VDRV Connect this pin to a separate supply voltage between 4.25V and 12V to vary the drive voltage on both the control and synchronous MOSFETs. Place a high quality low ESR ceramic capacitor from this pin to PGND pin (10). 12, 22 GATEL2 Gate connection of the Phase 2 synchronous MOSFET Q4. Use a short, wide and direct PCB trace to connect the two pins. BOOT2 Floating bootstrap supply pin for the gate drive of control MOSFET Q3. Connect the bootstrap capacitor between this pin and the SW2 pin. The bootstrap capacitor provides the charge to turn on the control MOSFET Q3. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. PWM2 / PWMIO1 Dual function pin. It is PWM2 in Dual mode. The PWM2 is the control input for the second driver with either an IR ATL compatible signal or an industry standard Tri-State signal. Connect this pin to the PWM output of the controller. As a DUAL driver, PWM2 controls gate drivers for Phase 2. As a DOUBLER driver, the pin is un-used and is internally disconnected. As a QUAD driver, the pin becomes PWMIO1, a CMOS input or output depending on the configuration of the IR3548 as a slave or master repectively. Refer to Table 1 on page 3 for more details. 4 13 14 15 16 6 EN2 / PWMIO2 Dual function pin. It is Phase 2 ENABLE input as a Dual driver. The pin must be driven high or low in this mode and should not be floated. Grounding this pin places Phase 2 in low quiescent mode. As a DOUBLER driver, the pin is un-used and is internally disconnected. As a QUAD driver, the pin becomes PWMIO2, a CMOS input or output depending on the configuration of the IR3548 as a slave or master respectively. Refer to Table 1 on page 3 for more details. FUNCTION FUNCTION pin used to select between Dual, Doubler and Quad driver modes. Voltage lower than 0.8V sets Dual mode; voltage higher than 2.0V sets Doubler mode; Floating the pin (or between 1.2V and 1.6V) sets Quad mode. This pin in combination with the MODE pin also determines Master or Slave behavior in Quad mode. The pin status is sensed when EN1 is enabled or VCC UVLO is cleared. Refer to Table 1 on page 3 for more details. www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 PIN # PIN NAME PIN DESCRIPTION MODE PWM mode pin used to select either IR ATL input or industry tri-state PWM input. This pin in combination with the FUNCTION pin also determines Master or Slave behavior in Quad mode. Pin should be tied to LGND or VCC, and the pin status is sensed at EN1 enable or when VCC UVLO is cleared. Refer to Table 1 on page 3 for more details. 18-21 VIN2 High current input supply pins for Phase 2. Recommended operating range is 4.25V to 17V. Connect at least a 10uF 1206 ceramic capacitor and a 0.1uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN2 pins and PGND pins (23 and 24). The 0.1uF 0402 capacitor should be on the same side of the PCB as the IR3548. 25-34 SW2 High Current Switch Node for Phase 2 (Q3 and Q4). 35-44 SW1 High Current Switch Node for Phase 1 (Q1 and Q2). 17 7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback January 08, 2014 IR3548 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 1, 2, 48, 49 VIN1 25V -0.3V 5A RMS 20A RMS 3 VINDIV VCC +0.3V -0.3V 1mA 1mA 4 EN1 VCC +0.3V -0.3V 1mA 50mA 5 PWM1 VCC +0.3V -0.3V 5mA 1mA 6 VCC 6.5V -0.3V NA 100mA 7 BOOT1 15V with respect to SW1, 35V with respect to PGND -0.3V with respect to SW1 1A for