IR3575MTRPBF

60A Exposed Top Integrated PowIRstage® FEATURES DESCRIPTION  Peak efficiency up to 95% at 1.2V  Integrated driver, control MOSFET, synchronous MOSFET and Schottky diode  Input voltage (VIN) operating range up to 15V  Output voltage range from 0.25V to Vcc-2.5V, or to 5.5V if internal current sense amplifier is not used  Output current capability of 60A DC  Operation up to 1.0MHz The IR3575 exposed-top integrated PowIRstage® is a synchronous buck gate driver co-packed with a control MOSFET and a synchronous MOSFET with integrated Schottky diode. It is optimized internally for PCB layout, heat transfer and driver/MOSFET timing. Custom designed gate driver and MOSFET combination enables higher efficiency at lower output voltages required by cutting edge CPU, GPU and DDR memory designs. Up to 1.0MHz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. The IR3575’s superior efficiency enables smallest size and lower solution cost. The IR3575 PCB footprint is compatible with the IR3550 (60A), IR3551 (50A) and IR3553 (40A).  Integrated current sense amplifier  VCC under voltage lockout  Thermal flag  Body-Braking® load transient support  Diode-emulation high efficiency mode  Compatible with 3.3V PWM logic and VCC tolerant  Compliant with Intel DrMOS V4.0  PCB footprint compatible with IR3550 and IR3551  Enhanced top side cooling through exposed pad  Small 6mm x 6mm x 0.9mm PQFN package  Lead free RoHS compliant package APPLICATIONS Integrated current sense amplifier achieves superior current sense accuracy and signal to noise ratio vs. best-inclass controller based Inductor DCR sense methods. The IR3575 incorporates the Body-Braking® feature which enables reduction of output capacitors. Synchronous diode emulation mode in the IR3575 removes the zero-current detection burden from the PWM controller and increases system light-load efficiency.  High current, low profile DC-DC converters BASIC APPLICATION IR3575 VIN 4.5V to 7V VIN 4.5V to 15V BOOST PHSFLT# PHSFLT# SW PWM PWM BBRK# BBRK# REFIN REFIN CSIN+ IOUT IOUT CSIN- LGND PGND VOUT Efficiency (%) VCC 95 20 93 18 91 16 89 14 87 12 85 10 83 8 81 6 79 4 77 2 75 Power Loss (W) The IR3575 is optimized specifically for CPU core power delivery in server applications. The ability to meet the stringent requirements of the server market also makes the IR3575 ideally suited to powering GPU and DDR memory designs and other high current applications.  Voltage Regulators for CPUs, GPUs, and DDR memory arrays VCC IR3575 0 0 5 10 15 20 25 30 35 40 45 50 55 60 Output Current (A) Figure 2: Typical IR3575 Efficiency & Power Loss (See Note 2 on Page 8) Figure 1: IR3575 Basic Application Circuit 1 September 6, 2017 | DATASHEET V3.4 60A Exposed Top Integrated PowIRstage® PINOUT DIAGRAM IR3575 ORDERING INFORMATION Package Tape & Reel Qty Part Number PQFN, 32 Lead 6mm x 6mm 3000 IR3575MTRPBF Package Qty Part Number PQFN, 32 Lead 6mm x 6mm 100 IR3575MPBF Figure 3: IR3575 Pin Diagram, Top View TYPICAL APPLICATION DIAGRAM VCC 4.5V to 7V C3 1uF R1 10k PHSFLT# PWM BBRK# Optional for diode emulation setup REFIN C8 1nF IR3575 25 PHSFLT# 26 PWM 27 BBRK# C9 22nF 28 LGND 29 REFIN 30 IOUT 3 18-23 VCC VIN C1 0.1uF BOOST Gate Drivers and Current Sense Amplifier 24 C5 0.22uF CSIN- R2 2.49k CSIN+ 2 Figure 4: Application Circuit with Current Sense Amplifier 2 September 6, 2017 | DATASHEET V3.4 VIN 4.5V to 15V C6 22uF C7 470uF VOUT 6-15 PGND 16, 17 PGND 4 31 1 No Connect L1 150nH SW IOUT TGND C2 10uF x 2 C4 0.22uF 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL APPLICATION DIAGRAM (CONTINUED) VCC 4.5V to 7V C3 0.22uF R1 10k IR3575 PHSFLT# PWM BBRK# 25 PHSFLT# 26 PWM 27 BBRK# 28 LGND 29 REFIN 30 IOUT 3 18-23 VCC VIN C1 0.1uF BOOST Gate Drivers and Current Sense Amplifier 24 C2 10uF x 2 C5 0.22uF L1 150nH CSIN- 1 31 No Connect C6 22uF SW C7 470uF VOUT 6-15 R2 2.49k PGND 16, 17 PGND 4 TGND VIN 4.5V to 15V C4 0.22uF CS+ CS- CSIN+ 2 Figure 5: Application Circuit without Current Sense Amplifier FUNCTIONAL BLOCK DIAGRAM BOOST VIN VIN VIN VIN VIN VIN 24 18 19 20 21 22 23 IR3575 VCC 3 VCC 3.3V 200k BBRK# 27 S Power-on Reset (POR), 3.3V Reference, and Dead-time Control Q R POR 3.3V PWM 26 PHSFLT# 25 LGND 28 IOUT 30 REFIN 29 MOSFET & Thermal Detection Driver Diode Emulation Comparator - 5 32 GATEL GATEL Figure 6: IR3575 Functional Block Diagram 3 15 SW + 31 September 6, 2017 | DATASHEET V3.4 SW 14 SW Driver 4 9 13 SW VCC 2 SW 12 SW 18k Offset +- 1 SW 8 11 SW - CSIN- CSIN+ PGND TGND SW 7 10 SW + Current Sense Amplifier 6 16 17 PGND PGND 60A Exposed Top Integrated PowIRstage® IR3575 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 CSIN- Inverting input to the current sense amplifier. Connect to LGND if the current sense amplifier is not used. 2 CSIN+ Non-Inverting input to the current sense amplifier. Connect to LGND if the current sense amplifier is not used. 3 VCC Bias voltage for control logic. Connect a minimum 1uF cap between VCC and PGND (pin 4) if current sense amplifier is used. Connect a minimum 0.22uF cap between VCC and PGND (pin 4) if current sense amplifier is not used. 4, 16, 17 PGND Power ground of MOSFET driver and the synchronous MOSFET. MOSFET driver signal is referenced to this pin. 5, 32 GATEL Low-side MOSFET driver pins that can be connected to a test point in order to observe the waveform. 6 – 15 SW Switch node of synchronous buck converter. VIN High current input voltage connection. Recommended operating range is 4.5V to 15V. Connect at least two 10uF 1206 ceramic capacitors and a 0.22uF 0402 ceramic capacitor. Place the capacitors as close as possible to VIN pins and PGND pins (16-17). The 0.22uF 0402 capacitor should be on the same side of the PCB as the IR3575. 24 BOOST Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Place the capacitor as close to BOOST pin as possible and minimize parasitic inductance of PCB routing from the capacitor to SW pin. 25 PHSFLT# Open drain output of the phase fault circuits. Connect to an external pull-up resistor. Output is low when a MOSFET fault or over temperature condition is detected. PWM 3.3V logic level tri-state PWM input and 7V tolerant. “High” turns the control MOSFET on, and “Low” turns the synchronous MOSFET on. “Tri-state” turns both MOSFETs off in Body-Braking® mode. In diode emulation mode, “Tri-state” activates internal diode emulation control. See “PWM Tri-state Input” Section for further details about the PWM Tri-State functions. 27 BBRK# 3.3V logic level input and 7V tolerant with internal weak pull-up to 3.3V. Logic low disables both MOSFETs. Pull up to VCC directly or by a 4.7kΩ resistor if Body-Braking® is not used. The second function of the BBRK# pin is to select diode emulatiom mode. Pulling BBRK# low at least 20ns after VCC passes its UVLO threshold selects internal diode emulation control. See “Body-Braking® Mode” Section for further details. 28 LGND Signal ground. Driver control logic, analog circuits and IC substrate are referenced to this pin. 29 REFIN Reference voltage input from the PWM controller. IOUT signal is referenced to the voltage on this pin. Connect to LGND if the current sense amplifier is not used. 30 IOUT Current output signal. Voltage on this pin is equal to V(REFIN) + 32.5 * [V(CSIN+) – V(CSIN-)]. Float this pin if the current sense amplifier is not used. 31 TGND This pin is connected to internal power and signal ground of the driver. For best performance of the current sense amplifier, TGND must be electrically isolated from Power Ground (PGND) and Signal Ground (LGND) in the PCB layout. Connect to PGND if the current sense amplifier is not used. Exposed Pad SW Exposed pad on top side of the package. Connect to a heat sink through insulated thermal material to improve the thermal performance of the package. 18 – 23 26 4 September 6, 2017 | DATASHEET V3.4 60A Exposed Top Integrated PowIRstage® IR3575 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 1 CSIN- VCC + 0.3V -0.3V 1mA 1mA 2 CSIN+ VCC + 0.3V -0.3V 1mA 1mA 5A for 100ns, 200mA DC 3 VCC 8V -0.3V NA 4 PGND 0.3V 5, 32 GATEL VCC + 0.3V 6-15 SW -0.3V -3V for 20ns, -0.3V DC -5V for 20ns, -0.3V DC 16, 17 PGND NA NA 15mA 1A for 100ns, 200mA DC 65A RMS, 90A Peak 30A RMS, 35A Peak 18-23 VIN 2 25V -0.3V 5A RMS 24 BOOST 33V -0.3V 1A for 100ns, 100mA DC 15mA 1A for 100ns, 200mA DC 30A RMS, 35A Peak 65A RMS, 90A Peak 25A RMS, 30A Peak 5A for 100ns, 100mA DC 25 PHSFLT# VCC + 0.3V -0.3V 1mA 20mA 26 PWM VCC + 0.3V -0.3V 1mA 1mA 27 BBRK# VCC + 0.3V -0.3V 1mA 1mA 28 LGND 0.3V -0.3V 15mA 15mA 29 REFIN 3.5V -0.3V 1mA 1mA 30 IOUT VCC + 0.3V -0.3V 5mA 5mA 31 TGND 0.3V -0.3V NA NA 2 25V 1 Note: 1. Maximum BOOST – SW = 8V. 2. Maximum VIN – SW = 25V. 3. All the maximum voltage ratings are referenced to PGND (Pins 16 and 17). THERMAL INFORMATION Thermal Resistance, Junction to Top (θJC_TOP) 0.5 °C/W Thermal Resistance, Junction to PCB (pin 17) (θJB) 1.7 °C/W Thermal Resistance (θJA) 1 19.1 °C/W Maximum Operating Junction Temperature -40 to 150°C Maximum Storage Temperature Range -65°C to 150°C ESD rating HBM Class 1B JEDEC Standard MSL Rating 3 Reflow Temperature 260°C Note: 1. Thermal Resistance (θJA) is measured with the component mounted on a high effective thermal conductivity test board in free air. Refer to International Rectifier Application Note AN-994 for details. 5 September 6, 2017 | DATASHEET V3.4 60A Exposed Top Integrated PowIRstage® IR3575 ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN PARAMETER SYMBOL MIN MAX UNIT Recommended VIN Range VIN 4.5 15 V Recommended VCC Range VCC 4.5 7 V REFIN 0.25 VCC - 2.5 V Recommended Switching Frequency ƒSW 200 1000 kHz Recommended Operating Junction Temperature TJ -40 125 °C Recommended REFIN Range ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Efficiency and Maximum Current IR3575 Peak Efficiency Note 1 IR3575 Maximum DC Current η Note 1 Note 2. See Figure 2. 94.5 % Note 3. See Figure 7. 93.5 % IDC_MAX Note 2. 60 A IPK_MAX Note 4. 5ms load pulse width, 10% load duty cycle. 90 A PWM Input High Threshold VPWM_HIGH PWM Tri-state to High PWM Input Low Threshold VPWM_LOW PWM Tri-state to Low PWM Tri-state Float Voltage VPWM_TRI PWM Floating 1.2 Hysteresis VPWM_HYS Active to Tri-state or Tristate to Active, Note 1 65 IR3575 Maximum Peak Current Note 1 PWM Comparator Tri-state Propagation Delay tPWM_DELAY 2.5 V 0.8 V 1.65 2.1 V 76 100 mV PWM Tri-state to Low transition to GATEL >1V 38 ns PWM Tri-state to High transition to GATEH >1V 18 ns PWM Sink Impedance RPWM_SINK 3.67 5.1 8.70 kΩ PWM Source Impedance RPWM_SOURCE 3.67 5.1 8.70 kΩ Internal Pull up Voltage VPWM_PULLUP VCC > UVLO 3.3 Minimum Pulse Width tPWM_MIN Note 1 41 58 ns V Current Sense Amplifier CSIN+/- Bias Current ICSIN_BIAS -100 0 100 nA CSIN+/- Bias Current Mismatch ICSIN_BIASMM -50 0 50 nA Calibrated Input Offset Voltage VCSIN_OFFSET 6 September 6, 2017 | DATASHEET V3.4 Self-calibrated offset, 0.5V ≤ V(REFIN) ≤ 2.25V ±450 µV 60A Exposed Top Integrated PowIRstage® PARAMETER Gain SYMBOL GCS IR3575 CONDITIONS MIN TYP MAX UNIT 0.5V ≤ V(REFIN) ≤ 2.25V, -5mV ≤ [V(CSIN+) –V(CSIN-)] ≤ 25mV, 0°C ≤ TJ ≤ 125°C 30.0 32.5 35.0 V/V 0.5V ≤ V(REFIN) ≤ 2.25V, -5mV ≤ [V(CSIN+) – V(CSIN-)] ≤ 25mV 30.0 33.0 36.0 V/V 0.8V ≤ V(REFIN) ≤ 2.25V, -10mV ≤[V(CSIN+)–V(CSIN-)] ≤ 25mV 28.0 31.5 35.0 V/V C(IOUT) = 10pF. Measure at IOUT. Note 1 4.8 6.8 8.8 MHz Unity Gain Bandwidth fBW Slew Rate SR Differential Input Range VD_IN Common Mode Input Range VC_IN Output Impedance (IOUT) RCS_OUT IOUT Sink Current ICS_SINK Driving external 3 kΩ Input Offset Voltage VIN_OFFSET Leading Edge Blanking Time Negative Current Time-Out 6 0.8V ≤ V(REFIN) ≤ 2.25V, V/µs -10 25 mV 0 VCC2.5 V 62 200 Ω 0.5 0.8 1.1 mA Note 1 -12 -3 3 mV tBLANK V(GATEL)>1V Starts Timer 50 150 200 ns tNC_TOUT PWM = Tri-State, V(SW) ≤ -10mV 12 28 46 µs Diode Emulation Mode Comparator Digital Input – BBRK# Input voltage high VBBRK#_IH 2.0 Input voltage low VBBRK#_IL Internal Pull Up Resistance RBBRK#_PULLUP VCC > UVLO Internal Pull Up Voltage VBBRK#_PULLUP VCC > UVLO 69 V 200 0.8 V 338 kΩ 3.3 V Digital Output – PHSFLT# Output voltage high VPHASFLT#_OH VCC V Output voltage low VPHASFLT#_OL 4mA 150 300 mV Input current IPHASFLT#_IN V(PHSFLT#) = 5.5V 0 1 µA Control MOSFET Short Threshold VCM_SHORT Measure from SW to PGND Synchronous MOSFET Short Threshold VSM_SHORT Measure from SW to PGND 150 200 250 mV Synchronous MOSFET Open Threshold VSM_OPEN Measure from SW to PGND -250 -200 -150 mV Propagation Delay tPROP PWM High to Low Cycles 15 Cycle Rising Threshold TRISE PHSFLT# Drives Low, Note 1 160 °C Falling Threshold TFALL Note 1 135 °C Phase Fault Detection 3.3 V Thermal Flag 7 September 6, 2017 | DATASHEET V3.4 60A Exposed Top Integrated PowIRstage® PARAMETER SYMBOL IR3575 CONDITIONS MIN TYP MAX UNIT I(BOOST) = 30mA, VCC=6.8V 360 520 920 mV Bootstrap Diode Forward Voltage VFWD VCC Under Voltage Lockout Start Threshold VVCC_START 3.3 3.7 4.1 V Stop Threshold VVCC_STOP 3.0 3.4 3.8 V Hysteresis VVCC_HYS 0.2 0.3 0.4 V 4 8 12 mA 1 µA General VCC Supply Current IVCC VCC = 4.5V to 7V VIN Supply Leakage Current IVIN VIN = 20V, 125C, V(PWM) = Tri-State BOOST Supply Current IBOOST 4.75V < V(BOOST)-V(SW) < 8V REFIN Bias Current IREFIN SW Floating Voltage VSW_FLOAT SW Pull Down Resistance RSW_PULLDOWN 0.5 1.5 3.0 mA -1.5 0 1 µA V(PWM) = Tri-State 0.2 0.4 V BBRK# is Low or VCC = 0V 18 kΩ Notes 1. Guaranteed by design but not tested in production 2. VIN=12V, VOUT=1.2V, ƒSW = 300kHz, L=210nH (0.2mΩ), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, 400LFM airflow, no heat sink, 25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included. 3. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, CIN=47uF x 4, COUT =470uF x3, no airflow, no heat sink, 25°C ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included. 4. VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=210nH (0.2mΩ, 13mm x 13mm x 8mm), VCC=6.8V, CIN=47uF x 4, COUT =470uF x3, no heat sink, 25°C ambient temperature, 8-layer PCB of 3.7” (L) x 2.6” (W), 5ms load pulse width, 10% load duty cycle, and IR3575 junction temerature below 125°C. 8 September 6, 2017 | DATASHEET V3.4 60A Exposed Top Integrated PowIRstage® IR3575 TYPICAL OPERATING CHARACTERISTICS Circuit of Figure 32, VIN=12V, VOUT=1.2V, ƒSW = 400kHz, L=150nH (0.29mΩ), VCC=7V, TAMBIENT = 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), no PWM controller loss, no inductor loss, unless specified otherwise. 94 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 92 91 Normalized Power Loss 90 88 87 86 85 84 83 82 81 0.85 80 5 10 15 20 25 30 35 40 45 50 -2.25 5 55 6 7 8 9 11 12 13 14 15 Input Voltage (V) Output Current (A) Figure 10: Normalized Power Loss vs. Input Voltage Figure 7: Typical IR3575 Efficiency 10 1.40 6.00 9 1.35 5.25 1.30 4.50 1.25 3.75 1.20 3.00 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 2 0.95 -0.75 1 0.90 -1.50 0 0.85 8 Normalized Power Loss 7 6 5 4 3 0 5 10 15 20 25 30 35 40 45 50 -2.25 0.8 55 0.9 1 1.1 Figure 8: Typical IR3575 Power Loss 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Output Voltage (V) Output Current (A) Figure 11: Normalized Power Loss vs. Output Voltage Normalized Power Loss Power Loss (W) 10 Case Temperature Adjustment (°C) 0 1.40 6.00 1.35 5.25 1.30 4.50 1.25 3.75 1.20 3.00 1.15 2.25 1.10 1.50 1.05 0.75 1.00 0.00 0.95 -0.75 0.90 -1.50 0.85 200 Case Temperature Adjustment (°C) Efficiency (%) 89 Case Temperature Adjustment (°C) 93 -2.25 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) Figure 9: Thermal Derating Curve, TCASE