6A Highly Integrated SupIRBuckTM SingleInput Voltage, Synchronous Buck Regulator
FEATURES
IR3827
DESCRIPTION
• Single input voltage range from 5V to 21V
• Wide input voltage range from 1.0V to 21V with
external VCC bias voltage
• Output voltage range from 0.6V to 0.86% PVin
The IR3827 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard PWM controller and MOSFETs make
IR3827 a space-efficient solution, providing accurate
power delivery for low output voltage applications.
• Enhanced line/load regulation with feedforward
IR3827 is a versatile regulator which offers
programmable switching frequency and internally set
current limit while operating in wide range of input and
output voltage conditions.
• Programmable switching frequency up to
1.2MHz
• Three user selectable soft-start time
• User selectable LDO output voltage
• Enable input with voltage monitoring capability
• Thermally compensated current limit with robust
hiccup mode over current protection
• Synchronization to an external clock
• Enhanced Pre-bias start-up
• Precise reference voltage (0.6V+/-0.6%)
The switching frequency is programmable from 300kHz
to 1.2MHz for an optimum solution. It also features
important protection functions, such as Pre-Bias
startup, thermally compensated current limit, over
voltage protection and thermal shutdown to give
required system level security in the event of fault
conditions.
APPLICATIONS
• Open-drain PGood indication
• Optional power up sequencing
• Computing Applications
• Integrated MOSFET drivers and bootstrap diode
• Set Top Box Applications
• Thermal Shut Down
• Storage Applications
• Monotonic Start-Up
• Data Center Applications
• Operating temp: -40°C < Tj < 125°C
• Distributed Point of Load Power Architectures
• Package size: 4mm x 5mm PQFN
• Lead-free, Halogen-free and RoHS6 Compliant
ORDERING INFORMATION
Base Part Number
Package Type
IR3827
IR3827
PQFN 4 mm x 5 mm
PQFN 4 mm x 5 mm
Standard Pack
Form
Quantity
Tape and Reel
750
Tape and Reel
4000
Orderable Part Number
IR3827MTR1PBF
IR3827MTRPBF
IR3827
PBF – Lead Free
TR/TR1 – Tape and Reel
M – PQFN Package
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© 2013 International Rectifier
July 18, 2013
IR3827
BASIC APPLICATION
Vin
SS_Select Vin
Vcc/
LDO_out
PGood
PGood
Seq
Enable
Rt/Sync
PVin
Boot
Vo
SW
IR3827
Fb
Comp
LDO_Select Gnd PGnd
Figure 1 IR3827 Basic Application Circuit
Figure 2 IR3827 Efficiency
PINOUT DIAGRAM
IR3827
PVin
SW
13
12
PGnd
11
Boot 14
10 Vcc/LDO_Out
GND
Enable 15
9
17
Vin
8 LDO_Select
d
7
PG
oo
t
ele
c
c
6
SS_
S
Syn
Gn
d
5
Rt/
4
mp
N/
3
Co
2
C
1
Fb
Seq 16
Figure 3 4mm x 5mm PQFN (Top View)
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© 2013 International Rectifier
July 18, 2013
IR3827
BLOCK DIAGRAM
5.1V/6.9V
Internal LDO
Vin
VCC
Vcc/ LDO_Out
THERMAL
TSD
SHUT DOWN
LDO_Select
OC
FAULT
POR
CONTROL
UVcc
Gnd
UVcc
Boot
OV
Comp
Seq
+
+
E/A
+
-
VREF
+
0.6V 0.15V
FAULT
POR VCC
PVin
Vin
Fb
Fb
HDrv
POR
INTL_SS
VREF
OV
OVER
VOLTAGE
HDin
SW
GATE
DRIVE
LDin
SS_Select
SOFT
START
POR
SSOK
LDrv
CONTROL
VREF
FAULT
PGnd
SEQ
Enable
LOGIC
UVEN
UVEN
OC
Over Current
Protection
POR
UVcc
POR
Rt/Sync PGood
Figure 4 Simplified Block Diagram
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© 2013 International Rectifier
July 18, 2013
IR3827
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
Fb
Inverting input to the error amplifier. This pin is connected directly to the output of the
regulator via a resistor divider to set the output voltage and to provide the feedback signal
to the error amplifier.
2
N/C
3
Comp
4, 17
Gnd
5
Rt/Sync
Multi-function pin to set the switching frequency. The internal oscillator frequency is set
with a resistor between this pin and Gnd. Or synchronization to an external clock by
connecting this pin to the external clock signal through a diode.
6
SS_Select
Soft start selection pin. Three user selectable soft start time is available: 1.5ms
(SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd)
7
PGood
8
LDO_Select
Should not be connected to other signals on PCB layout. It is internally connected for
testing purpose.
Output of error amplifier. An external resistor and capacitor network is typically connected
from this pin to Fb pin to form a loop compensator.
Signal ground for internal reference and control circuitry.
Open-drain power good indication pin. Connect a pull-up resistor from this pin to Vcc.
LDO output voltage selection pin. Float gives 5.1V and low 0V (Gnd) gives 6.9V
Input for internal LDO. A 1.0µF capacitor should be connected between this pin and
PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to
Vcc/LDO_out pin. Connecting this pin to PVin can also implement the input voltage
feedforward.
9
Vin
10
Vcc/LDO_Out
11
PGnd
12
SW
Switch node. Connected this pin to the output inductor.
13
PVin
Input voltage for power stage.
14
Boot
Supply voltage for high side driver, a 100nF capacitor should be connected between this
pin and SW pin.
15
Enable
Enable pin to turn on and off the device. Input voltage monitoring (input UVLO) can also
be implemented by connecting this pin to PVin pin through a resistor divider.
16
Seq
Sequence pin to do simultaneous and ratiometric sequencing operation. A resistor divider
can be connected from master output to this pin for sequencing mode of operation. If not
used, leave it open.
17
Gnd
Signal ground for internal reference and control circuitry.
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Output of the internal LDO and optional input of an external biased supply voltage.
minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd.
A
Power Ground. This pin serves as a separated ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
© 2013 International Rectifier
July 18, 2013
IR3827
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin to PGnd (Note 4)
-0.3V to 25V
Vcc/LDO_Out to PGnd (Note 4)
-0.3V to 8V (Note 1)
Boot to PGnd (Note 4)
-0.3V to 33V
SW to PGnd (Note 4)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
Boot to SW
-0.3V to VCC + 0.3V (Note 2)
PGood, SS_Select to Gnd (Note 4)
-0.3V to VCC + 0.3V (Note 2)
Other Input/Output Pins to Gnd (Note 4)
-0.3V to +3.9V
PGnd to Gnd
-0.3V to +0.3V
THERMAL INFORMATION
Junction to Ambient Thermal Resistance ƟjA
32 °C/W (Note 3)
Junction to PCB Thermal Resistance Ɵj-PCB
2 °C/W
Storage Temperature Range
-55°C to 150°C
Junction Temperature Range
-40°C to 150°C
Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C
Note 2: Must not exceed 8V
Note 3: Based on IRDC3827 demo board - 2.6”x2.2”, 4-layer PCB board using 2 oz. copper on each layer.
Note 4: PGnd pin and Gnd pin are connected together.
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July 18, 2013
IR3827
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
MIN
MAX
UNITS
Input Voltage Range with External Vcc Note 5, Note 7
PVin
1.0
21
Input Voltage Range with Internal LDO Note 6, Note 7
Vin, PVin
5.5
21
Supply Voltage Range (Note 6)
VCC
4.5
7.5
Supply Voltage Range (Note 6)
Boot to SW
4.5
7.5
Output Voltage Range
V0
0.6
0.86 x PVin
Output Current Range
I0
0
6
A
Switching Frequency
FS
300
1200
kHz
Operating Junction Temperature
TJ
-40
125
°C
V
Note 5: Vin is connected to Vcc to bypass the internal LDO.
Note 6: Vin is connected to PVin. For single-rail applications with PVin=Vin= 4.5V-5.5V, please refer to the application information in the
section of User Selectable Internal LDO and the section of Over Current Protection.
Note 7: Maximum SW node voltage should not exceed 25V.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Stage
PVin=Vin = 12V, Vo=1.2V,
Io = 6A, Fs=600kHz,L=1.0uH,
LDO_Select=Gnd. Note 8
Power Losses
Top Switch RDS(ON)
Bottom Switch RDS(ON)
Bootstrap Diode Forward
Voltage
PLOSS
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W
PVin=Vin =12V, Vo=1.2V,
Io=6A, Fs=600kHz, L=1.0uH,
LDO_Select=Float. Note 8
1.3
VBOOT -Vsw=5.1V,Io = 6A,
Tj = 25°C
21
29
VBOOT -Vsw=6.9V,Io = 6A,
Tj = 25°C
16
22
Vcc = 5.1V, Io = 6A, Tj = 25°C
21.4
30
Vcc = 6.9V, Io = 6A, Tj = 25°C
16.8
23
260
470
mV
VSW = 0V, Enable = 0V
1
µA
VSW = 0V, Enable = High,
VSEQ=0V
1
µA
RDS(on)-T
RDS(on)-B
VD
SW Leakage Current
Dead Band Time
1.1
TD
I(Boot) = 10mA
Note 8
© 2013 International Rectifier
180
10
mΩ
ns
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
200
µA
Supply Current
Vin Supply Current (standby)
Vin Supply Current
(dynamic)
Iin(Standby)
EN = Low, No Switching
EN = High, Fs = 600kHz,
Vin = PVin = 21V,
LDO_Select=Gnd
Iin(Dyn)
10
13
mA
EN = High, Fs = 600kHz,
Vin = PVin = 21V,
LDO_Select=Float
8
11
5.1
5.4
VCC/LDO_Out
Vin(min) = 5.5V, Io = 0-30mA,
Cload =2.2uF,
LDO_Select=Float
Output Voltage
4.75
V
Vcc
Vin(min) = 7.3V, Io = 0-30mA,
Cload = 2.2uF,
LDO_Select=Gnd
LDO_Select Input bias
Current
6.5
LDO_Select=Gnd
6.9
7.2
30
60
Vin=6.5V,Io=30mA,
Cload=2.2uF,
LDO_Select=Gnd
LDO Dropout Voltage
0.7
Vcc_drop
V
Vin=4.7V,Io=25mA,
Cload=2.2uF,
LDO_Select=Float
Short Circuit Current
Ishort
uA
0.7
LDO_Select=Gnd
70
mA
1.0
V
Oscillator
Rt Voltage
Frequency Range
Ramp Amplitude
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VRt
Fs
Rt = 80.6kΩ
270
300
330
Rt = 39.2kΩ
540
600
660
Rt = 19.1kΩ
1080
1200
1320
Vin = 7.3V, Vin slew rate max
= 1V/µs, Note 8
1.095
Vin = 12V, Vin slew rate max
= 1V/µs, Note 8
1.80
Vin = 21V, Vin slew rate max
= 1V/µs, Note 8
3.15
Vin=Vcc=5V, For external Vcc
operation, Note 8
0.75
Vramp
kHz
Vp-p
© 2013 International Rectifier
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
Ramp Offset
CONDITIONS
MIN
Note 8
Minimum Pulse Width
Tmin(ctrl)
Maximum Duty Cycle
Dmax
Fixed Off Time
Toff
TYP
0.16
Note 8
Fs = 300kHz, Vin =PVin= 12V
MAX
V
60
86
Note 8
Fsync
270
Sync Pulse Duration
Tsync
100
High
3
ns
%
200
Sync Frequency Range
UNITS
250
ns
1320
kHz
200
ns
Sync Level Threshold
V
Low
0.6
Error Amplifier
Input Offset Voltage
VFB – VSEQ, VSEQ=0.3V
-3
+3
%
Input Bias Current (VFB)
IFB(E/A)
-1
+1
Input Bias Current (VSEQ)
ISEQ(E/A)
0
+4
Sink Current
Isink(E/A)
0.4
0.85
1.2
mA
Isource(E/A)
4
7.5
11
mA
µA
Source Current
Slew Rate
Gain-Bandwidth Product
DC Gain
SR
Note 8
7
12
20
V/µs
GBWP
Note 8
20
30
40
MHz
Gain
Note 8
100
110
120
dB
1.7
2.0
2.3
V
100
mV
1.2
V
Maximum Output Voltage
Vmax(E/A)
Minimum Output Voltage
Vmin(E/A)
Common Mode Input Voltage
0
Reference Voltage (VREF)
Feedback Voltage
LDO_Select= Gnd
0.6
LDO_Select= Float
0.6
VFB
V
0°C < Tj < 70°C
-0.6
+0.6
-40°C < Tj < 125°C ; Note 9
-1.2
+1.2
SS_Select=High
0.34
0.4
0.46
SS_Select=Float
0.17
0.2
0.23
SS_Select=Gnd
0.085
0.1
0.115
40
80
%
Accuracy
Soft Start
Soft Start Ramp Rate
SS_Select Input Bias Current
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LDO_Select=Gnd
SS_Select=Gnd
© 2013 International Rectifier
mV/µs
uA
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Good
Power Good Turn on
Threshold
VPG (on)
VFB rising
85
90
95
% VREF
Power Good Lower Turn off
Threshold
VPG(lower)
VFB falling
80
85
90
% VREF
Power Good Turn on Delay
TPG(ON)_D
VFB rising, see VPG(on)
Power Good Upper Turn off
Threshold
VPG(upper)
VFB rising
PGood Comparator Delay
PGood Voltage Low
VFB < VPG(lower) or
VFB > VPG(upper)
PG(voltage)
2.56
ms
115
120
125
% VREF
1
2
3.5
µs
0.5
V
IPGood = -5mA
Under-Voltage Lockout
Vcc-Start Threshold
VCC UVLO
Start
Vcc rising trip Level
3.9
4.1
4.3
V
Vcc-Stop Threshold
VCC UVLO
Stop
Vcc falling trip Level
3.6
3.8
4.0
V
Enable-Start-Threshold
Enable
UVLO Start
ramping up
1.14
1.2
1.26
V
Enable-Stop-Threshold
Enable
UVLO Stop
ramping down
0.95
1
1.05
Enable Leakage Current
IEN_LK
Enable = 3.3V
1
µA
Over-Voltage Protection
OVP Trip Threshold
OVP Comparator Delay
OVP_Vth
VFB rising
115
120
125
% VREF
1
2
3.5
µs
Tj = 25°C, LDO_Select=Float
6.2
7.3
8.5
Tj = 25°C, LDO_Select=Gnd
7.9
9.3
10.8
TOVP_D
Over-Current Protection
Current Limit
Hiccup Blanking Time
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A
ILIMIT
TBLK_Hiccup
SS_Select = Vcc, Note 8
10
SS_Select = Float, Note 8
20
SS_Select = Gnd, Note 8
40
© 2013 International Rectifier
ms
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Upper Gate Driver
Source Resistance
VBOOT-VSW = 5.1V, Note 8
3
Sink Resistance
VBOOT-VSW = 5.1V, Note 8
4
Source Resistance
VCC = 5.1V, Note 8
2
Sink Resistance
VCC = 5.1V, Note 8
0.8
Thermal Shutdown Threshold
Note 8
145
Hysteresis
Note8
20
Ω
Lower Gate Driver
Ω
Over-Temperature Protection
°C
Note 8: Guaranteed by design, but not tested in production.
Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
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IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= Internal LDO, LDO_Select = Float, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3827, the inductor losses and the losses of the input and output
capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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© 2013 International Rectifier
July 18, 2013
IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= Internal LDO, LDO_Select = Gnd, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3827, the inductor losses and the losses of the input and output
capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement.
12
VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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July 18, 2013
IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= External 5V, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power
loss curves include the losses of IR3827, the inductor losses and the losses of the input and output capacitors. The table
below shows the inductors used for each of the output voltages in the efficiency measurement.
13
VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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© 2013 International Rectifier
July 18, 2013
IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss
curves include the losses of IR3827, the inductor losses and the losses of the input and output capacitors. The table below
shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.68
PCMB065T- R68MS (Cyntec)
3.9
1.2
0.82
SPM6550T-R82M(TDK)
4.2
1.8
0.82
SPM6550T-R82M(TDK)
4.7
3.3
1.0
SPM6550T-1R0M(TDK)
4.7
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IR3827
RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=6.9V
RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=5.1V
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IR3827
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
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July 18, 2013
IR3827
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
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IR3827
THEORY OF OPERATION
DESCRIPTION
The IR3827 SupIRBuckTM is a 6A easy-to-use, fully
integrated and highly efficient synchronous Buck
regulator intended for Point-Of-Load (POL)
applications. It includes two IR HEXFETs with low
RDS(on). The bottom FET has an integrated
monolithic schottky diode in place of a conventional
body diode.
The IR3827 provides precisely regulated output
voltage programmed via two external resistors from
0.6V to 0.86×Vin. It uses voltage mode control
employing a proprietary PWM modulator with input
voltage feedforward. That provides excellent noise
immunity, easy loop compensation design, and good
line transient response.
The IR3827 has a user-selectable internal Low
Dropout (LDO) Regulator, allowing single supply
operation without resorting to an external bias
supply voltage. To further improve the efficiency, the
internal LDO can be bypassed. Instead an external
bias supply can be used. This feature allows the
input bus voltage range extended to 1.0V.
A RC network has to be connected between the FB
pin and the COMP pin to form a feedback
compensator. The goal of the compensator design
is to achieve a high control bandwidth with a phase
margin of 45° or above. The high control bandwidth
is beneficial for the loop dynamic response, which
helps to reduce the number of output capacitors,
PCB size and the cost. A phase margin of 45° or
higher is desired to ensure the system stability. For
most applications, a gain margin of -10dB or higher
is preferred to accommodate component variations
and to eliminate jittering/noise. The proprietary PWM
modulator in IR3827 significantly reduces the PWM
jittering, allowing the control bandwidth in the range
th
th
of 1/10 to 1/5 of the switching frequency.
Two types of compensators are commonly used:
Type II (PI) and Type III (PID), as shown in Figure 5.
The selection of the compensation type is
dependent on the ESR of the output capacitors.
Electrolytic capacitors have relatively higher ESR. If
the ESR pole is located at the frequency lower than
the cross-over frequency, FC, the ESR pole will help
to boost the phase margin. Thus a type II
compensator can be used. For the output capacitors
with lower ESR such as ceramic capacitors, type III
compensation is often desired.
The IR3827 features programmable switching
frequency from 300kHz to 1.2MHz, three selectable
soft-start time, and smooth synchronization to an
external clock. The other important functions include
thermally compensated over current protection,
output over voltage protection and thermal shutdown, etc.
CC2
Vout
CC1
RC1
Rf1
-
Fb
Rf2
E/A
Comp
+
VREF
VOLTAGE LOOP COMPESNATION DESIGN
The IR3827 uses PWM voltage mode control. The
output voltage of the POL, sensed by a resistor
divider, is fed into an internal Error Amplifier (E/A).
The output of the E/R is then compared to an
internal ramp voltage to determine the pulse width of
the gate signal for the control FET. The amplitude of
the ramp voltage is proportional to Vin so that the
bandwidth of the voltage loop remains almost
constant for different input voltages. This feature is
called input voltage feedfoward. It allows the
feedback loop design independent of the input
voltage. Please refer to the next section for more
information.
(a)
Vout
Rf3
CC2
Rf1
RC1
Fb
-
Rf2
+
CC1
Cf3
E/A
Comp
VREF
(b)
Figure 5 Loop Compensator (a) Type II, (b) Type III
18
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© 2013 International Rectifier
July 18, 2013
IR3827
Table 1 lists the compensation selection for different
types of output capacitors.
For more detailed design guideline of voltage loop
compensation, please refer to the application note
AN-1162, “Compensation Design Procedure for
Buck Converter with Voltage-Mode Error-Amplifier”.
SupBuck design tool is also available at www.irf.com
providing the reference design based on user’s
design requirements.
function can also minimize impact on output voltage
from fast Vin change. The maximum Vin slew rate is
within 1V/µs.
If an external bias voltage is used as Vcc, Vin pin
should be connected to Vcc/LDO_out pin instead of
PVin pin. Then the feedforward function is disabled.
The control loop compensation might need to be
adjusted.
16V
12V
TABLE 1 RECOMMENDED COMPENSATION TYPE
LOCATION OF
CROSS-OVER
FREQUENCY
TYPE OF
OUTPUT
CAPACITORS
Type II (PI)
FLC
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