IR3892MTRPBF

Dual output, 6A/Phase, Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES IR3892 DESCRIPTION • Single 5V to 21V application The IR3892 SupIRBuck® is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3892 a space-efficient solution, providing accurate power delivery for low output voltage. • Wide Input Voltage Range from 1V to 21V with external Vcc • Output Voltage Range: 0.5V to 0.86*PVin • Dual output, 6A/Phase • Enhanced Line/Load Regulation with FeedForward • Programmable Switching Frequency up to 1.0MHz • Internal Digital Soft-Start • Enable input with Voltage Monitoring Capability The switching frequency is programmable from 300kHz to 1.0MHz for an optimum solution. • Thermally compensated current limit and Hiccup Mode Over Current Protection • External synchronization with Smooth Clocking • Precision Reference Voltage (0.5V +/-1%) • Seq pin for Sequencing Applications • Integrated MOSFETs, drivers and Bootstrap diode • Thermal Shut Down IR3892 is a versatile regulator which offers programmability of switching frequency and a fixed current limit while operating in wide input and output voltage range. It also features important protection functions, Over Voltage Protection (OVP), Pre-Bias hiccup current limit and thermal shutdown required system level security in the event conditions. such as startup, to give of fault APPLICATIONS • Open Feedback Line Protection • Over Voltage Protection • Sever Applications • Interleaved Phases to reduce Input Capacitors • Netcom Applications • Monotonic Start-Up • Set Top Box Applications • Operating Junction Temp: -40 C 1.2V Intl_SS 1/2 [Time] Vo 1/2 Figure 7: Pre-bias Start Up Figure 5: Recommended startup for Normal operation 12.5% Vcc EN2 ... HDRv PVin=Vin ... LDRv > 1.2V 16 ... ... 25% ... ... 16 ... 87.5% ... ... End of PB ... Intl_SS 2 EN1 > 1.2V Intl_SS 1 SOFT-START Vo1 Vo2 Figure 6: Recommended startup for sequencing operation (ratiometric or simultaneous) Figure 5 shows the recommended start-up sequence for the normal (non-sequencing) operation of IR3892, when EN pins are used as a logic input. Figure 6 shows the recommended startup sequence for sequenced operation of IR3892. PRE-BIAS STARTUP IR3892 begins each start up by pre-charging the output to prevent oscillation and disturbances to the output voltage. The buck converter starts in an asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 7 shows a typical pre-bias sequence. The sync FET always starts with a narrow pulse width (12.5% of the switching period). The pulse width increase after 16 pulses by 12.5% until the output reaches steady state value. There are 16 pulses for each step. Figure 8 shows the series of 16 x 8 startup pulses. 18 www.irf.com Figure 8: Pre-bias startup pulses © 2014 International Rectifier IR3892 has an internal digital soft-start to control the output voltage rise and to limit the current surge during start-up. To ensure the correct start-up, the soft-start sequence initiates when the EN and VCC rise above their UVLO thresholds and generates Power On Ready (POR) signal. The internal soft-start rises with the typical rate of 0.2mV/µS from 0V to 1.5V. Figure 9 shows the waveforms during soft-start. The normal Vout start-up time is fixed, and is equal to: Tstart = (0.65V − 0.15V ) = 2.7mS 0.18mV / µS (1) During the soft-start the over-current protection (OCP) and the over-voltage protection (OVP) is enabled to protect the device from short circuit or over voltage events. Submit Datasheet Feedback May 29, 2014 IR3892 from Rt/Sync pin to GND is required to set the free running frequency. POR 3.0V 1.5V 0.65V Intl_SS 0.15V Vout t1 t2 t3 Figure 9: Theoretical operation waveforms during softstart (non-sequencing) OPERATING FREQUENCY When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its free-running frequency, a transition from the free-running frequency to the external clock frequency will happen. The switching frequency gradually synchronizes to the external clock frequency regardless of which one is faster. On the contrary, when the external clock signal is removed from Rt/Sync pin, the switching frequency gradually returns to the free-running frequency. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin. Figure 10 shows the timing diagram of these transitions. The switching frequency can be programmed between 300KHz-1.0MHz by connecting an external resistor from Rt/Sync pin to GND. Table 1 tabulates the oscillator frequency versus Rt. Synchronize to the external clock Free Running Frequency ... SW Table 1: Switching Frequency (Fs) vs. External Resistor (Rt) Rt (KΩ) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 Freq (KHz) 300 400 500 600 700 800 900 1000 EXTERNAL SYNCHRONIZATION IR3892 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (POL) regulators are used. A multiplefunction pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock solely and no resistor is required. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free-running frequency, an external resistor 19 www.irf.com © 2014 International Rectifier Return to freerunning freq Gradually change Gradually change ... Fs1 SYNC Fs1 Fs2 Figure 10: Timing diagram for synchronization to an external clock (Fs1>Fs2 or Fs15.0V. The PWM ramp amplitude (Vramp) is proportionally changed with respect to Vin to maintain PVin/Vramp ratio. The ratio is almost constant throughout the Vin range (as shown in Figure 12). By maintaining a constant PVin/Vramp, the control loop bandwidth and phase margin are more constant. F.F. function also helps minimize the effect of PVin changes on the output voltage. Feed-Forward is based on the Vin voltage and needs to be accounted for when calculating IR3892 compensation. The PVin/Vramp ratio is not maintained when Vin and PVin are not equal. This is the case when an external bias voltage for VCC. When using an external VCC voltage, Vin pin should be connected to the VCC pin instead of the PVin pin. Compensation for the configuration should reflect the separation. 16V 12V 0 Current Limit Hiccup PWM Ramp PWM Ramp Amplitude = 2.4V PWM Ramp Amplitude = 1.8V Tblk_Hiccup 20.48 mS* IL 12V 6.8V Vin PWM Ramp Amplitude = 1.02V 0 0 HDrv ... Figure 12: Timing diagram for Feed Forward (F.F.) Function 0 LDrv Ramp Offset ... 0 PGood *typical filter delay 0 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 LOW DROPOUT REGULATOR (LDO) Ext VCC IR3892 has an integrated low dropout (LDO) regulator which can provide gate drive voltage for both drivers. When using an internally biased configuration, the LDO draws from the Vin pin and provides a 5.3V (typ.), as shown in Figure 13. Vin and PVin can be connected together as shown in the internally biased single rail configuration, Figure 14. PVin Vin PVin IR3892 VCC PGND An external bias configuration can provide gate drive voltage for the drivers instead of the internal LDO. To use an external bias, connected to Vin and VCC to the external bias, as shown in Figure 15. PVin can also be connected or a different rail can be used. When using multiple rail configurations, calculate the compensation Vramp associated with Vin. Vramp is derived from Vin which can be different from PVin, refer to Feed-Forward section. Vin PVin Vin PVin IR3892 VCC PGND Figure 13: Internally Biased Configuration Vin Vin PVin IR3892 VCC PGND Figure 14: Internally Biased Single Rail Configuration 21 www.irf.com © 2014 International Rectifier Figure 15: Externally Biased Configuration OUTPUT VOLTAGE SEQUENCING IR3892 can accommodate user sequencing options using Seq, EN1/2, and PGood1/2 pins. In the block diagram presented on page 3, the error-amplifier (E/A) has been depicted with three positive inputs. Ideally, the input with the lowest voltage is used for regulating the output voltage and the other two inputs are ignored. In practice the voltages of the other two inputs should be at least 200mV greater than the referenced voltage input so that their effects can completely be ignored. In normal operating condition, the IR3892 channels initially follow their internal soft-starts (Intl_SS) and then references VREF. After Enable goes high, Intl_SS begins to ramp up from 0V. The FB pin follows the Intl_SS until it approaches VREF where the E/A starts to reference the VREF instead of the Intl_SS (refer to Figure 16). VREF and Seq are not referenced initially because they are higher than Intl_SS. VREF is 0.5V, typical. Seq is internally pulled up to approximately 3.3V when left floating in normal operation and only used by channel 2. In sequencing mode of operation, Vout2 is initially regulated with the Seq pin. Vout2 ramps up similar to the normal operation, but Intl_SS is replaced with Seq. Seq is kept to ground level until Intl_SS signal reaches its final value. FB2 follows Seq, until Seq approaches VREF where the E/A switches reference to the VREF. Vout2 is then regulated with respect to internal VREF (refer to Figure 17). The final Seq voltage should between 0.7V and 3.3V. Submit Datasheet Feedback May 29, 2014 IR3892 resistor values are set up in the following way, RA/RB > RE/RF > RC/RD. 0.65V OVP Is Activated Intl_SS OVP(Threshold) OVP(Hys) VPG(Upper) LDrv turned off VPG(Lower) FB/Vsns PGood Table 2 summarizes the required conditions to achieve simultaneous or ratiometric sequencing operations. Table 2: Required Conditions for Simultaneous / Ratiometric Tracking and Sequencing Seq Required Condition Floating ― Ramp up from 0V Ramp up from 0V RA/RB>RE/RF=RC/RD Operating Mode 1.3 mS* 1.3 mS* * typical filter delay Figure 16: Timing Diagram for Output Sequence Intl_SS (>0.7V) Normal (Non-sequencing, Non-tracking) Simultaneous Sequencing Ratiometric Sequencing VREF RA/RB>RE/RF>RC/RD Vin Seq OVP(Threshold) Vo1 VPG(Lower) Threshold SW2 En2 PVin Vin Vcc/LDO_out En1 SW1 VPG(Upper) Threshold Vo2 Boot2 RA FB1 RB FB/Vsns PGood 1.3 mS* 2uS* RD Vo1 PGND2 Comp2 Vsns2 PGood2 Rt/Sync GND Figure 17: Timing Diagram for Sequence Startup (Seq ramping up/down) RF Comp1 Vsns1 PGood1 Seq PGND1 RE *typical filter delay RC FB2 Figure 18: Application Circuit for Simultaneous and Ratiometric Sequencing IR3892 can perform simultaneous or ratiometric sequencing operations. Simultaneous sequencing is when the both outputs rise at the same rate. During Ratiometric sequencing, the ratio of the two outputs is held constant during power-up. Figure 19 shows examples of the two sequencing modes. IR3892 uses a single configuration to implement both mode of sequencing operations. Figure 18 shows the typical circuit configuration for both modes of sequencing operation. The sequencing mode is determined by the RA/RB, RE/RF, and RC/RD ratios. If RE/RF = RC/RD, simultaneous startup is achieved. Vout2 follows Vout1 until the voltage at the Seq pin reaches VREF. After the voltage at the Seq pin exceeds VREF, VREF dictates Vout2. In ratiometric startup, Vout2 rises at a slower rate than Vout1. The 22 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Vcc EN2 Intl_SS2 EN1 Vo1 (master) Vo2 (slave) (a) Open Feedback Loop protection (OFLP) is devised to shutdown the channel in case the feedback is broken. OFLP is activated when the Vsns is above the VPG(upper) threshold, 0.85*VREF typical, and remains active while Vsns is above the VPG(lower) threshold, 0.80*VREF. When FB drop below OFLP(threshold) threshold, 0.70*VREF, OFLP disables switching and pulls down on PGood. The part remains disabled until FB rises above OFLP(threshold) plus OFLP(Hys), 0.75*VREF. This function does not latch the part off nor does it require an EN or a VCC toggle to re-enable the part. Vo1 (master) Vo2 (slave) (b) Vsns Figure 19: Typical waveforms for sequencing mode of operation: (a) simultaneous, (b) ratiometric Over-Voltage protection (OVP) disables the channel when the output voltage exceeds the over-voltage threshold. IR3892 achieves OVP by comparing Vsns pin to the internal over-voltage threshold set at OVP(threshold), 1.2*VREF typical. Vsns voltage is determined by an external voltage divider resistor network connected to the output in typical application. When Vsns exceeds the over-voltage threshold, an over-voltage is detected and OV signal asserts after OVP(delay). The high side drive signal HDrv is turned off immediately and PGood flags low. The low side drive signal is kept on until the Vsns voltage drops below the lower threshold. After that, HDrv is latched off until a reset is performed by cycling either VCC or the respective EN. OVP(Hys) Vsns 2uS * PGood HDrv LDrv *typical filter delay Figure 20: Timing diagram for OVP OPEN FEEDBACK-LOOP PROTECTION 23 www.irf.com VREF OFLP Trip Threshold PGood OVER-VOLTAGE PROTECTION (OVP) OVP(Threshold) FB VPG(Lower) Threshold © 2014 International Rectifier Figure 21: Timing Diagram for Open Feedback Line Protection (OFLP) POWER GOOD OUTPUT PGood is an open drain pin that monitors the UV, FAULT and the POR signals. PGood signal asserts approximately 1.3mS, after Vsns rises above VGP(Upper) threshold, 0.85*VREF typical, while FAULT is low and POR is high. It remains asserted while FAULT is low and POR is high and Vsns stays above VGP(Lower) threshold, 0.80*VREF typical. When Vsns falls below VGP(Lower) threshold there is a typical 2µS delay before PGood goes low. The two PGood signals are independent of each other and are set according to their respective channel. SWITCH NODE PHASE SHIFT The two converters on the IR3892 run interleaving phases by 180° to reduce input filter requirements. The two converters are synchronized to the user programmable oscillator. Channel 1 runs in phase with the oscillator while channel 2 runs out of phase. Staggering the switching cycles reduces the time the converters draw current from the supply simultaneously. The pulses of current drawn from the input induce voltage ripples across the input capacitor. The voltage ripple shapes are dependent on the different loading and output voltages of the two converters. By switching the converters at different times, the magnitude of voltage ripples reduces and input filter requirements become less stringent. Submit Datasheet Feedback May 29, 2014 IR3892 MINIMUM ON-TIME CONSIDERATIONS MAXIMUM DUTY RATIO The minimum on-time is the shortest amount of time which the Control FET may be reliably turned on. Internal delays and gate drive make up a large portion of the minimum on-time. IR3892 has a minimum ontime of 60nS. Maximum duty ratio is lower at higher frequencies and higher Vin voltages. A maximum off-time of 250nS is specified for IR3892. This provides an upper limit on the operating duty ratio at any given switching frequency. The off-time becomes a larger percentage of the switching period when high switching frequencies are used. Thus, a lower the maximum duty ratio can be achieved when frequencies increase. Any design or application using IR3892 should operation with a pulse width greater than minimum ontime. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. ton = Vout D = Fs PVin × Fs (3) In any application that uses IR3892, the following condition must be satisfied: t on (min) ≤ t on (4) Vout PVin × Fs V ∴ PVin × Fs ≤ out ton (min) ton (min) ≤ (5) (6) Feed-Forward from the Vin voltage placed a limitation on the maximum duty cycle by saturating the compensation ramp. By maintaining a constant Vin/Vramp, the effective Vramp voltage is increased while the maximum range is remains the same. The ramp reaches the maximum limit before reaching the expected level. Reaching the maximum limit ends the switching cycle prematurely and results in a lower maximum duty cycle. Maximum duty cycle is dependent on the Vin and switching frequency. Figure 22 is a theoretical plot of the maximum duty cycle vs. the switching frequency using typical parameter values. It shows how the maximum duty cycle is influenced by the Vin and the switching frequency. The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.5V. For Vout(min) = 0.5V, ∴ PVin × Fs ≤ ∴ PVin × Fs ≤ Vout ton (min) (7) 0.5V = 8.33V / µS 60nS Therefore, with an input voltage 16V and minimum output voltage, the converter should be designed for switching frequency not to exceed 520kHz. Conversely, the input voltage (PVin) should not exceed 5.55V for operation at the maximum recommended operating frequency (1.0MHz) and minimum output voltage (0.5V). Increasing the PVin greater than 5.55V will cause pulse skipping. 24 www.irf.com © 2014 International Rectifier Figure 22: Maximum Duty Cycle vs. Switching Frequency Submit Datasheet Feedback May 29, 2014 IR3892 DESIGN EXAMPLE The following example is a typical application for IR3892. The application circuit is shown in Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The FB pin is the inverting input of the error amplifier, which is internally referenced to VREF. The divider ratio is set to equal VREF at the FB pin when the output is at its desired value. When an external resistor divider is connected to the output as shown in Figure 24, the output voltage is defined by using the following equation: Vin = PVin = 12V (21V Max) Fs = 600kHz Channel 1: Vo = 1.8V Io = 6A Ripple Voltage = ± 1% * Vo ΔVo = ± 4% * Vo (for 30% load transient)  R  Vo = Vref × 1 + 5   R6  Channel 2: Vo = 1.2V Io = 6A Ripple Voltage = ± 1% * Vo ΔVo = ± 4% * Vo (for 30% load transient)  Vref R6 = R5 ×  V −V ref  o Enabling the IR3892 As explained earlier, the precise threshold of the Enable lends itself well to implementation of a UVLO for the Bus Voltage as shown in Figure 23. (10)     (11) For the calculated values of R5 and R6, see feedback compensation section. Vout PVin IR3892 IR3892 R1 R5 FB R6 Enable R2 Figure 23: Using Enable pin for UVLO implementation For a typical Enable threshold of VEN = 1.2 V R2 PVin (min) × = V EN = 1.2 R1 + R2 R2 = R1 V EN PVin (min) − V EN Bootstrap Capacitor Selection (8) (9) For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice. Programming the frequency For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1. 25 www.irf.com Figure 24: Typical application of the IR3892 for programming the output voltage © 2014 International Rectifier To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (C1). The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled down to ground. The capacitor charges towards Vcc through the internal bootstrap diode (Figure 25), which has a forward voltage drop VD. The voltage Vc across the bootstrap capacitor C1 is approximately given as: Vc ≅ Vcc − VD Submit Datasheet Feedback (12) May 29, 2014 IR3892 When the control FET turns on in the next cycle, the capacitor node connected to SW rises to the bus voltage Vin. However, if the value of C1 is appropriately chosen, the voltage Vc across C1 remains approximately unchanged and the voltage at the Boot pin becomes: VBoot ≅ Vin + Vcc − VD Cvin + VD - (13) Inductor Selection Inductors are selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but may reduce efficiency and cause higher output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (Δi). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: VIN Boot Vcc C1 SW IR3892 Ceramic capacitors are recommended due to their peak current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is advisable to have 4x10uF, 25V ceramic capacitors, C3216X5R1E106K from TDK. In addition to these, although not mandatory, a 1x330uF, 25V SMD capacitor EEVFK1E331P from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. + Vc L PGnd Figure 25: Bootstrap circuit to generate Vc voltage ∆i 1 ; ∆t = D × ∆t Fs Vo L = (Vin − Vo ) × Vin × ∆i × Fs Vin − Vo = L × A bootstrap capacitor of value 0.1uF is suitable for most applications. Input Capacitor Selection The ripple currents generated during the on time of the control FETs should be provided by the input capacitor. The RMS value of this ripple for each channel is expressed by: I RMS = I o × D × (1 − D ) D= Vo Vin (14) (15) Where: D is the Duty Cycle IRMS is the RMS value of the input capacitor current. Io is the output current. For channel 1, Io=6A and D=0.15, the IRMS = 2.14A. For channel 2, Io=6A and D=0.1, the IRMS = 1.8A. Where: Vin V0 Δi Fs Δt D (16) = Maximum input voltage = Output Voltage = Inductor Peak-to-Peak Ripple Current = Switching Frequency = On time for Control FET = Duty Cycle If Δi ≈ 30%*Io, then the channel 1 output inductor is calculated to be 1.42μH. Select L=1.0μH, SPM6550T1R0M100A, from TDK which provides a compact, low profile inductor suitable for this application. For channel 2, the output inductor is calculated to be 1.0μH. Select L=1.0μH, SPM6550T-1R0M100A, from TDK. Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors type and values. The criterion is normally based on the value of the 26 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components. These components can be described as: The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o. The resonant frequency of the LC filter is expressed as follows: ∆Vo = ∆Vo ( ESR ) + ∆Vo ( ESL ) + ∆Vo (C ) FLC = ∆V0 ( ESR ) = ∆I L × ESR  V −V  ∆V0 ( ESL ) =  in o  × ESL  L  ∆I L ∆V0 (C ) = 8 × Co × Fs 1 (18) 2 × π × Lo × Co Figure 26 shows gain and phase of the LC filter. Since we already have 180o phase shift from the output filter alone, the system runs the risk of being unstable. Phase Gain (17) 0dB 00 -40dB/Decade Where: ΔV0 = Output Voltage Ripple ΔIL = Inductor Ripple Current -900 -1800 Since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. The IR3892 can perform well with all types of capacitors. As a rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. Therefore it is advisable to select ceramic capacitors due to their low ESR and ESL and small size. Four of TDK C2012X5R0J226M (22uF/0805/X5R/6.3V) capacitors is a good choice for channel 1 and channel 2. It is also recommended to use a 0.1µF ceramic capacitor at the output for high frequency filtering. Feedback Compensation The IR3892 is a voltage mode controller. The control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to have a stable closed-loop transfer function with a high crossover frequency and o phase margin greater than 45 . 27 www.irf.com © 2014 International Rectifier FLC Frequency FLC Frequency Figure 26: Gain and Phase of LC filter The IR3892 uses a voltage-type error amplifier with high-gain and high-bandwidth. The output of the amplifier is available for DC gain control and AC phase compensation. The error amplifier can be compensated either in type II or type III compensation. Local feedback with Type II compensation is shown in Figure 27. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. If the output capacitor’s ESR generates a zero at 5kHz to 50kHz, the zero generates acceptable phase margin and the Type II compensator can be used. The ESR zero of the output capacitor is expressed as follows: FESR = 1 2 × π × ESR × Co Submit Datasheet Feedback (19) May 29, 2014 IR3892 VOUT Z IN FLC = Resonant Frequency of the Output Filter R5 = Feedback Resistor C POLE R3 C3 R5 Zf Fb E/A R6 Comp Ve FZ = 75% × FLC FZ = 0.75 × VREF Gain(dB) To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: 1 2 × π Lo × Co (25) H(s) dB Use equation (22), (23) and (24) to calculate C3. F FZ Frequency POLE Figure 27: Type II compensation network and its asymptotic gain plot The additional pole is given by: The transfer function (Ve/Vout) is given by: Z 1 + sR3C3 Ve = H (s) = − f = − Z IN sR5C3 Vout Fp = (20) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: H (s) = Fz = R3 R5 (21) 1 2 × π × R3 × C3 (22) First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1 / 5 ~ 1 / 10) × Fs One more capacitor is sometimes added in parallel with C3 and R3. This introduces one more pole which is mainly used to suppress the switching noise. 1 C × C POLE 2×π × 3 C3 + C POLE (26) The pole sets to one half of the switching frequency which results in the capacitor CPOLE: CPOLE = 1 1 π × R3 × FS − C3 ≅ 1 π × R3 × FS (27) For an unconditional stability general solution using any type of output capacitors with a wide range of ESR values, use local feedback with type III compensation network. Type III compensation network is typically used for voltage-mode controller as shown in Figure 28. (23) Use the following equation to calculate R3: R3 = Vramp × Fo × FESR × R5 2 Vin × FLC (24) Where: Vin = Maximum Input Voltage Vramp = Amplitude of the oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 VOUT ZIN C2 C4 R4 R3 Zf Fb R6 Ve Comp E/ A FZ 2 (33) Cross over frequency is expressed as: Fo = R3 × C 4 × VREF Gain (dB) Vin 1 × Vramp 2π × Lo × C o (34) Based on the frequency of the zero generated by the output capacitor and its ESR, relative to the crossover frequency, the compensation type can be different. Table 3 shows the compensation types for relative locations of the crossover frequency. |H(s)| dB FZ1 FZ 2 FP2 FP3 Frequency Figure 28: Type III Compensation network and its asymptotic gain plot Again, the transfer function is given by: Zf Ve = H (s) = − Z IN Vout By replacing Zin and Zf, according to Figure 28, the transfer function can be expressed as: H ( s) = − (32) C3 R5 1 2π × R3 × C3 1 1 = ≅ 2π × C 4 × (R4 × R5 ) 2π × C 4 × R5 FZ 1 = (1 + sR3C3 )[1 + sC4 (R4 + R5 )]   C × C3   (1 + sR4C4 ) sR5 (C2 + C3 )1 + sR3  2 + C C 2 3    (28) The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 (29) 1 2π × R4 × C4 1 1 FP 3 = ≅  C × C3  2π × R3 × C2  2π × R3  2  C2 + C3  FP 2 = (30) (31) Table 3: Different types of compensators Compensator Type FESR vs FO Typical Output Capacitor Type II FLC < FESR < FO < FS/2 Electrolytic Type III FLC < FO < FESR SP Cap, Ceramic The higher the crossover frequency is, the potentially faster the load transient response will be. However, the crossover frequency should be low enough to allow attenuation of switching noise. Typically, the control loop bandwidth or crossover frequency (Fo) is selected such that: Fo ≤ (1/5 ~ 1/10 )* Fs The DC gain should be large enough to provide high DC-regulation accuracy. The phase margin should be greater than 45o for overall stability. The specifications for designing channel 1: Vin = 12V Vo = 1.8V Vramp= 1.8V (This is a function of Vin, pls. see Feed-Forward section) Vref = 0.5V Lo = 1.0uH Co = 4x22uF, ESR≈3mΩ each It must be noted here that the value of the capacitance used in the compensator design must be 29 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 29, 2014 IR3892 the small signal value. For instance, the small signal capacitance of the 22uF capacitor used in this design is 15uF at 1.8 V DC bias and 600 kHz frequency. It is this value that must be used for all computations related to the compensation. The small signal value may be obtained from the manufacturer’s datasheets, design tools or SPICE models. Alternatively, they may also be inferred from measuring the power stage transfer function of the converter and measuring the double pole frequency FLC and using equation (18) to compute the small signal Co. These result to: FLC = 20.6 kHz FESR = 3.54 MHz Fs/2 = 300 kHz Select crossover frequency F0=100 kHz Since FLC