IR3898MTR1PBF

PD-97662 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator -1- FEATURES IR3898 DESCRIPTION The IR3898 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC regulator. The onboard PWM controller and MOSFETs make IR3898 a space-efficient solution, providing accurate power delivery.  Single 5V to 21V application  Wide Input Voltage Range from 1.0V to 21V with external Vcc  Output Voltage Range: 0.5V to 0.86× Vin  Enhanced Line/Load Regulation with Feed-Forward IR3898 is a versatile regulator which offers programmable switching frequency and the fixed internal current limit while operates in wide input and output voltage range.  Programmable Switching Frequency up to 1.5MHz  Internal Digital Soft-Start/Soft-Stop  Enable input with Voltage Monitoring Capability The switching frequency is programmable from 300kHz to 1.5MHz for an optimum solution.  Thermally Compensated Current Limit with robust hiccup mode over current protection  Smart Internal LDO to improve light load and full load efficiency It also features important protection functions, such as Pre-Bias startup, thermally compensated current limit, over voltage protection and thermal shutdown to give required system level security in the event of fault conditions.  External Synchronization with Smooth Clocking  Enhanced Pre-Bias Start-Up  Precision Reference Voltage (0.5V+/-0.5%) with margining capability APPLICATIONS  Vp for Tracking Applications (Source/Sink Capability +/-6A)  Netcom Applications  Integrated MOSFET drivers and Bootstrap Diode  Embedded Telecom Systems  Thermal Shut Down  Server Applications  Programmable Power Good Output with tracking capability  Storage Applications  Distributed Point of Load Power Architectures  Monotonic Start-Up  Operating temp: -40 C < Tj < 125 C o o  Small Size: 4mm x 5mm PQFN  Lead-free, Halogen-free and RoHS Compliant BASIC APPLICATION 98 5V 1V Enable >1.2V Intl_SS Figure 5a: Recommended startup for Normal operation In normal and sequencing mode operation, Vref is left floating. A 100pF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. It is recommended to apply the Enable signal after the VCC voltage has been established. If the Enable signal is present before VCC, a 50kΩ resistor can be used in series with the Enable pin to limit the current flowing into the Enable pin. Pvin (12V) PRE-BIAS STARTUP IR3898 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. Vcc Enable > 1. 2 V Intl_SS Vp Figure 5b: Recommended startup for sequencing operation (ratiometric or simultaneous) The output starts in asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 6a shows a typical Pre-Bias condition at start up. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 6b shows the series of 16x8 startup pulses. Pvin=Vin=12V [V] Vo Vcc Pre-Bias Voltage Vref=0 [Time] VDDQ Figure 6a: Pre-Bias startup Vp=VDDQ/2 Enable > 1.2V ... HDRv 12.5% VTT VTT Tracking 16 Figure 5c: Recommended startup for memory tracking operation (VTT-DDR4) 19 JANURARY 18, 2013 | DATA SHEET | Rev 3.5 ... 25% ... LDRv ... ... ... 16 ... 87.5% ... ... ... Figure 6b: Pre-Bias startup pulses End of PB PD-97662 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator - 20 - IR3898 TABLE 1: SWITCHING FREQUENCY (FS) VS. EXTERNAL RESISTOR (RT) SOFT-START IR3898 has an internal digital soft-start to control the output voltage rise and to limit the current surge at the start-up. To ensure correct start-up, the soft-start sequence initiates when the Enable and Vcc rise above their UVLO thresholds and generate the Power On Ready (POR) signal. The internal soft-start (Intl_SS) signal linearly rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7 shows the waveforms during soft start (also refer to Fig. 20). The normal Vout start-up time is fixed, and is equal to: Tstart   0.65V-0.15V   2.5ms(1) 0.2mV/s During the soft start the over-current protection (OCP) and over-voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. POR 3.0V 1.5V 0.65V 0.15V Intl_SS Vout t1 t 2 t3 Figure 7: Theoretical operation waveforms during soft-start (non tracking / non sequencing) OPERATING FREQUENCY The switching frequency can be programmed between 300kHz – 1500kHz by connecting an external resistor from Rt pin to Gnd. Table 1 tabulates the oscillator frequency versus Rt. SHUTDOWN IR3898 can be shut down by pulling the Enable pin below its 1.0V threshold. This will tri-state both the high side and the low side driver. 20 JANURARY 18, 2013 | DATA SHEET | Rev 3.5 Rt (KΩ) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 21 19.1 17.4 16.2 15 Freq (KHz) 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 OVER CURRENT PROTECTION The over current (OC) protection is performed by sensing current through the RDS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The current limit is pre-set internally and is compensated according to the IC temperature. So at different ambient temperature, the over-current trip threshold remains almost constant. Note that the over current limit is a function of the Vcc voltage. Refer to the typical performance curves of the OCP current limit with the internal LDO and the external Vcc voltage. Detailed operation of OCP is explained as follows. Over Current Protection circuit senses the inductor current flowing through the Synchronous MOSFET closer to the valley point. OCP circuit samples this current for 40nsec typically after the rising edge of the PWM set pulse which has a width of 12.5% of the switching period.The PWM pulse starts at the falling edge of the PWM set pulse.This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters into hiccup mode. PGood will go low and the internal soft start signal will be pulled low. The converter goes into hiccup mode with a 20.48ms (typ.) delay as shown in Figure 8. The convertor stays in this mode until the over load or short circuit is removed. The actual DC output current limit point will be greater PD-97662 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator - 21 than the valley point by an amount equal to approximately half of peak to peak inductor ripple current. i 2 IOCP= DC current limit hiccup point ILIMIT= Current limit Valley Point Δi=Inductor ripple current IOCP  ILIMIT  (2) Current Limit Hiccup 20.48ms IR3898 frequency, a transition from the free-running frequency to the external clock frequency will happen. This transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. On the contrary, when the external clock signal is removed from Rt/Sync pin, the switching frequency is also changed to free-running gradually. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin as shown in Figure 9a. Figure 9b shows the timing diagram of these transitions. IL IR3898 0 HDrv Rt/Sync ... Gnd 0 LDrv ... 0 PGood 0 Figure 8: Timing Diagram for Current Limit and Hiccup Figure 9a: Configuration of External Synchronization THERMAL SHUTDOWN Temperature sensing is provided inside IR3898. The trip o threshold is typically set to 145 C. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. Automatic restart is initiated when the sensed temperature drops within the operating range. There is o a 20 C hysteresis in the thermal shutdown threshold. EXTERNAL SYNCHRONIZATION IR3898 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (POL) regulators are used. A multi-function pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock signal solely and no other resistor is needed. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free-running frequency, an external resistor from Rt/Sync pin to Gnd is required to set the free-running frequency. When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its free-running 21 JANURARY 18, 2013 | DATA SHEET | Rev 3.5 Synchronize to the external clock Free Running Frequency Return to freerunning freq ... SW Gradually change Gradually change ... Fs1 SYNC Fs1 Fs2 Figure 9b: Timing Diagram for Synchronization to the external clock (Fs1>Fs2 or Fs1 0 on LDrv falling edge in a switching cycle. If this case happens for consecutive 256 switching cycles, the smart LDO reduces its output to 4.4. If in any one of the 256 cycles, Vsw < 0 on LDrv falling edge, the counter is reset and LDO voltage doesn’t change. On the other hand, if Vsw < 22 JANURARY 18, 2013 | DATA SHEET | Rev 3.5 Figure 11b: Internally Biased Single Rail Operation Ext VCC Vin Vin PVin IR3898 VCC/ LDO_OUT PGnd Figure 11c: Use External Bias Voltage When the Vin voltage is below 6.8V, the internal LDO enters the dropout mode at medium and heavy load. The dropout voltage increases with the switching frequency. Figure 11d PD-97662 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator - 23 shows the LDO voltage for 600 kHz and 1500 kHz switching frequency respectively. IR3898 In sequencing mode of operation (simultaneous or ratiometric), Vref is left floating and Vp is kept to ground level until Intl_SS signal reaches the final value. Then Vp is ramped up and Vfb follows Vp. When Vp>0.5V the error-amplifier switches to Vref and the output voltage is regulated with Vref.The final Vp voltage after sequencing startup should between 0.7V ~ 3.3V. 5 V RC/RD RE/RF =RC/RD RE/RF >RC/RD 0.85*Vp 0 0.9*Vp OVP Latch PGood JANURARY 18, 2013 | DATA SHEET | Rev 3.5 0 1.28ms 1.28ms Figure 15: Non-sequence, Non-tracking Startup and Vref Margin (Vp pin floating) PD-97662 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator - 25 0.4V 0.3V Vp 0 1.2*Vp Vsns IR3898 and Fig 18b. If either of the above conditions is not satisfied, OVP is disabled. Vsns voltage is set by the voltage divider connected to the output and it can be programmed externally. Figure 18c shows the timing diagram for OVP in non-tracking mode. 0.9*Vp En 0 1.2V PGood 1.0V 0 1.28ms Vref Figure 16: Vp Tracking (Vref =0V) 0.2V Internal SS OVP active region 0 Vref 0 0.5V (0.7V