IRDC3897

IRDC3897-P1V2 SupIRBuck TM USER GUIDE FOR IR3897 EVALUATION BOARD 1.2Vout DESCRIPTION The IR3897 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm X 5 mm Power QFN package. Key features offered by the IR3897 include internal Digital Soft Start/Soft Stop, precision 0.5Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias startup. Output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous Mosfet for optimum cost and performance and the current limit is thermally compensated. This user guide contains the schematic and bill of materials for the IR3897 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3897 is available in the IR3897 data sheet. BOARD FEATURES • Vin = +12V (+ 13.2V Max) •Vout = +1.2V @ 0- 4A • Fs=600kHz • L= 1.5uH • Cin= 2x10uF (ceramic 1206) + 1X330uF (electrolytic) • Cout=4x22uF (ceramic 0805) 12/5/2012 1 IRDC3897-P1V2 CONNECTIONS and OPERATING INSTRUCTIONS A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 4A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I. IR3897 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDO_Out pins should be shorted together for external Vcc operation. The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero ohm resistor for R21). The value of R14 and R20 can be selected to provide the desired tracking ratio between output voltage and the tracking input. Table I. Connections Connection Signal Name VIN+ Vin (+12V) VIN- Ground of Vin Vout+ Vout(+1.2V) Vout- Ground for Vout Vcc+ Vcc/ LDO_Out Pin Vcc- Ground for Vcc input Enable Enable PGood Power Good Signal AGnd Analog ground LAYOUT The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB thickness is 0.062”. The IR3897 and other major power components are mounted on the top side of the board. Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3897. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path. 12/5/2012 2 IRDC3897-P1V2 Connection Diagram Vin Gnd Gnd Vout Enable VDDQ Top View Vref Sync S-Ctrl AGnd PGood Vsns Vcc+ Vcc- Bottom View Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards 12/5/2012 3 IRDC3897-P1V2 Fig. 2: Board Layout-Top Layer Single point connection between AGnd and PGnd Fig. 3: Board Layout-Bottom Layer 12/5/2012 4 IRDC3897-P1V2 Fig. 4: Board Layout-Mid Layer 1 Fig. 5: Board Layout-Mid Layer 2 12/5/2012 5 Vcc- PGood C10 N/A 49.9K R17 Vcc+ N/S R28 VCC R14 0 ohm Agnd VDDQ R1 SYNC 3.01k R9 39.2K 100pF C12 1 10nF 0 ohm R13 C23 2.2uF VCC S_Ctrl Vp Rt_Sy nc Gnd COMP C32 1.0uF IR3897 R7 R10 R4 PGnd SW PVin R3 2.37K R2 3.32K C24 N38703 C7 0.1uF 0.1uF Vsns PGND C8 11 12 13 0 ohm N/S R29 VCC R15 A 20 ohm R6 R12 2.37K N/S B 3.32K R11 1.5uH L1 0 ohm C25 100 ohm 2200pF N/A R18 49.9K N/S N/S 0 ohm R50 + C35 N/S C29 C30 + C36 N/S N/S C28 N/S C4 10uF C3 N/S N/S C20 N/S C19 22uF C18 C17 22uF 22uF C16 22uF C15 1 1 1 1 1 1 Vout+ Vout+ (1.2V) Vin- Vin- Vin+ Vin+ 1 Vout- 1 C14 0.1uFVout- Vout C1 + N/S 330uF/25V C2 Input ceramic: 1206 C5 10uF C6 N/A C27 Fig. 6: Schematic of the IR3897 evaluation board 6 16 5 4 3 1 FB N/S U1 C37 R19 7.5K S_Ctrl VREF C26 120pF C11 R21 N/S 1 2 VREF 1 15 Enable 1 1 1 9 Vin PGood 7 Vsns 8 GND 17 Vcc/LDO_OUT 10 14 Boot Enable 1 1 1 1 1 1 12/5/2012 1 Vin IRDC3897-P1V2 6 IRDC3897-P1V2 Bill of Materials Item Qty Part Reference Value Description Manufacturer Part Number 1 1 C1 330uF SMD Electrolytic F size 25V 20% Panasonic EEV-FK1E331P 2 2 C4 C5 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M 3 3 C7 C14 C24 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA0 1B 4 1 C12 100pF 0603,50V,NP0, 5% Murata GRM1885C1H101JA01D 5 1 C8 2200p F 0603,50V,X7R Murata GRM188R71H222KA0 1B 6 1 C11 120pF 0603, 50V, NP0, 5% Murata GRM1885C1H121JA0 1D 7 4 C15 C16 C17 C18 22uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J226M 8 1 C23 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M 9 1 C26 10nF Murata GRM188R71E103KA0 1J 10 1 C32 1.0uF Murata GRM188R61E105KA1 2D 11 1 L1 1.5uH SMD 7.05x6.6x4.8mm,6.7mΩ Cyntec PCMB065T-1R5MS 12 1 R1 3.01K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3011V 13 2 R2 R11 3.32K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V 14 2 R3 R12 2.37K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2371V 15 1 R4 100 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V 16 1 R6 20 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF20R0V 17 1 R9 39.2K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V 18 5 R10 R13 R14 R15 R50 0 Panasonic ERJ-3GEY0R00V 19 2 R17 R18 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V 20 1 R19 7.5K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7501V 21 1 U1 IR389 7 PQFN 4x5mm IR IR3897MPBF 12/5/2012 0603, 25V, X7R, 10% 0603, 25V, X5R, 10% Thick Film, 0603,1/10W 7 IRDC3897-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no airflow Fig. 7: Start up at 4A Load Ch1:Vin, Ch2:Vo, Ch3:PGood Ch4:Enable Fig. 9: Start up with 1V Pre Bias , 0A Load, Ch2:Vo Fig. 11: Inductor node at 4A load Ch2:LX 12/5/2012 Fig. 8: Start up at 4A Load, Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood Fig. 10: Output Voltage Ripple, 4A load Ch2: Vout , Fig. 12: Short circuit (Hiccup) Recovery Ch2:Vout , Ch4:Iout 8 IRDC3897-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no air flow Fig. 13: Transient Response, 2.0A to 4A step Ch4-Iout Ch2:Vout 12/5/2012 9 IRDC3897-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no air flow Fig. 14: Bode Plot at 4A load shows a bandwidth of 112.6KHz and phase margin of 52.4 degrees 12/5/2012 10 IRDC3897-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no air flow Fig (15) Soft start and soft stop using S_Ctrl pin Fig (16) Feed Forward for Vin change from 7 to 16V and back to 7V Ch2-Vout Ch4-Vin 12/5/2012 11 IRDC3897-P1V2 TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, no air flow 90 88 86 Efficiency (%) 84 82 80 78 76 74 72 70 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 3.6 4 Load Current (A) Fig.17: Efficiency versus load current 0.775 0.700 Power Dissipation(W) 0.625 0.550 0.475 0.400 0.325 0.250 0.175 0.100 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 Load Current (A) Fig.18: Power loss versus load current 12/5/2012 12 IRDC3897-P1V2 THERMAL IMAGES Vin=12.0V, Vo=1.2V, Io=0-4A, Room Temperature, No Air flow Fig. 19: Thermal Image of the board at 4A load Test point 1 is IR3897 Test point 2 is inductor 12/5/2012 13 IRDC3897-P1V2 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 20: PCB Metal Pad Spacing (all dimensions in mm) 12/5/2012 14 IRDC3897-P1V2 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 21: Solder resist 12/5/2012 15 IRDC3897-P1V2 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses. Figure 22: Stencil Pad Spacing (all dimensions in mm) 12/5/2012 16 IRDC3897-P1V2 PACKAGE INFORMATION Figure 23: Package Dimensions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice.12/11 12/5/2012 17