IRF1407SPbF
IRF1407LPbF
Benefits
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
HEXFET® Power MOSFET
Description
Advanced HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized device
design that HEXFET power MOSFETs are well known for,
provides the designer with an extremely efficient and reliable
device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the highest
power capability and the lowest possible on-resistance in any
existing surface mount package. The D2Pak is suitable for high
current applications because of its low internal connection
resistance and can dissipate up to 2.0W in a typical surface
mount application.
The through-hole version (IRF1407L) is available for low-profile
applications.
Base part number
Package Type
IRF1407LPbF
TO-262
IRF1407SPbF
Absolute Maximum Ratings
Symbol
Tape and Reel Left
75V
RDS(on)
0.0078
ID
100A
D
D
S
D
S
G
G
TO-262 Pak
IRF1407LPbF
D2 Pak
IRF1407SPbF
G
Gate
D
Drain
Standard Pack
Form
Quantity
Tube
50
D2-Pak
VDSS
S
Source
Orderable Part Number
IRF1407LPbF (Obsolete)
800
IRF1407STRLPbF
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
100
ID @ TC = 100°C
IDM
PD @TA = 25°C
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Maximum Power Dissipation
70
520
3.8
W
PD @TC = 25°C
Maximum Power Dissipation
200
W
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Symbol
RJC
RJA
1
Parameter
Junction-to-Case
Junction-to-Ambient ( PCB Mount, steady state)
A
1.3
± 20
390
See Fig.15,16, 12a, 12b
4.6
-55 to + 175
W/°C
V
mJ
A
mJ
V/ns
°C
300
10 lbf•in (1.1N•m)
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
2016-5-26
IRF1407S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Trans conductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
75
–––
–––
2.0
74
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
IGSS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Coss
Output Capacitance
Coss
Output Capacitance
Effective Output Capacitance
Coss eff.
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
IS
(Body Diode)
Pulsed Source Current
ISM
(Body Diode)
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
ton
Forward Turn-On Time
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
–––
–––
V VGS = 0V, ID = 250µA
0.09 ––– V/°C Reference to 25°C, ID = 1mA
––– 0.0078 VGS = 10V, ID = 78A
–––
4.0
V VDS = VGS, ID = 250µA
–––
–––
S VDS = 25V, ID = 78A
–––
20
VDS =75 V, VGS = 0V
µA
–––
250
VDS = 60V,VGS = 0V,TJ =150°C
–––
200
VGS = 20V
nA
-200
VGS = -20V
160
250
ID = 78A
nC VDS = 60V
35
52
VGS = 10V
54
81
11
–––
VDD = 38V
150
–––
ID =78A
ns
150
–––
RG= 2.5
VGS = 10V
140
–––
Between lead,
4.5
–––
6mm (0.25in.)
nH
from package
7.5
–––
and center of die contact
5600 –––
VGS = 0V
890
–––
VDS = 25V
ƒ = 1.0kHz, See Fig. 5
190
–––
pF
5800 –––
VGS = 0V, VDS = 1.0V ƒ = 1.0kHz
560
–––
VGS = 0V, VDS = 60V ƒ = 1.0kHz
1100 –––
VGS = 0V, VDS = 0V to 60V
Min.
Typ.
Max. Units
–––
–––
100
–––
–––
520
–––
–––
–––
–––
110
390
1.3
170
590
Conditions
MOSFET symbol
showing the
A
integral reverse
p-n junction diode.
V TJ = 25°C,IS = 78A,VGS = 0V
ns TJ = 25°C ,IF = 78A
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
starting TJ = 25°C, L = 0.13mH, RG = 25, IAS = 78A, VGS =10V. (See fig. 12)
ISD 78A, di/dt 320A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
Uses IRF1407 data and test conditions.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994
2
2016-5-26
IRF1407S/LPbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
4.5V
10
20µs PULSE WIDTH
Tj = 25°C
100
10
20µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
0.1
100
1
1000.00
3.0
20µs PULSE WIDTH
5.0
7.0
9.0
11.0
13.0
VGS, Gate-to-Source Voltage (V)
Fig. 3 Typical Transfer Characteristics
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current)
VDS = 25V
3.0
I D = 130A
2.5
TJ = 175°C
100.00
10.00
100
Fig. 2 Typical Output Characteristics
Fig. 1 Typical Output Characteristics
TJ = 25°C
10
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
3
4.5V
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ, Junction Temperature
80
100
120
140
160
180
( °C)
Fig. 4 Normalized On-Resistance
vs. Temperature
2016-5-26
IRF1407S/LPbF
100000
15
VGS = 0V,
f = 1 kHZ
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
10000
Ciss
Coss
Crss
100
1
10
9
6
3
0
100
0
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
120
160
200
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
80
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000.00
T J = 175°C
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
10.00
100
T J = 25°C
1.00
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.10
1
0.0
1.0
2.0
VSD , Source-toDrain Voltage (V)
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
4
40
QG, Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
100.00
VDS = 60V
VDS = 37V
VDS = 15V
12
Coss = Cds + Cgd
1000
ID = 78A
3.0
1
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
2016-5-26
IRF1407S/LPbF
120
LIMITED BY PACKAGE
100
ID , Drain Current (A)
80
60
40
Fig 10a. Switching Time Test Circuit
20
0
25
50
75
100
125
150
175
( °C)
TC, Case Temperature
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10b. Switching Time Waveforms
1
(Z thJC)
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty f actor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t
2
J = P DM x Z thJC
+T C
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5
2016-5-26
IRF1407S/LPbF
15V
650
L
VDS
ID
DRIVER
TOP
IAS
20V
+
V
- DD
A
0.01
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
520
D.U.T
RG
32A
55A
78A
BOTTOM
390
260
130
0
25
50
75
100
125
Starting T , Junction
Temperature
J
150
175
( °C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Fig 13a. Gate Charge Waveform
VGS(th) Gate threshold Voltage (V)
3.5
3.0
ID = 250µA
2.5
2.0
1.5
-75 -50 -25
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
Fig 14. Threshold Voltage vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
2016-5-26
IRF1407S/LPbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses
0.01
100
0.05
0.10
10
1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs. Pulse width
EAR , Avalanche Energy (mJ)
400
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 78A
300
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
175
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy
vs. Temperature
7
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IRF1407S/LPbF
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
8
2016-5-26
IRF1407S/LPbF
D2-Pak (TO-263AB) Package Outline (Dimensions are shown in millimeters (inches))
D2-Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
ASSEMBLY
LOT CODE
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
9
2016-5-26
IRF1407S/LPbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
ASSEMBLED ON WW19, 1997
IN THE ASSEMBLYLINE "C"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
10
2016-5-26
IRF1407S/LPbF
D2-Pak (TO-263AB) Tape & Reel Information (Dimensions are shown in millimeters (inches))
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
11
2016-5-26
IRF1407S/LPbF
Qualification Information†
Qualification Level
Moisture Sensitivity Level
D2-Pak
TO-262
RoHS Compliant
Industrial
(per JEDEC JESD47F) ††
MSL1
(per JEDEC J-STD-020D) ††
N/A
Yes
†
Qualification standards can be found at Infineon’s web site www.infineon.com
††
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
4/20/2016
5/26/2016
Comments
Updated datasheet with corporate template.
Corrected typo on Fig. 3 from VDS =15V to VDS = 25V on page 3.
Corrected typo on Fig. 5 from f = 1MHz to 1kHz on page 4.
Updated Package outline on pages 9,10.
Added disclaimer on last page.
TO-262 package was removed from ordering information since it is EOL on page 1.
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU‐ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI‐POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my‐d™, NovalithIC™, OPTIGA™,
Op MOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO‐SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respec ve owners.
Edi on 2016‐04‐19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a ques on about this
document?
Email: erratum@infineon.com
Document reference
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12
IMPORTANT NOTICE
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event be regarded as a guarantee of condi ons or
characteris cs (“Beschaffenheitsgaran e”) .
With respect to any examples, hints or any typical
values stated herein and/or any informa on
regarding the applica on of the product, Infineon
Technologies hereby disclaims any and all
warran es and liabili es of any kind, including
without limita on warran es of non‐infringement
of intellectual property rights of any third party.
In addi on, any informa on given in this document
is subject to customer’s compliance with its
obliga ons stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applica ons.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended applica on and the completeness of the
product informa on given in this document with
respect to such applica on.
For further informa on on the product, technology,
delivery terms and condi ons and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Please note that this product is not qualified
according to the AEC Q100 or AEC Q101 documents
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WARNINGS
Due to technical requirements products may
contain dangerous substances. For informa on on
the types in ques on please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a wri en document signed by
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Infineon Technologies’ products may not be used in
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2016-5-26
