IRF7811APBF

IRF7811APBF

  • 厂商:

    EUPEC(英飞凌)

  • 封装:

    SO-8

  • 描述:

    MOSFET N-CH 28V 11A 8-SOIC

  • 数据手册
  • 价格&库存
IRF7811APBF 数据手册
PD - 95264B IRF7811APbF Applications High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l 100% RG Tested l Lead-Free HEXFET® Power MOSFET l Benefits l l l Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current VDSS RDS(on) max Qg 12mΩ 17nC 28V A A D S 1 8 S 2 7 D S 3 6 D G 4 5 D SO-8 Top View Absolute Maximum Ratings Symbol Parameter ID @ TA = 25°C Continuous Drain Current, VGS @ 10V ID @ TA = 70°C IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TA = 25°C Power Dissipation PD @TA = 70°C Power Dissipation VGS Linear Derating Factor Gate-to-Source Voltage TJ Operating Junction and TSTG Storage Temperature Range f f Max c Smoldering Temperature, for 10 seconds Units f 9.1 f 11 A 91 2.5 W 1.6 0.02 ±12 W/°C V -55 to + 150 °C 300 (1.6mm from case) Thermal Resistance Symbol RθJL RθJA Parameter g Junction-to-Ambient fg Junction-to-Drain Lead Notes  through … are on page 10 www.irf.com Typ Max ––– 20 ––– 50 Units °C/W 1 01/09/08 IRF7811APbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units BVDSS ∆ΒVDSS/∆TJ Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) ∆VGS(th) Gate Threshold Voltage Gate Threshold Voltage Coefficient IDSS Drain-to-Source Leakage Current IGSS Conditions 28 ––– ––– ––– ––– 0.025 8.7 10 ––– ––– 10 12 V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA VGS = 10V, ID = 11A mΩ VGS = 4.5V, ID = 9.0A 1.0 ––– ––– -4.0 3.0 ––– Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage ––– ––– ––– ––– ––– ––– ––– ––– V VDS = VGS, ID = 250µA mV/°C VDS = 28V, VGS = 0V 12 µA VDS = 24V, VGS = 0V, TJ = 100°C 150 VGS = 12V 100 nA VGS = -12V -100 gfs Qg Qgs1 Qgs2 Forward Transconductance Total Gate Charge Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge 28 ––– ––– ––– ––– 17 3.3 1.3 ––– 26 ––– ––– Qgd Qgodr Qsw Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– ––– ––– 4.7 7.2 6.0 ––– ––– ––– Qoss RG td(on) Output Charge Gate Resistance Turn-On Delay Time ––– 0.9 ––– 24 ––– 7.5 ––– 3.7 ––– tr td(off) tf Ciss Rise Time Turn-Off Delay Time Fall Time Input Capacitance ––– ––– ––– ––– 4.1 19 6.5 1760 ––– ––– ––– ––– Coss Crss Output Capacitance Reverse Transfer Capacitance ––– ––– 960 54 ––– ––– f f S nC nC VDS = 15V, ID = 9.0A VDS = 15V VGS = 4.5V ID = 9.0A See Fig. 16 VDS = 16V, VGS = 0V Ω VDD = 15V, VGS = 4.5V ns f ID = 9.0A Clamped Inductive Load VGS = 0V pF VDS = 15V ƒ = 1.0MHz Avalanche Characteristics Symbol EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current c Max. 58 9.0 Typ. ––– ––– d Units mJ A Diode Characteristics Symbol Parameter Min. Typ. Max. Units IS Continuous Source Current (Body Diode) ––– ––– 11 ISM Pulsed Source Current (Body Diode) ––– ––– 91 VSD Diode Forward Voltage trr Qrr trr Qrr 2 c A ––– 0.8 1.0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Time ––– ––– ––– ––– 0.66 72 93 73 ––– 110 140 110 ns nC ns Reverse Recovery Charge ––– 100 150 nC V Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C, IS = 9.0A, VGS = 0V e e TJ = 125°C, IS = 9.0A, VGS = 0V TJ = 25°C, IF = 9.0A, VR = 15V di/dt = 100A/µs e TJ = 125°C, IF = 9.0A, VR = 15V di/dt = 100A/µs e www.irf.com IRF7811APbF 100 10 1 0.1 20µs PULSE WIDTH Tj = 25°C 1.5V 0.01 0.1 1 10 10 1 1.5V 0.1 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100.00 2.0 T J = 150°C 10.00 1.00 T J = 25°C 0.10 VDS = 15V 20µs PULSE WIDTH ID = 11A VGS = 10V 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (Α) 20µs PULSE WIDTH Tj = 150°C 0.1 100 VDS, Drain-to-Source Voltage (V) 0.01 VGS 10V 4.5V 3.5V 2.7V 2.5V 2.0V 1.8V BOTTOM 1.5V TOP 10V 4.5V 3.5V 2.7V 2.5V 2.0V 1.8V BOTTOM 1.5V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 VGS 1.0 0.5 1.4 1.8 2.2 2.6 3.0 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 3.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF7811APbF 100000 ID= 9.0A VGS , Gate-to-Source Voltage (V) Coss 10000 C, Capacitance (pF) 12 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd = Cds + Cgd Ciss 1000 Coss 100 Crss 8 6 4 2 0 10 1 10 0 100 20 30 40 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100.0 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 10 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) OPERATION IN THIS AREA LIMITED BY RDS(on) 100 10.0 T J = 150°C T J = 25°C 1.0 10 1 0.1 0.1 0.2 0.4 0.6 0.8 1.0 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 1.2 100µsec 1msec VGS = 0V 4 VDS=1 5V 10 10msec Tc = 25°C Tj = 150°C Single Pulse 0 1 10 100 1000 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF7811APbF 12 VDS ID , Drain Current (A) 10 VGS D.U.T. RG 8 RD + -V DD 10V 6 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 4 Fig 10a. Switching Time Test Circuit 2 VDS 90% 0 25 50 75 100 125 150 T J , Junction Temperature (°C) 10% VGS Fig 9. Maximum Drain Current Vs. Ambient Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJA ) 100 D = 0.50 0.20 10 0.10 0.05 PDM 0.02 1 t1 0.01 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA SINGLE PULSE (THERMAL RESPONSE) 0.1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 0.013 0.011 R DS(on) , Drain-to -Source On Resistance ( Ω) RDS (on) , Drain-to-Source On Resistance ( Ω) IRF7811APbF VGS = 4.5V 0.009 VGS = 10V 0.007 0.005 0 10 20 30 40 50 0.03 0.02 ID = 9.0A 0.01 0.00 2.0 60 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VGS, Gate -to -Source Voltage (V) ID , Drain Current (A) Fig 12. On-Resistance Vs. Drain Current Fig 13. On-Resistance Vs. Gate Voltage Current Regulator Same Type as D.U.T. 50KΩ .2µF .3µF 140 + V - DS D.U.T. EAS, Single Pulse Avalanche Energy (mJ) 12V VGS 3mA IG ID Current Sampling Resistors Fig 14. Basic Gate Charge Test Circuit 15V V(BR)DSS tp L VDS D.U.T RG IAS 20V I AS tp DRIVER 120 BOTTOM ID 4.0A 7.2A 9.0A 100 80 60 40 20 0 + V - DD 0.01Ω Fig 15a&b. Unclamped Inductive Test circuit and Waveforms 6 TOP A 25 50 75 100 125 150 Starting TJ , Junction Temperature (°C) Fig 15c. Maximum Avalanche Energy Vs. Drain Current www.irf.com IRF7811APbF D.U.T Driver Gate Drive P.W. + ƒ + ‚ „ * D.U.T. ISD Waveform Reverse Recovery Current +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - - D= Period VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF7811APbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgs 2 ⎞ ⎛ ⎞ Qgd +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎠ ⎝ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRF7811APbF SO-8 Package Outline Dimensions are shown in millimeters (inches) ' ',0 %  $          $ + >@ ( ;E >@ $ $       F '         ( H   %$6,&   %$6,& H + %$6,&   %$6,&   . /         \ ƒ ƒ ƒ ƒ $ .[ƒ & \ >@ ;/ ;F  & $ % 127(6 ',0(16,21,1* 72/(5$1&,1*3(5$60(,1&+(6@ 287/,1(&21)250672-('(&287/,1(06$$ ',0(16,21'2(6127,1&/8'(02/'3527586,216 02/'3527586,21612772(;&(('>@ ',0(16,21'2(6127,1&/8'(02/'3527586,216 02/'3527586,21612772(;&(('>@ ',0(16,21,67+(/(1*7+2)/($')2562/'(5,1*72 $68%675$7( )22735,17 ;>@ >@ ;>@ SO-8 Part Marking (;$03/(7+,6,6$1,5) 026)(7 ,17(51$7,21$/ 5(&7,),(5 /2*2 0,//,0(7(56 0,1 0$;   $  E  ; H H ,1&+(6 0,1 0$;   ;;;; ) ;>@ '$7(&2'(
IRF7811APBF 价格&库存

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