PD - 95213A
IRF7821PbF
HEXFET® Power MOSFET
Applications
l High Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
l Lead-Free
Benefits
l Very Low RDS(on) at 4.5V VGS
l Low Gate Charge
l Fully Characterized Avalanche Voltage
and Current
VDSS
RDS(on) max
Qg(typ.)
30V
9.1mW@VGS= 10V
9.3nC
A
A
D
S
1
8
S
2
7
D
S
3
6
D
G
4
5
D
SO-8
Top View
Absolute Maximum Ratings
Parameter
Max.
Units
30
V
VDS
Drain-to-Source Voltage
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
13.6
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
100
PD @TA = 25°C
Power Dissipation
2.5
PD @TA = 70°C
Power Dissipation
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
ID @ TA = 25°C
ID @ TA = 70°C
f
f
± 20
A
11
c
W
1.6
0.02
-55 to + 155
W/°C
°C
Thermal Resistance
Parameter
RθJL
RθJA
g
fg
Junction-to-Ambient
Junction-to-Drain Lead
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes through
are on page 10
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1
05/23/07
IRF7821PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
Min. Typ. Max. Units
30
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
0.025
7.0
–––
9.1
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 13A
Gate Threshold Voltage
–––
1.0
9.5
–––
12.5
–––
VGS = 4.5V, ID = 10A
VDS = VGS, ID = 250µA
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
- 4.9
–––
–––
1.0
Gate-to-Source Forward Leakage
–––
–––
–––
–––
150
100
nA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = 20V
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
22
–––
–––
-100
–––
S
VGS = -20V
VDS = 15V, ID = 10A
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
9.3
2.5
14
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
0.8
2.9
–––
–––
Qgodr
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
3.1
3.7
–––
–––
Qoss
td(on)
Output Charge
Turn-On Delay Time
–––
–––
6.1
6.3
–––
–––
tr
td(off)
Rise Time
Turn-Off Delay Time
–––
–––
2.7
9.7
–––
–––
tf
Ciss
Fall Time
Input Capacitance
–––
–––
7.3
1010
–––
–––
Coss
Crss
Output Capacitance
Reverse Transfer Capacitance
–––
–––
360
110
–––
–––
RDS(on)
VGS(th)
∆VGS(th)
IDSS
IGSS
gfs
Qg
Qgs1
Qgs2
Qgd
V
Conditions
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
e
e
mV/°C
µA VDS = 24V, VGS = 0V
VDS = 15V
nC
VGS = 4.5V
ID = 10A
See Fig. 16
nC
ns
VDS = 10V, VGS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 10A
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
c
Typ.
–––
–––
dh
Max.
44
10
Units
mJ
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
3.1
ISM
(Body Diode)
Pulsed Source Current
–––
–––
100
VSD
trr
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
–––
–––
–––
28
1.0
42
V
ns
Qrr
Reverse Recovery Charge
–––
23
35
nC
2
ch
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 10A, VGS = 0V
TJ = 25°C, IF = 10A, VDD = 20V
di/dt = 100A/µs
e
e
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IRF7821PbF
100
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
100
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
TOP
10
1
2.5V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
2.5V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
0.1
0.1
1
10
0.1
100
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
TJ = 150°C
10.0
T J = 25°C
1.0
VDS = 15V
20µs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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ID = 13A
VGS = 10V
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
100.0
ID, Drain-to-Source Current (Α)
1
1.0
0.5
6.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7821PbF
10000
12
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
VGS , Gate-to-Source Voltage (V)
ID= 10A
C, Capacitance (pF)
Crss = Cgd
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
8
6
4
2
0
10
1
10
0
100
5
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100.0
1.0
T J = 25°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
10
1
0.1
0.1
1.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
1.5
100µsec
1msec
VGS = 0V
0.5
20
100
T J = 150°C
0.0
15
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10.0
10
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
4
VDS= 24V
VDS= 15V
10
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
0.1
1.0
10.0
100.0
1000.0
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7821PbF
2.6
VGS(th) Gate threshold Voltage (V)
14
ID , Drain Current (A)
12
10
8
6
4
2
2.2
1.8
ID = 250µA
1.4
1.0
0
25
50
75
100
125
-75
150
-50
-25
25
50
75
100
125
150
T J , Temperature ( °C )
T J , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
0
Fig 10. Threshold Voltage Vs. Temperature
100
Thermal Response ( Z thJA )
D = 0.50
0.20
10
0.10
0.05
0.02
0.01
1
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
30
100
ID = 13A
25
20
15
T J = 125°C
10
T J = 25°C
5
0
2.0
4.0
6.0
8.0
10.0
VGS, Gate-to-Source Voltage (V)
EAS, Single Pulse Avalanche Energy (mJ)
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRF7821PbF
ID
4.5A
TOP
8.0A
BOTTOM 10A
80
60
40
20
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12. On-Resistance Vs. Gate Voltage
LD
VDS
15V
L
VDS
VDD
DRIVER
D.U.T
D.U.T
RG
VGS
20V
+
V
- DD
IAS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
A
0.01Ω
tp
Fig 13a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 14a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 13b. Unclamped Inductive Waveforms
6
td(on)
tf
td(off)
tr
Fig 14b. Switching Time Waveforms
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IRF7821PbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Current Regulator
Same Type as D.U.T.
Id
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Qgs1 Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 16. Gate Charge Test Circuit
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Fig 17. Gate Charge Waveform
7
IRF7821PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
8
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF7821PbF
SO-8 Package Details
Dimensions are shown in milimeters (inches)
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