IRFB3306GPBF

PD - 96211 IRFB3306GPbF HEXFET® Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits G D Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free S VDSS RDS(on) typ. max. ID (Silicon Limited) 60V 3.3m: 4.2m: 160A ID (Package Limited) 120A c D G D S TO-220AB IRFB3306GPbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C VGS Parameter Max. 160 110 120 620 230 1.5 ± 20 14 -55 to + 175 d Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw f dv/dt TJ TSTG Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy d e d Units c c Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) A W W/°C V V/ns °C 300 x x 10lbf in (1.1N m) 184 See Fig. 14, 15, 22a, 22b, mJ A mJ Thermal Resistance Symbol RθJC RθCS RθJA www.irf.com Parameter j Junction-to-Case Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 Typ. Max. Units ––– 0.50 ––– 0.65 ––– 62 °C/W 1 01/06/09 IRFB3306GPbF Static @ TJ = 25°C (unless otherwise specified) Symbol V(BR)DSS Parameter Min. Typ. Max. Units Drain-to-Source Breakdown Voltage V Conditions 60 ––– ––– ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.07 ––– V/°C Reference to 25°C, ID = 5mA mΩ VGS = 10V, ID = 75A RDS(on) Static Drain-to-Source On-Resistance ––– 3.3 4.2 VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V IDSS Drain-to-Source Leakage Current ––– ––– 20 µA ––– ––– 250 Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 Internal Gate Resistance ––– 0.7 ––– IGSS RG VGS = 0V, ID = 250µA g d VDS = VGS, ID = 150µA VDS = 60V, VGS = 0V VDS = 48V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 230 ––– ––– S VDS = 50V, ID = 75A Qg Total Gate Charge ––– 85 120 nC ID = 75A Qgs Gate-to-Source Charge ––– 20 ––– Qgd Gate-to-Drain ("Miller") Charge ––– 26 Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 59 ––– td(on) Turn-On Delay Time ––– 15 ––– tr Rise Time ––– 76 ––– td(off) Turn-Off Delay Time ––– 40 ––– RG = 2.7Ω tf Fall Time ––– 77 ––– VGS = 10V Ciss Input Capacitance ––– 4520 ––– Coss Output Capacitance ––– 500 ––– VDS = 50V Crss Reverse Transfer Capacitance ––– 250 ––– ƒ = 1.0MHz, See Fig. 5 Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 720 ––– VGS = 0V, VDS = 0V to 48V 880 ––– VGS = 0V, VDS h VDS =30V VGS = 10V g ID = 75A, VDS =0V, VGS = 10V ns VDD = 30V ID = 75A pF VGS = 0V g i, See Fig. 11 = 0V to 48V h Diode Characteristics Symbol Parameter Min. Typ. Max. Units IS Continuous Source Current ISM (Body Diode) Pulsed Source Current VSD (Body Diode) Diode Forward Voltage ––– ––– trr Reverse Recovery Time ––– 31 ––– 35 ––– 34 ––– 45 ––– 1.9 Qrr ––– ––– d Reverse Recovery Charge IRRM Reverse Recovery Current ton Forward Turn-On Time ––– c 620 1.3 Conditions A MOSFET symbol A showing the integral reverse V p-n junction diode. TJ = 25°C, IS = 75A, VGS = 0V ns TJ = 25°C VR = 51V, TJ = 125°C IF = 75A di/dt = 100A/µs nC TJ = 25°C D G S g g TJ = 125°C ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. ‚ Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by TJmax, starting TJ = 25°C, L = 0.04mH RG = 25Ω, IAS = 96A, VGS =10V. Part not recommended for use above this value. 2 ––– 160 „ ISD ≤ 75A, di/dt ≤ 1400A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. … Pulse width ≤ 400µs; duty cycle ≤ 2%. † Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. ˆ Rθ is measured at TJ approximately 90°C www.irf.com IRFB3306GPbF 1000 1000 BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 4.5V BOTTOM 100 4.5V ≤ 60µs PULSE WIDTH Tj = 175°C ≤ 60µs PULSE WIDTH Tj = 25°C 10 10 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 100 Fig 2. Typical Output Characteristics 1000 2.5 100 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current(Α) 10 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) TJ = 175°C 10 TJ = 25°C 1 VDS = 25V ≤ 60µs PULSE WIDTH 0.1 2.0 3.0 4.0 5.0 6.0 7.0 ID = 75A VGS = 10V 2.0 1.5 1.0 0.5 8.0 -60 -40 -20 VGS, Gate-to-Source Voltage (V) 8000 VGS, Gate-to-Source Voltage (V) Coss = Cds + Cgd Ciss 4000 2000 Coss Crss 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com ID= 75A VDS = 48V VDS= 30V VDS= 12V 16 12 8 4 0 0 1 20 40 60 80 100 120 140 160 180 Fig 4. Normalized On-Resistance vs. Temperature 20 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 6000 0 TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) 1 0 20 40 60 80 100 120 140 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFB3306GPbF 10000 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 TJ = 175°C TJ = 25°C 10 1 OPERATION IN THIS AREA LIMITED BY R DS (on) 1000 1msec 100 10msec 10 1 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.1 2.0 V(BR)DSS , Drain-to-Source Breakdown Voltage 180 Limited By Package 140 120 100 80 60 40 20 0 25 50 75 100 125 150 10 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 160 1 VDS, Drain-toSource Voltage (V) VSD, Source-to-Drain Voltage (V) ID, Drain Current (A) DC 0.1 0.1 80 ID = 5mA 70 60 50 -60 -40 -20 0 175 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (°C) T C , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage EAS, Single Pulse Avalanche Energy (mJ) 1.5 Energy (µJ) 1.0 0.5 0.0 800 I D 13A 18A BOTTOM 96A TOP 600 400 200 0 0 10 20 30 40 50 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 100µsec 60 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig 12. Maximum Avalanche Energy Vs. DrainCurrent www.irf.com IRFB3306GPbF 1 Thermal Response ( ZthJC ) D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 0.01 τJ R1 R1 τJ τ1 τC τ1 τ2 τ2 Ri (°C/W) τι (sec) 0.249761 0.00028 0.400239 0.005548 Ci= τi/Ri C SINGLE PULSE ( THERMAL RESPONSE ) 0.001 R2 R2 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) 0.01 0.05 10 0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 200 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 96A 160 120 80 40 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFB3306GPbF 16 ID = 1.0A ID = 1.0mA ID = 250µA ID = 150µA 4.0 3.5 12 IRRM - (A) VGS(th) Gate threshold Voltage (V) 4.5 3.0 2.5 8 2.0 IF = 30A VR = 51V 4 TJ = 125°C 1.5 TJ = 25°C 0 1.0 -75 -50 -25 0 25 50 75 100 200 300 400 500 600 700 800 900 1000 100 125 150 175 dif / dt - (A / µs) TJ , Temperature ( °C ) Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt 16 350 300 250 QRR - (nC) IRRM - (A) 12 8 4 IF = 45A VR = 51V 200 150 TJ = 125°C 0 IF = 30A VR = 51V 100 50 TJ = 125°C TJ = 25°C TJ = 25°C 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / µs) dif / dt - (A / µs) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 350 300 QRR - (nC) 250 200 150 100 50 0 IF = 45A VR = 51V TJ = 125°C TJ = 25°C 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFB3306GPbF Driver Gate Drive D.U.T ƒ - ‚ „ - - * D.U.T. ISD Waveform Reverse Recovery Current +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG VGS 20V + V - DD IAS A 0.01Ω tp I AS Fig 22a. Unclamped Inductive Test Circuit LD Fig 22b. Unclamped Inductive Waveforms VDS VDS + 90% VDD - 10% D.U.T VGS VGS Pulse Width < 1µs Duty Factor < 0.1% td(on) Fig 23a. Switching Time Test Circuit tr td(off) Fig 23b. Switching Time Waveforms Id Current Regulator Same Type as D.U.T. Vds Vgs 50KΩ 12V tf .2µF .3µF D.U.T. + V - DS Vgs(th) VGS 3mA IG ID Current Sampling Resistors Fig 24a. Gate Charge Test Circuit www.irf.com Qgs1 Qgs2 Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRFB3306GPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5)%*3%) 1RWH*VXIIL[LQSDUWQXPEHU LQGLFDWHV+DORJHQ)UHH 1RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH ,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$57180%(5 '$7(&2'( < /$67',*,72) &$/(1'$5