PD - 97214D
IRFB3307ZPbF
IRFS3307ZPbF
IRFSL3307ZPbF
Applications
l High Efficiency Synchronous Rectification in
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
D
G
Benefits
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
l Enhanced body diode dV/dt and dI/dt
Capability
S
D
75V
4.6mΩ
5.8mΩ
128A
120A
c
D
D
G
D
S
S
G
G
D2Pak
IRFS3307ZPbF
TO-220AB
IRFB3307ZPbF
D
S
TO-262
IRFSL3307ZPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
VGS
d
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
f
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
Units
c
c
128
90
120
512
230
1.5
± 20
6.7
-55 to + 175
A
W
W/°C
V
V/ns
°C
300
x
x
10lbf in (1.1N m)
e
140
See Fig. 14, 15, 22a, 22b
g
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
RθJA
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Parameter
k
Junction-to-Case
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
k
Junction-to-Ambient (PCB Mount) , D2Pak
jk
Typ.
Max.
–––
0.50
–––
–––
0.65
–––
62
40
Units
°C/W
1
08/19/11
IRFB/S/SL3307ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
RG(int)
IDSS
Internal Gate Resistance
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min. Typ. Max. Units
75
–––
–––
2.0
–––
0.094
4.6
–––
–––
–––
5.8
4.0
–––
0.70
–––
–––
–––
–––
–––
20
250
100
-100
–––
–––
–––
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mA
mΩ VGS = 10V, ID = 75A
V VDS = VGS, ID = 150μA
g
d
Ω
μA
nA
VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
h
i
320
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
79
19
24
55
15
64
38
65
4750
420
190
440
410
–––
110
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
VDS = 50V, ID = 75A
ID = 75A
VDS = 38V
VGS = 10V
ID = 75A, VDS =0V, VGS = 10V
VDD = 49V
ID = 75A
RG = 2.6Ω
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
VGS = 0V, VDS = 0V to 60V
g
ns
pF
g
j
h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
di
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 120A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.050mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
2
Min. Typ. Max. Units
–––
––– 128
–––
–––
c
512
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
S
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 75A, VGS = 0V
VR = 64V,
–––
33
50
ns TJ = 25°C
TJ = 125°C
IF = 75A
–––
39
59
di/dt = 100A/μs
–––
42
63
nC TJ = 25°C
TJ = 125°C
–––
56
84
–––
2.2
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
ISD ≤ 75A, di/dt ≤ 1570A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
www.irf.com
IRFB/S/SL3307ZPbF
1000
1000
100
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
4.5V
10
BOTTOM
4.5V
10
≤60μs PULSE WIDTH
≤60μs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
1
0.1
1
10
0.1
100
Fig 1. Typical Output Characteristics
100
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 2. Typical Output Characteristics
1000
100
T J = 175°C
T J = 25°C
10
1
VDS = 25V
≤60μs PULSE WIDTH
0.1
ID = 72A
VGS = 10V
2.0
1.5
1.0
0.5
2
3
4
5
6
7
8
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 72A
C oss = C ds + C gd
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
10000
Ciss
Coss
1000
Crss
10.0
VDS= 60V
VDS= 38V
VDS= 15V
8.0
6.0
4.0
2.0
0.0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
10
20
30
40
50
60
70
80
90
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB/S/SL3307ZPbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
100
T J = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100μsec
100
1msec
10msec
10
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
1
2.0
ID, Drain Current (A)
120
100
80
Limited By Package
40
20
0
50
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
140
25
100
Id = 5mA
95
90
85
80
75
70
65
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1.2
EAS , Single Pulse Avalanche Energy (mJ)
600
1.0
Energy (μJ)
0.8
0.6
0.4
0.2
0.0
ID
15A
26A
BOTTOM 75A
TOP
500
400
300
200
100
0
20
30
40
50
60
70
80
VDS, Drain-to-Source Voltage (V)
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
60
10
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 11. Typical COSS Stored Energy
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB/S/SL3307ZPbF
Thermal Response ( Z thJC )
1
D = 0.50
0.20
0.1
0.10
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
R3
R3
τ3
τC
τ
τ3
0.2313
Ci= τi/Ri
Ci i/Ri
1E-005
0.009191
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
Ri (°C/W) τi (sec)
0.1164 0.000088
0.3009 0.001312
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Δ Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
0.01
Duty Cycle =
Single Pulse
0.05
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
150
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 75A
125
100
75
50
25
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL3307ZPbF
20
IF = 48A
V R = 64V
4.0
3.0
2.5
ID = 150μA
ID = 250μA
ID = 1.0mA
ID = 1.0A
2.0
1.5
1.0
10
5
0
0.5
-75 -50 -25 0
0
25 50 75 100 125 150 175 200
200
400
600
800
1000
T J , Temperature ( °C )
diF /dt (A/μs)
Fig 16. Threshold Voltage vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
20
420
IF = 72A
V R = 64V
IF = 48A
V R = 64V
340
TJ = 25°C
TJ = 125°C
QRR (A)
15
IRR (A)
TJ = 25°C
TJ = 125°C
15
3.5
IRR (A)
VGS(th), Gate threshold Voltage (V)
4.5
10
5
TJ = 25°C
TJ = 125°C
260
180
100
0
20
0
200
400
600
800
1000
0
200
diF /dt (A/μs)
400
600
800
1000
diF /dt (A/μs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
420
IF = 72A
V R = 64V
QRR (A)
340
TJ = 25°C
TJ = 125°C
260
180
100
20
0
200
400
600
800
1000
diF /dt (A/μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB/S/SL3307ZPbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
tp
A
0.01Ω
I AS
Fig 21a. Unclamped Inductive Test Circuit
LD
Fig 21b. Unclamped Inductive Waveforms
VDS
VDS
90%
+
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 22a. Switching Time Test Circuit
tr
td(off)
tf
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
VCC
Vgs(th)
1K
Qgs1 Qgs2
Fig 23a. Gate Charge Test Circuit
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Qgd
Qgodr
Fig 23b. Gate Charge Waveform
7
IRFB/S/SL3307ZPbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
(;$03/( 7+,6,6$1,5)
/27&2'(
$66(0%/('21::
,17+($66(0%/