PD - 96216
IRFB4115GPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
l Halogen-Free
150V
9.3mΩ
11mΩ
104A
D
G
D
S
TO-220AB
IRFB4115GPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
104
74
420
380
2.5
± 20
18
-55 to + 175
c
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
e
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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d
c
Parameter
i
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
Units
A
W
W/°C
V
V/ns
°C
300
x
x
10lbf in (1.1N m)
220
See Fig. 14, 15, 22a, 22b
mJ
A
mJ
Typ.
Max.
Units
–––
0.50
–––
0.40
–––
62
°C/W
1
01/06/09
IRFB4115GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
IGSS
RG
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
150
–––
–––
3.0
–––
–––
–––
–––
–––
–––
0.18
9.3
–––
–––
–––
–––
–––
2.3
–––
–––
11
5.0
20
250
100
-100
–––
V
V/°C
mΩ
V
µA
nA
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 3.5mA
VGS = 10V, ID = 62A
VDS = VGS, ID = 250µA
VDS = 150V, VGS = 0V
VDS = 150V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
c
f
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Conditions
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
97
–––
–––
–––
–––
Turn-On Delay Time
–––
Rise Time
–––
Turn-Off Delay Time
–––
Fall Time
–––
Input Capacitance
–––
Output Capacitance
–––
Reverse Transfer Capacitance
–––
Effective Output Capacitance (Energy Related) –––
Effective Output Capacitance (Time Related)
–––
–––
77
28
26
51
18
73
41
39
5270
490
105
460
530
–––
120
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
VDS = 50V, ID = 62A
ID = 62A
VDS = 75V
VGS = 10V
ID = 62A, VDS =0V, VGS = 10V
VDD = 98V
ID = 62A
RG = 2.2Ω
VGS = 10V
VGS = 0V
VDS = 50V
f
ns
pF
f
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 120V
VGS = 0V, VDS = 0V to 120V
Diode Characteristics
Symbol
IS
Parameter
VSD
trr
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
d
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.11mH
RG = 25Ω, IAS = 62A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 62A, di/dt ≤ 1040A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Conditions
Min. Typ. Max. Units
–––
–––
104
A
–––
–––
420
A
h, See Fig. 11
g
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 62A, VGS = 0V
TJ = 25°C
VR = 130V,
IF = 62A
TJ = 125°C
TJ = 25°C
di/dt = 100A/µs
TJ = 125°C
TJ = 25°C
D
f
S
––– –––
1.3
V
–––
86
–––
ns
––– 110 –––
––– 300 –––
nC
––– 450 –––
–––
6.5
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
f
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C.
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IRFB4115GPbF
1000
1000
100
BOTTOM
100
10
1
5.0V
BOTTOM
5.0V
10
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1
0.1
1
1
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
100
T J = 25°C
10
1
VDS = 50V
≤60µs PULSE WIDTH
0.1
ID = 62A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
2
4
6
8
10
12
14
16
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
14.0
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
10000
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
Ciss
Coss
1000
Crss
100
10
ID= 62A
12.0
VDS= 120V
VDS= 75V
VDS= 30V
10.0
8.0
6.0
4.0
2.0
0.0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
20
40
60
80
100
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB4115GPbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
100
10
T J = 25°C
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
10msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1
VSD, Source-to-Drain Voltage (V)
80
60
40
20
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID, Drain Current (A)
100
50
1000
200
Id = 3.5mA
190
180
170
160
150
140
-60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C)
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
900
EAS , Single Pulse Avalanche Energy (mJ)
6.0
5.0
4.0
Energy (µJ)
100
Fig 8. Maximum Safe Operating Area
120
25
10
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
3.0
2.0
1.0
ID
TOP
10A
22A
BOTTOM 62A
800
700
600
500
400
300
200
100
0
0.0
-20
0
20
40
60
80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
1msec
DC
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB4115GPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
0.001
τJ
τJ
τ1
R2
R2
τ2
τ1
τ2
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
0.0500 0.000052
0.1461 0.000468
0.2041
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
R1
R1
0.004702
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
0.05
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
250
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 62A
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4115GPbF
50
5.0
40
4.0
30
IRR (A)
VGS(th) , Gate threshold Voltage (V)
6.0
ID = 250µA
ID = 1.0mA
3.0
IF = 42A
V R = 130V
TJ = 25°C
TJ = 125°C
20
ID = 1.0A
10
2.0
0
1.0
-75 -50 -25
0
0
25 50 75 100 125 150 175
200
TJ , Temperature ( °C )
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
50
2500
IF = 62A
V R = 130V
40
IF = 42A
V R = 130V
2000
TJ = 25°C
TJ = 125°C
30
QRR (A)
IRR (A)
400
diF /dt (A/µs)
20
10
TJ = 25°C
TJ = 125°C
1500
1000
500
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
3000
IF = 62A
V R = 130V
QRR (A)
2400
TJ = 25°C
TJ = 125°C
1800
1200
600
0
0
200
400
600
800
1000
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4115GPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFB4115GPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
(;$03/( 7+,6,6$1,5)%*3%)
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