IRFI4410ZPBF

IRFI4410ZPbF   HEXFET® Power MOSFET Applications  High Efficiency Synchronous Rectification in SMPS  Uninterruptible Power Supply  High Speed Power Switching  Hard Switched and High Frequency Circuits   Benefits  Improved Gate, Avalanche and Dynamic dV/dt Ruggedness  Fully Characterized Capacitance and Avalanche SOA  Enhanced body diode dV/dt and dI/dt Capability  Lead-Free VDSS 100V RDS(on) typ. 7.9m RDS(on) max. 9.3m ID 43A G Package Type IRFI4410ZPbF TO-220 Full-Pak Absolute Maximum Ratings Symbol D Drain Standard Pack Form Quantity Tube 50 IRFI4410ZPbF Parameter Max. ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 43 Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Maximum Power Dissipation 30 170 47 Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy (Thermally Limited)  Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw 0.3 ± 30 Thermal Resistance   Symbol Parameter Junction-to-Case  RJC Junction-to-Ambient (PCB Mount) RJA 1 S Source Orderable Part Number ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS TJ TSTG S TO-220 Full-Pak G Gate Base Part Number D Units A W 310 -55 to + 175 W/°C V mJ   °C  300 10 lbf•in (1.1N•m) Typ. ––– ––– Max. 3.2 65     Units °C/W 2017-04-27 IRFI4410ZPbF   Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Min. 100 ––– ––– 2.0 ––– ––– ––– ––– ––– Typ. ––– 95 7.9 ––– ––– ––– ––– ––– 0.9 Max. ––– ––– 9.3 4.0 20 250 100 -100 ––– IDSS Drain-to-Source Leakage Current Dynamic @ TJ = 25°C (unless otherwise specified) gfs Forward Trans conductance Qg Total Gate Charge Qgs Gate-to-Source Charge Qgd Gate-to-Drain Charge td(on) Turn-On Delay Time Rise Time tr td(off) Turn-Off Delay Time Fall Time tf Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance 80 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 81 18 23 15 27 43 30 4910 330 150 Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 420 ––– S VDS = 50V, ID = 26A 110   ID = 26A ––– nC   VDS = 50V VGS = 10V  –––   ––– VDD = 65V ––– ID = 26A ns ––– RG= 2.7 VGS = 10V  ––– ––– VGS = 0V ––– VDS = 50V ––– pF   ƒ = 1.0MHz ––– VGS=0V,VDS= 0V to 80V See Fig. 11 Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 680 ––– IGSS   RG Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance Source-Drain Ratings and Characteristics Parameter Continuous Source Current IS (Body Diode) Pulsed Source Current ISM (Body Diode) VSD Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current ton Forward Turn-On Time Min. Typ. ––– ––– 43 ––– ––– 170 ––– ––– 1.3 ––– 47 71 ––– ––– ––– 54 110 140 81 160 210 ––– 2.5 ––– Units V mV/°C m V Conditions VGS = 0V, ID = 250µA Reference to 25°C, ID = 5mA  VGS = 10V, ID = 26A VDS = VGS, ID = 150µA VDS = 100 V, VGS = 0V µA VDS = 100V,VGS = 0V,TJ =125°C VGS = 20V nA   VGS = -20V  VGS = 0V, VDS = 0V to 80V  Max. Units A V ns Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C,IS = 26A,VGS = 0V  TJ = 25°C TJ = 125°C VR = 85V TJ = 25°C  I nC F = 26A TJ = 125°C  di/dt= 100A/µs A  TJ = 25°C   Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)  Limited by TJmax, starting TJ = 25°C, L = 0.91mH, RG = 25, IAS = 26A, VGS =10V. Part not recommended for use above this value.  Pulse width 400µs; duty cycle  2%. R is measured at TJ approximately 90°C.  Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.  Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 2 2017-04-27 IRFI4410ZPbF   1000 ID, Drain-to-Source Current (A) TOP BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 60µs PULSE WIDTH VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP Tj = 25°C ID, Drain-to-Source Current (A) 1000 100 BOTTOM 100 4.5V 60µs PULSE WIDTH 4.5V Tj = 175°C 10 10 0.1 1 10 0.1 100 VDS, Drain-to-Source Voltage (V) 100 3.0 R DS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current(A) 1000 100 TJ = 175°C 10 TJ = 25°C 1 VDS = 50V 60µs PULSE WIDTH 0.1 2 3 4 5 ID = 26A VGS = 10V 2.5 2.0 1.5 1.0 0.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig. 3 Typical Transfer Characteristics 8000 VGS, Gate-to-Source Voltage (V) Coss = Cds + Cgd C iss 4000 2000 C oss C rss 0 1 Fig. 4 Normalized On-Resistance vs. Temperature 16 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 6000 C, Capacitance (pF) 10 Fig. 2 Typical Output Characteristics Fig. 1 Typical Output Characteristics ID= 26A VDS = 80V VDS = 50V 12 VDS = 20V 8 4 0 10 100 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 3 1 VDS, Drain-to-Source Voltage (V) 0 20 40 60 80 100 120 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 2017-04-27 IRFI4410ZPbF   1000 100 ID, Drain-to-Source Current (A) ISD , Reverse Drain Current (A) 1000 TJ = 175°C 10 TJ = 25°C 1 OPERATION IN THIS AREA LIMITED BY R DS (on) 100 100µsec 1msec 10 DC 10msec 1 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.1 0.1 0.0 0.5 1.0 0.1 1.5 Fig. 7. Typical Source-to-Drain Diode Forward Voltage 50 ID , Drain Current (A) 40 30 20 10 0 50 75 100 125 150 175 V(BR)DSS, Drain-to-Source Breakdown Voltage (V) VSD , Source-to-Drain Voltage (V) 25 1 1000 Fig 8. Maximum Safe Operating Area Id = 5mA 125 120 115 110 105 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , Temperature ( °C ) Fig. 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage 1400 EAS, Single Pulse Avalanche Energy (mJ) 2.0 1.5 Energy (µJ) 100 130 TC , CaseTemperature (°C) 1.0 0.5 ID 8.6A 14A BOTTOM 26A 1200 TOP 1000 800 600 400 200 0 0.0 0 20 40 60 80 VDS, Drain-to-Source Voltage (V) Fig. 11. Typical COSS Stored Energy   4 10 VDS , Drain-toSource Voltage (V) 100 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. Drain Current 2017-04-27 IRFI4410ZPbF   Thermal Response ( Z thJC ) 10 D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 J R1 R1 J 1 R2 R2 R3 R3 R4 R4 C 2 1 2 3 3 4 4 Ci= iRi Ci iRi 0.01  Ri (°C/W) (sec) 0.117574 0.000176 1.337531 0.7389 1.260992 0.103059 0.508931 0.008379 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case Avalanche Current (A) 100 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150°C and Tstart =25°C (Single Pulse) 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming  j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 tav (sec) Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width EAR , Avalanche Energy (mJ) 320 TOP Single Pulse BOTTOM 10% Duty Cycle ID = 26A 240 160 80 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (°C) Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.infineon.com) 1.Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC Iav = 2T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav   Fig 15. Maximum Avalanche Energy vs. Temperature 5 2017-04-27 IRFI4410ZPbF   16 4.0 ID = 1.0A ID = 1.0mA 3.5 ID = 150µA 12 14 ID = 250µA 10 3.0 IRR (A) VGS(th) Gate threshold Voltage (V) 4.5 2.5 8 6 IF = 17A VR = 85V 2.0 4 1.5 TJ = 25°C TJ = 125°C 2 1.0 -75 -50 -25 0 25 50 75 0 100 125 150 175 100 200 TJ , Temperature ( °C ) 400 500 600 700 diF /dt (A/µs) Fig 16. Threshold Voltage vs. Temperature Fig 17. Typical Recovery Current vs. dif/dt 16 350 14 300 12 250 QRR (nC) 10 IRR (A) 300 8 6 4 IF = 26A VR = 85V 2 TJ = 25°C TJ = 125°C 200 150 IF = 17A VR = 85V 100 TJ = 25°C TJ = 125°C 50 0 0 100 200 300 400 500 600 700 100 200 diF /dt (A/µs) 300 400 500 600 700 diF /dt (A/µs) Fig 18. Typical Recovery Current vs. dif/dt Fig 19. Typical Stored Charge vs. dif/dt 350 300 QRR (nC) 250 200 150 IF = 26A VR = 85V 100 TJ = 25°C TJ = 125°C 50 0 100 200 300 400 500 600 700 diF /dt (A/µs) Fig 20. Typical Stored Charge vs. dif/dt 6 2017-04-27 IRFI4410ZPbF   Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS tp 15V L VDS D.U.T RG IAS 20V tp DRIVER + V - DD A 0.01 Fig 22a. Unclamped Inductive Test Circuit Fig 23a. Switching Time Test Circuit I AS Fig 22b. Unclamped Inductive Waveforms Fig 23b. Switching Time Waveforms Id Vds Vgs Vgs(th) Qgs1 Qgs2 Fig 24a. Gate Charge Test Circuit 7 Qgd Qgodr Fig 24b. Gate Charge Waveform 2017-04-27 IRFI4410ZPbF   TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches)) TO-220 Full-Pak Part Marking Information TO-220AB Full-Pak packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to website at http://www.irf.com/package/   8 2017-04-27 IRFI4410ZPbF   Qualification Information  Industrial (per JEDEC JESD47F) † Qualification Level   TO-220 Full-Pak Moisture Sensitivity Level   N/A Yes RoHS Compliant † Applicable version of JEDEC standard at the time of product release. Revision History Date 04/27/2017 Comments     Changed datasheet with Infineon logo - all pages. Corrected Package Outline on page 8. Corrected fig 19 & 20 –Y axis title from “A” to “nC” on page 6. Added disclaimer on last page. Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2016-04-19 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Email: erratum@infineon.com Document reference ifx1 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.   9 For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). Please note that this product is not qualified according to the AEC Q100 or AEC Q101 documents of the Automotive Electronics Council. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 2017-04-27