IRFR3607TRPBF

PD - 97312B IRFR3607PbF IRFU3607PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET® Power MOSFET D G Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability S VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited) 75V 7.34mΩ 9.0mΩ 80A 56A c D S S D G G D-Pak I-Pak IRFR3607PbF IRFU3607PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Max. Units c c 80 56 56 310 140 Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Wire Bond Limited) d Pulsed Drain Current Maximum Power Dissipation A W 0.96 ± 20 27 -55 to + 175 Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds f W/°C V V/ns °C 300 (1.6mm from case) Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy d e mJ A mJ 120 46 g 14 Thermal Resistance Symbol RθJC RθJA RθJA www.irf.com Parameter k Junction-to-Case Junction-to-Ambient (PCB Mount) Junction-to-Ambient j Typ. Max. Units ––– ––– ––– 1.045 50 110 °C/W 1 04/30/2010 IRFR/U3607PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units 75 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– 0.096 ––– 7.34 9.0 ––– 4.0 ––– 20 ––– 250 ––– 100 ––– -100 Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mA mΩ VGS = 10V, ID = 46A V VDS = VGS, ID = 100µA µA VDS = 75V, VGS = 0V VDS = 60V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V d g Dynamic @ TJ = 25°C (unless otherwise specified) Symbol Parameter gfs Qg Qgs Qgd Qsync Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) h j 115 ––– ––– ––– ––– ––– 56 13 16 40 ––– 84 ––– ––– ––– ––– 0.55 16 110 43 96 3070 280 130 380 610 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC Conditions VDS = 50V, ID = 46A ID = 46A VDS = 38V VGS = 10V ID = 46A, VDS =0V, VGS = 10V g Ω ns pF VDD = 49V ID = 46A RG = 6.8Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V VGS = 0V, VDS = 0V to 60V g j h Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM d Notes:  Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 56A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. ‚ Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by TJmax, starting TJ = 25°C, L = 0.12mH RG = 25Ω, IAS = 46A, VGS =10V. Part not recommended for use above this value. 2 Min. Typ. Max. Units c ––– ––– 80 ––– ––– 310 A Conditions MOSFET symbol showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 46A, VGS = 0V TJ = 25°C VR = 64V, IF = 46A TJ = 125°C di/dt = 100A/µs TJ = 25°C S g ––– ––– 1.3 V ––– 33 50 ns ––– 39 59 ––– 32 48 nC TJ = 125°C ––– 47 71 ––– 1.9 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) g „ ISD ≤ 46A, di/dt ≤ 1920A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. … Pulse width ≤ 400µs; duty cycle ≤ 2%. † Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom- mended footprint and soldering techniques refer to application note #AN-994. ‰ Rθ is measured at TJ approximately 90°C. www.irf.com IRFR/U3607PbF 1000 1000 100 BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V BOTTOM 100 4.5V 10 4.5V ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 175°C Tj = 25°C 10 1 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 100 Fig 2. Typical Output Characteristics 1000 3.0 100 T J = 175°C 10 T J = 25°C 1 VDS = 25V ≤60µs PULSE WIDTH 0.1 2 3 4 5 6 7 ID = 80A 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature Fig 3. Typical Transfer Characteristics 12.0 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd VGS , Gate-to-Source Voltage (V) ID= 46A Coss = Cds + Cgd 10000 Ciss Coss 1000 2.0 8 VGS , Gate-to-Source Voltage (V) 100000 VGS = 10V 2.5 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (A) 10 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) C, Capacitance (pF) 1 Crss 10.0 VDS= 24V VDS= 15V 8.0 6.0 4.0 2.0 0.0 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 10 20 30 40 50 60 Q G , Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFR/U3607PbF 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 100 T J = 175°C 10 T J = 25°C 1 100µsec 100 1msec 10msec 10 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.0 0.5 1.0 1.5 1 2.0 Limited By Package ID, Drain Current (A) 60 50 40 30 20 10 0 50 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 80 25 100 Id = 5mA 95 90 85 80 75 70 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 1.20 EAS , Single Pulse Avalanche Energy (mJ) 500 1.00 0.80 Energy (µJ) 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 70 10 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 0.60 0.40 0.20 0.00 ID 5.6A 11A BOTTOM 46A 450 TOP 400 350 300 250 200 150 100 50 0 -10 0 10 20 30 40 50 60 70 80 VDS, Drain-to-Source Voltage (V) 4 DC 1 0.1 Fig 11. Typical COSS Stored Energy 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRFR/U3607PbF Thermal Response ( Z thJC ) °C/W 10.00 1.00 D = 0.50 0.20 0.10 0.05 0.10 τJ 0.02 0.01 0.01 R1 R1 τJ τ1 R2 R2 R3 R3 τC τ τ2 τ1 τ2 τ3 τ3 Ci= τi/Ri Ci i/Ri 1E-005 τ4 0.01109 0.000003 0.26925 0.000130 0.49731 0.001301 0.26766 0.008693 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.00 1E-006 τ4 τi (sec) Ri (°C/W) R4 R4 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) 100 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 150 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 46A 125 100 75 50 25 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFR/U3607PbF 20 IF = 31A V R = 64V 4.0 TJ = 25°C TJ = 125°C 15 3.5 3.0 IRR (A) VGS(th) , Gate Threshold Voltage (V) 4.5 ID = 100µA 2.5 10 ID = 250µA 2.0 ID = 1.0mA 5 ID = 1.0A 1.5 1.0 0 -75 -50 -25 0 25 50 75 100 125 150 175 200 0 200 T J , Temperature ( °C ) 600 800 1000 Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 560 20 IF = 46A V R = 64V IF = 31A V R = 64V 480 TJ = 25°C TJ = 125°C TJ = 25°C TJ = 125°C 400 Q RR (A) 15 IRR (A) 400 diF /dt (A/µs) 10 320 240 160 5 80 0 0 0 200 400 600 800 0 1000 200 400 600 800 1000 diF /dt (A/µs) diF /dt (A/µs) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 560 IF = 46A V R = 64V 480 TJ = 25°C TJ = 125°C Q RR (A) 400 320 240 160 80 0 0 200 400 600 800 1000 diF /dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFR/U3607PbF D.U.T Driver Gate Drive ƒ - ‚ „ - - * D.U.T. ISD Waveform Reverse Recovery Current +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V D.U.T RG VGS 20V DRIVER L VDS tp + V - DD IAS tp A 0.01Ω I AS Fig 21a. Unclamped Inductive Test Circuit LD Fig 21b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1µs Duty Factor < 0.1% td(on) Fig 22a. Switching Time Test Circuit tr td(off) tf Fig 22b. Switching Time Waveforms Id Vds Vgs L DUT 0 VCC Vgs(th) 1K Qgs1 Qgs2 Fig 23a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 23b. Gate Charge Waveform 7 IRFR/U3607PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information (;$03/( 7+,6,6$1,5)5 3$57180%(5 :,7+$66(0%/< ,17(51$7,21$/ /27&2'( ,5)5 5(&7,),(5 $66(0%/('21::  ,17+($66(0%/