PD -97147
IRFS4115-7PPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
D
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
VDSS
150V
RDS(on) typ.
10.0m:
max. 11.8m:
ID
105A
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Units
105
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
74
IDM
Pulsed Drain Current c
420
PD @TC = 25°C
Maximum Power Dissipation
380
W
Linear Derating Factor
2.5
VGS
Gate-to-Source Voltage
± 20
W/°C
V
dv/dt
TJ
Peak Diode Recovery e
32
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
A
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy d
IAR
Avalanche Current c
EAR
Repetitive Avalanche Energy f
mJ
230
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Symbol
RθJC
RθJA
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Parameter
Typ.
Max.
Units
Junction-to-Case jk
–––
0.40
°C/W
Junction-to-Ambient (PCB Mount) ij
–––
40
1
11/7/08
IRFS4115-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
RG(int)
Min. Typ. Max. Units
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
150
–––
–––
3.0
–––
–––
–––
–––
–––
0.18
10.
–––
–––
–––
–––
–––
–––
–––
11.8
5.0
20
250
100
-100
Internal Gate Resistance
–––
2.1
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 3.5mAc
mΩ VGS = 10V, ID = 63A f
V VDS = VGS, ID = 250μA
μA VDS = 150V, VGS = 0V
VDS = 150V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
93
–––
–––
–––
–––
Turn-On Delay Time
–––
Rise Time
–––
Turn-Off Delay Time
–––
Fall Time
–––
Input Capacitance
–––
Output Capacitance
–––
Reverse Transfer Capacitance
–––
Effective Output Capacitance (Energy Related)h –––
–––
Effective Output Capacitance (Time Related)g
–––
73
28
28
45
18
50
37
23
5320
490
110
450
520
–––
110
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Conditions
VDS = 50V, ID = 62A
ID = 63A
VDS = 75V
VGS = 10V f
ID = 63A, VDS =0V, VGS = 10V
VDD = 98V
ID = 63A
RG = 2.1Ω
VGS = 10V f
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 120V h
VGS = 0V, VDS = 0V to 120V g
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
(Body Diode)c
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.115mH
RG = 25Ω, IAS = 63A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 63A, di/dt ≤ 2510A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
–––
–––
–––
–––
104
420
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 63A, VGS = 0V f
TJ = 25°C
VR = 130V,
IF = 63A
TJ = 125°C
di/dt = 100A/μs f
TJ = 25°C
––– –––
1.3
V
–––
82
–––
ns
–––
99
–––
––– 271 –––
nC
TJ = 125°C
––– 385 –––
–––
6.0
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
S
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
www.irf.com
IRFS4115-7PPbF
1000
1000
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
1
0.1
5.0V
100
BOTTOM
10
5.0V
≤60μs PULSE WIDTH
≤60μs PULSE WIDTH
Tj = 25°C
Tj = 175°C
0.01
1
0.1
1
10
100
1000
0.1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS, Drain-to-Source Voltage (V)
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
≤ 60μs PULSE WIDTH
0.1
3.0
4.0
5.0
6.0
7.0
8.0
ID = 63A
2.0
1.5
1.0
0.5
0.0
9.0
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
8000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
Ciss
4000
2000
Coss
Crss
0
1
ID= 63A
VDS = 120V
VDS = 75V
12
VDS = 30V
8
4
0
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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Fig 4. Normalized On-Resistance vs. Temperature
16
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
6000
VGS = 10V
2.5
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
0
20
40
60
80
100
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS4115-7PPbF
10000
100
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000
TJ = 175°C
10
TJ = 25°C
1
1000
VGS = 0V
0.5
1.0
1.5
1msec
10
10msec
1
80
60
40
20
0
125
150
175
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
ID , Drain Current (A)
100
100
100
1000
Id = 3.5mA
180
170
160
150
140
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1000
EAS, Single Pulse Avalanche Energy (mJ)
4
3
Energy (μJ)
10
190
TC , CaseTemperature (°C)
2
1
ID
14A
24A
BOTTOM 63A
TOP
800
600
400
200
0
0
0
20
40
60
80
100
120
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
1
Fig 8. Maximum Safe Operating Area
120
75
DC
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
50
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
2.0
VSD , Source-to-Drain Voltage (V)
25
100μsec
100
0.1
0.1
0.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
140
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFS4115-7PPbF
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20
R1
R1
0.10
τJ
0.05
0.02
0.01
0.01
τJ
τ1
R2
R2
τ2
τ1
τ2
R3
R3
τ3
R4
R4
τC
τ
τ4
τ3
Ci= τi/Ri
Ci i/Ri
τ4
Ri (°C/W) τι (sec)
0.015402 0.00001
0.056989 0.000065
0.180208 0.001377
0.146323 0.010705
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
100
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
240
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 63A
200
160
120
80
40
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS4115-7PPbF
50
ID = 1.0A
ID = 1.0mA
5.0
40
ID = 250μA
4.0
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
6.0
3.0
2.0
30
20
IF = 42A
VR = 127V
10
1.0
TJ = 125°C
TJ = 25°C
0
-75
-50
-25
0
25
50
75
100 125 150 175
100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C )
dif / dt - (A / μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
2400
50
2000
40
QRR - (nC)
IRRM - (A)
1600
30
20
10
0
1200
800
IF = 63A
VR = 127V
IF = 42A
VR = 127V
400
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
2400
2000
QRR - (nC)
1600
1200
800
400
IF = 63A
VR = 127V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS4115-7PPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFS4115-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS4115-7PPbF
D2Pak - 7 Pin Part Marking Information
25
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/08
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9
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
