IRFU3711ZPBF

PD - 95074A IRFR3711ZPbF IRFU3711ZPbF Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use l Lead-Free HEXFET® Power MOSFET VDSS 20V RDS(on) max 5.7m: Qg 18nC Benefits l l l Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current D-Pak IRFR3711Z I-Pak IRFU3711Z Absolute Maximum Ratings Parameter Max. Units 20 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 93 66 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TC = 25°C Maximum Power Dissipation PD @TC = 100°C Maximum Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range ID @ TC = 25°C ID @ TC = 100°C c f f A 370 g g 79 W 39 0.53 -55 to + 175 Soldering Temperature, for 10 seconds W/°C °C 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount) RθJA Junction-to-Ambient g Typ. Max. ––– 1.9 ––– 50 ––– 110 Units °C/W Notes  through … are on page 11 www.irf.com 1 12/13/04 IRFR/U3711ZPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance ––– 20 V Conditions ––– ––– VGS = 0V, ID = 250µA ––– 13 ––– ––– 4.5 5.7 mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 15A 6.2 7.8 VGS = 4.5V, ID = 12A VGS(th) Gate Threshold Voltage 1.55 2.0 2.45 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.4 ––– mV/°C IDSS Drain-to-Source Leakage Current µA VDS = 16V, VGS = 0V nA VGS = 20V ––– ––– 1.0 ––– ––– 150 IGSS Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 gfs Qg Forward Transconductance 48 ––– ––– e e VDS = VGS, ID = 250µA VDS = 16V, VGS = 0V, TJ = 125°C VGS = -20V S VDS = 10V, ID = 12A Total Gate Charge ––– 18 27 Qgs1 Pre-Vth Gate-to-Source Charge ––– 5.1 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 1.8 ––– Qgd Gate-to-Drain Charge ––– 6.5 ––– ID = 12A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 4.6 ––– See Fig. 16 Qsw ––– 8.3 ––– Qoss Output Charge ––– 9.8 ––– td(on) Turn-On Delay Time ––– 12 ––– VDD = 15V, VGS = 4.5V tr Rise Time ––– 13 ––– ID = 12A td(off) Turn-Off Delay Time ––– 15 ––– tf Fall Time ––– 5.2 ––– Ciss Input Capacitance ––– 2160 ––– Coss Output Capacitance ––– 700 ––– Crss Reverse Transfer Capacitance ––– 360 ––– VDS = 10V nC nC ns VGS = 4.5V VDS = 10V, VGS = 0V e Clamped Inductive Load VGS = 0V pF VDS = 10V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c d c Typ. Max. Units ––– 140 mJ ––– 12 A ––– 7.9 mJ Diode Characteristics Parameter Min. Typ. Max. Units f IS Continuous Source Current ––– ––– 93 ISM (Body Diode) Pulsed Source Current ––– ––– 370 VSD (Body Diode) Diode Forward Voltage ––– ––– 1.0 V trr Reverse Recovery Time ––– 19 28 ns Qrr Reverse Recovery Charge ––– 9.4 14 nC ton Forward Turn-On Time 2 c Conditions MOSFET symbol A showing the integral reverse p-n junction diode. TJ = 25°C, IS = 12A, VGS = 0V e TJ = 25°C, IF = 12A, VDD = 10V di/dt = 100A/µs e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRFR/U3711ZPbF 1000 1000 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V BOTTOM 2.5V 100 TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 10 1 2.5V 100 10 2.5V 20µs PULSE WIDTH Tj = 175°C 20µs PULSE WIDTH Tj = 25°C 1 0.1 0.1 1 0.1 10 Fig 1. Typical Output Characteristics 10 Fig 2. Typical Output Characteristics 2.0 T J = 25°C T J = 175°C 100 10 VDS = 10V 20µs PULSE WIDTH 1 ID = 30A VGS = 10V 1.5 (Normalized) RDS(on) , Drain-to-Source On Resistance 1000 ID, Drain-to-Source Current (Α) 1 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) 1.0 0.5 2.0 3.0 4.0 5.0 6.0 7.0 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 8.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRFR/U3711ZPbF VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds Crss = C gd 12 ID= 12A SHORTED VGS , Gate-to-Source Voltage (V) 10000 C, Capacitance (pF) Coss = Cds + Cgd Ciss 1000 Coss Crss 100 10 8 6 4 2 0 1 10 100 0 10 VDS, Drain-to-Source Voltage (V) 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 30 40 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.0 100.0 T J = 175°C 10.0 T J = 25°C 1.0 20 Q G Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100µsec 10 1msec Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 10msec 1 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 VDS= 18V VDS= 10V 2.5 0.1 1.0 10.0 100.0 1000.0 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRFR/U3711ZPbF 100 2.5 VGS(th) Gate threshold Voltage (V) LIMITED BY PACKAGE ID , Drain Current (A) 80 60 40 20 0 2.0 1.5 ID = 250µA 1.0 0.5 0.0 25 50 75 100 125 150 175 -75 -50 -25 T C , Case Temperature (°C) 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 R1 R1 τJ τ1 R2 R2 τ2 τ1 τ2 Ci= τi/Ri Ci= i/Ri 0.01 SINGLE PULSE ( THERMAL RESPONSE ) R3 R3 τ3 τC τ τ3 Ri (°C/W) τi (sec) 0.805 0.000237 0.606 0.001005 0.492 0.101628 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFR/U3711ZPbF 15V D.U.T RG + V - DD IAS 20V VGS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS, Single Pulse Avalanche Energy (mJ) DRIVER L VDS 600 ID 7.7A 8.9A BOTTOM 12A TOP 500 400 300 200 100 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current LD I AS VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID VGS Current Sampling Resistors td(on) Fig 13. Gate Charge Test Circuit 6 tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRFR/U3711ZPbF D.U.T Driver Gate Drive P.W. + ƒ + - - „ * D.U.T. ISD Waveform Reverse Recovery Current +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ‚ D= Period V DD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRFR/U3711ZPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ ⎞ ⎞ ⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRFR/U3711ZPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRF R120 WITH AS SEMB LY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASS EMBLY LINE "A" PART NUMBER INTE RNATIONAL RECTIFIER LOGO Note: "P" in ass embly line position indicates "Lead-Free" IRFU120 12 916A 34 ASS EMBLY LOT CODE DATE CODE YEAR 9 = 1999 WE EK 16 LINE A OR PART NUMBER INTE RNATIONAL RECTIFIER LOGO IRFU120 12 ASS EMBLY LOT CODE www.irf.com 34 DATE CODE P = DESIGNAT ES LEAD-F REE PRODUCT (OPTIONAL) YEAR 9 = 1999 WE EK 16 A = ASS EMBLY SIT E CODE 9 IRFR/U3711ZPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H ASSEMBLY LOT CODE 5678 ASSE MBLE D ON WW 19, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INTE RNAT IONAL RECT IF IER LOGO IRFU120 919A 56 78 ASSEMBLY LOT CODE Note: "P" in ass embly line pos ition indicates "Lead-Free" DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR PART NUMBE R INT ERNAT IONAL RECTIF IER LOGO IRFU120 56 AS SEMBLY LOT CODE 10 78 DATE CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPTIONAL) YEAR 9 = 1999 WE EK 19 A = ASS EMBLY SIT E CODE www.irf.com IRFR/U3711ZPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes:  Repetitive rating; pulse width limited by „ Calculated continuous current based on maximum allowable max. junction temperature. ‚ Starting TJ = 25°C, L = 1.9mH, RG = 25Ω, IAS = 12A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. … When mounted on 1" square PCB (FR-4 or G-10 Material). junction temperature. Package limitation current is 30A. For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 www.irf.com 11 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/ IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.