PD - 95446B
IRL1404ZPbF
IRL1404ZSPbF
IRL1404ZLPbF
Features
l
l
l
l
l
l
l
Logic Level
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
HEXFET® Power MOSFET
D
VDSS = 40V
RDS(on) = 3.1mΩ
G
ID = 120A
Description
S
This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features combine
to make this design an extremely efficient and
reliable device for use in a wide variety of
applications.
TO-220AB
IRL1404ZPbF
D2Pak
TO-262
IRL1404ZSPbF IRL1404ZLPbF
Absolute Maximum Ratings
ID @ TC = 25°C
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Max.
200
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
k
140k
120k
IDM
Pulsed Drain Current
790
PD @TC = 25°C
Power Dissipation
c
Linear Derating Factor
VGS
Gate-to-Source Voltage
d
EAS (Thermally limited)
Single Pulse Avalanche Energy
EAS (Tested )
Single Pulse Avalanche Energy Tested Value
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
c
g
h
Units
A
230
W
1.5
± 16
W/°C
V
220
mJ
490
See Fig.12a, 12b, 15, 16
A
mJ
-55 to + 175
°C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
y
y
10 lbf in (1.1N m)
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat, Greased Surface
RθJA
Junction-to-Ambient
RθJA
Junction-to-Ambient (PCB Mount)
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i
i
j
Typ.
–––
Max.
0.65
0.50
–––
–––
62
–––
40
Units
°C/W
1
06/25/12
IRL1404Z/S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min.
40
Typ.
–––
Max.
–––
Units
Conditions
V
VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ
Breakdown Voltage Temp. Coefficient
–––
0.034
–––
V/°C
–––
2.5
3.1
–––
–––
4.7
–––
–––
5.9
1.4
–––
2.7
Reference to 25°C, ID = 1mA
el
e
= 40A e
VGS = 10V, ID = 75A
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
VGS = 5.0V, ID = 40A
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
120
–––
–––
S
VDS = 10V, ID = 75A
IDSS
Drain-to-Source Leakage Current
–––
–––
20
μA
VDS = 40V, VGS = 0V
–––
–––
250
IGSS
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
VGS = -16V
Qg
Total Gate Charge
–––
75
110
ID = 75A
Q gs
Gate-to-Source Charge
–––
28
–––
Q gd
Gate-to-Drain ("Miller") Charge
–––
40
–––
VGS = 5.0V
td(on)
Turn-On Delay Time
–––
19
–––
VDD = 20V
tr
Rise Time
–––
180
–––
td(off)
Turn-Off Delay Time
–––
30
–––
tf
Fall Time
–––
49
–––
VGS = 5.0V
LD
Internal Drain Inductance
–––
4.5
–––
Between lead,
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
–––
and center of die contact
VGS = 0V
VGS = 4.5V, ID
V
VDS = VGS, ID = 250μA
l
VDS = 40V, VGS = 0V, TJ = 125°C
nA
nC
VGS = 16V
ID = 75A
ns
nH
l
VDS = 32V
e
l
RG = 4.0Ω
e
D
G
S
Ciss
Input Capacitance
–––
5080
Coss
Output Capacitance
–––
970
–––
Crss
Reverse Transfer Capacitance
–––
570
–––
Coss
Output Capacitance
–––
3310
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
870
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
1280
–––
VGS = 0V, VDS = 0V to 32V
VDS = 25V
pF
ƒ = 1.0MHz
f
Source-Drain Ratings and Characteristics
IS
Parameter
Continuous Source Current
Min.
–––
Typ.
–––
Max.
200
ISM
(Body Diode)
Pulsed Source Current
–––
–––
790
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
p-n junction diode.
TJ = 25°C, IS = 75A
trr
Reverse Recovery Time
–––
26
39
ns
Q rr
Reverse Recovery Charge
–––
18
27
nC
ton
Forward Turn-On Time
c
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C,
L = 0.079mH, RG = 25Ω, IAS = 75A, VGS =10V.
Part not recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical
repetitive avalanche performance.
2
k
Units
A
Conditions
MOSFET symbol
D
G
TJ = 25°C, IF = 75A
di/dt = 100A/μs
e
S
l, V
l, V
e
GS
= 0V
DD
= 20V
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
This value determined from sample failure population. 100%
tested to this value in production.
This is only applied to TO-220AB package.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques
refer to application note #AN-994.
Calculated continuous current based on maximum allowable
junction temperature. Bond wire current limit is 120A. Note that
current limitations arising from heating of the device leads may
occur with some lead mounting arrangements.
All AC and DC test condition based on former Package limited
current of 75A.
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IRL1404Z/S/LPbF
1000
1000
VGS
10V
7.0V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
3.0V
60μs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
BOTTOM
100
3.0V
10
60μs PULSE WIDTH
Tj = 175°C
1
100
0.1
V DS, Drain-to-Source Voltage (V)
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
200
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
VGS
10V
7.0V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
T J = 175°C
100
10
T J = 25°C
VDS = 10V
60μs PULSE WIDTH
1.0
2
3
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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TJ = 25°C
150
100
T J = 175°C
50
V DS = 10V
0
10
0
50
100
150
200
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRL1404Z/S/LPbF
100000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 75A
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
C oss = C ds + C gd
10000
Ciss
Coss
1000
Crss
4.0
3.0
2.0
1.0
0.0
100
1
10
100
0
VDS, Drain-to-Source Voltage (V)
20
40
60
80
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000.00
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
VDS= 32V
VDS= 20V
5.0
T J = 175°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100.00
100
10.00
T J = 25°C
VGS = 0V
1.00
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
2.5
100μsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1404Z/S/LPbF
200
LIMITED BY PACKAGE
ID , Drain Current (A)
160
120
80
40
0
25
50
75
100
125
150
175
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.0
ID = 75A
VGS = 10V
1.5
1.0
0.5
TC , Case Temperature (°C)
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
τJ
SINGLE PULSE
( THERMAL RESPONSE )
0.001
R1
R1
τJ
τ1
τ1
R2
R2
τ2
R3
R3
τ3
τ2
Ci= τi/Ri
Ci i/Ri
τC
τ
τ3
Ri (°C/W) τi (sec)
0.000213
0.185
0.241
0.001234
0.227
0.021750
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1404Z/S/LPbF
900
DRIVER
L
VDS
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
15V
ID
16A
26A
BOTTOM 75A
800
TOP
700
600
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2μF
.3μF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
3.0
2.5
2.0
ID = 250μA
1.5
1.0
0.5
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRL1404Z/S/LPbF
Avalanche Current (A)
1000
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Δ Tj = 25°C due to
avalanche losses
Duty Cycle = Single Pulse
100
0.01
0.05
0.10
10
1
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
250
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
200
150
100
50
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRL1404Z/S/LPbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
V DD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
*
VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
V GS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRL1404Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN THE AS S EMBLY LINE "C"
Note: "P" in as sembly line position
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRL1404Z/S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
T HIS IS AN IRF530S WITH
LOT CODE 8024
AS SEMBLED ON WW 02, 2000
IN T HE ASS EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
F530S
DAT E CODE
P = DES IGNAT ES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASS EMBLY SIT E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRL1404Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE AS SEMBLY LINE "C"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMB ER
DAT E CODE
P = DESIGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS SEMBLY S ITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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11
IRL1404Z/S/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
3
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 101N.Sepulveda blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/2012
12
www.irf.com
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
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